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Achieving Signal and
Timing Requirements for
a DDR2 Based System
Kim Owen, Bruce Caryl
Application Engineers
Mentor Graphics
DDR2 Presentation Overview
DDR2 Technology Review
Planning DDR2 Topology and Entering
Constraints
Review Routing Guidelines
Verifying SI and Timing Margins Using the
Hyperlynx 8.0 DDR/2/3 Wizard
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DDR2 Overview
What is DDR2, anyway?
DDR2 = “Double-Data-Rate v2” synchronous
DRAM memory
Physically, it’s a source-synchronous technology
—
Small groups of data (or “byte lanes”) have their
own “private” clocks or strobes
Each 8-bit
lane gets its
own strobe
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DDR2 Overview
Data bandwidth is doubled by clocking data on
every edge of the strobe (rising and falling)
DDR2 is popular, because it’s cheap and fast:
©2003 Micron Technology, Inc. All rights reserved.
JEDEC spec supports 400, 533, 667, 800,
and 1066 Mbps
— x64 bits 8.528 GBps
—
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DDR2 Bus Architecture
©2003 Micron Technology, Inc. All rights reserved.
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New for DDR2 Technology
DDR2 Operating Speeds
—
—
DDR2-533 (266 MHz clock)
—
DDR2-667 (333 MHz clock)
—
DDR2-400 (200 MHz clock)
DDR2-800 (400 MHz clock)
Source-Synchronous
interface like original DDR
Recommended board
impedance is 50 ohms
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BC-KO, U2U, Nov 2008
DQS
DQS
DQ0
DQ0
DQ1
DQ1
DQ2
DQ2
Strobe
Strobe
Data
Data
Technical Background
DDR2 timing margins are so tight, signal-integrity
and timing calculations are critical
—
@ 800 Mbps rate, the bit period is only 1.25 ns
This means previous bits linger on the copper bus
even while later bits are being sent
An effect called “intersymbol interference” (ISI)
— Each bit’s shape and timing depends previous bits
—
Bits are interfering with each other
ISI, and therefore the shape of
each bit is different different
timing
There is no longer a single delay:
Every bit delay varies at least a little
on every clock cycle!
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BC-KO, U2U, Nov 2008
NEW: DDR2 Signaling – Example SSTL-1.8
VDDQ (1.8V nominal)
VOH(MIN)
VIHAC
1.150V
1.025V
VIH DC
0.9V
0.775V
VI L DC
0.650V
VIL AC
VOL (MAX)
Receiver
VSSQ
Transmitter
Slide 9
TM
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
NEW: DDR2 On Die Termination
ODT – On Die Termination
—
Built into the controller IC
and DDR2 SDRAM
—
Selectable resistor values
—
50 Ohm, 75 Ohm, 150 Ohm
ODT turns on / off depending
on Read or Write operation
* Courtesy of Micron
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New:
On Die Termination
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ODT Values must be chosen and specified for Simulation
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NEW: DDR2 Delay Measurement
Slew Rate affects switching time
Charge Model Simplification: The area under the curve
affects when the buffer switches
+ Dt
- Dt
Vih AC
2 V/ns
1 V/ns
0.5 V/ns
Vref
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Setup Nominal Slew Rate
New Measurement
Requirement
17
©2008 Micron Technology, Inc. All rights reserved.
Setup Tangent Line Slew Rate
New Measurement
Requirement
18
©2008 Micron Technology, Inc. All rights reserved.
Clock Derating Table
Derating can consume
50% of your Interconnect
Timing Budget!
tIS (total setup time) = tIS (base) + ΔtIS (derating)
tIH (total hold time) = tIH (base) + ΔtIH (derating)
19
©2008 Micron Technology, Inc. All rights reserved.
533 MBS DDR2 Write Timing Budget
Pre-Route planning
and constraint
management is
essential
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DDR2 Planning and Constraints
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DDR2 Design Guidelines
What results are important
—
We need to constrain 4 critical lengths
1. Net length from the controller to the 1st DIMM slot
2. Net length between DIMM slots
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BC-KO, U2U, Nov 2008
#1
VTT
#2
DIMM Slot 2
Memory
Controller
DIMM Slot 1
4. All DQS/DQ groups
should be length
matched to minimize
skew within the group
and across the channel
VDD
#3
VTT Pull-up Resistors
3. Net length from last
slot to the pull-up term.
(only Address/Command)
DDR2 Design Guidelines
Spacing Recommendations
—
—
Varies depending on stackup
Typically rules of thumb say 3H spacing
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BC-KO, U2U, Nov 2008
For a 5 mil dielectric this would be 15 mils
For signals coupled closely to reference planes,
often 1.5H can be used or ~8 mils
Mentor DDR2 Design Kit
Design kits for DDR2 are available online
through SupportNet
http://supportnet.mentor.com/reference/otherinfo/hyperlynx_designkits/downloads.cfm
Design kits include presentations and
example LineSim schematics with typical
DDR2 memory board topology
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BC-KO, U2U, Nov 2008
Key Signal Groups
Address/Command (A, BA, RAS#, CAS#, WE#)
—
—
Control (S#, CKE, ODT)
—
—
—
Differential , terminated on die with ODT
Data
—
Single ended, parallel, terminated to VTT (0.9V), registered on rising
edge of clock
Each bank has own control signal (less loading)
Must use 1T timing
Clocks
—
Single ended, parallel, terminated to VTT (0.9V), registered on rising
edge of clock
May use 2T timing if too heavily loaded
Single ended, bi-directional, synchronized to Data Strobes, terminated
on die with ODT
Data Strobes
—
Differential, bi-directional, terminated on die with ODT
—
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Can be single ended but differential more commonly used
One diff pair for each byte lane
DIMM Layout
Address/Command (A0)
Data (DQ0)
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DIMM Layout
Clock (CK0)
Data Strobe (DQS8)
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Power Supplies
Three power supplies are required
—
VDD 1.8 V Supply for I/O Drivers (SSTL1.8) and DRAM
core
—
VREF 0.9 volt switching reference voltage used by
DRAMs and controller
—
—
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BC-KO, U2U, Nov 2008
Critical value since all switching is referenced to VREF
Isolate and/or shield with ground
VTT 0.9 volt termination supply (1/2 VDD)
—
Controller core may have additional requirements
Use wide island trace area
+/- 2% AC noise
VTT = VREF +/- 40 mV
VREF and VTT should be properly decoupled
VREF is more sensitive to noise, so it cannot share the
VTT plane
Constraint Entry System (CES)
Use CES to fully constrain all important aspects of a
net
—
—
Trace width, impedance, layer, clearance, min/max delay,
matching, diff pair rules, etc.
Constrain one net in bus, create a constraint template,
apply template to all other nets in bus
Constraints are used by Auto Router and manual
routing
Constraints can be entered from schematic or layout
(synchronized during forward and back annotation)
—
—
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Allows engineering to create verifiable requirements
Ensures implementation matches requirements
Address/Command/Control Signals
Single ended, parallel bus architecture
Synchronized to memory clock
Switch on positive edge of clock
Terminated to VTT (0.9V)
Address/Command Can have heavy capacitive
loading (36 DRAMS in 2 DIMM configuration)
Control signals have separate signal for each
bank (1/4 the load in 2 DIMM configuration)
For DDR2-667 (333 MHz clock), Address
changes at 167 MHz max (1T Timing)
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Address Topology Simplified
Design File: A_A0_Constraints.ffs
HyperLynx LineSim V7.7
Model trace lengths, widths,
layers, termination, timing
Create constraints for layout
Use intended board stackup
VTT
0.9V
R21
Length of trace
between
connectors
Length of trace
to terminator
47.0 ohms
TL8
48.5 ohms
88.828 ps
0.600 in
A_A0
Stackup
TL9
48.5 ohms
88.828 ps
0.600 in
A_A0
X2.188
mt18htf 12872ay-6...
A0
DIMM modeled as EBD
(Electrical Board Desc.)
U1.F24
VIRTEX-4
SSTL18_II
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BC-KO, U2U, Nov 2008
X1.188
TL5
48.5 ohms
296.093 ps
2.000 in
A_A0
Length of trace
on PCB
mt18htf 12872ay-6...
A0
Address Simulation (1T Timing)
OSCILLOSCOPE
Design file: A_A0_CONSTRAINTS.FFS
HyperLynx V7.7
Designer: Bruce Caryl
V
V
V
V
1800.0
[U18.R8 (EBD-X1) (at pin)]
[U6.R8 (EBD-X1) (at pin)]
[U4.R8 (EBD-X1) (at pin)]
[U2.R8 (EBD-X1) (at pin)]
1600.0
1400.0
1200.0
V ol t ag e -mV -
1000.0
800.0
600.0
• 36 DRAM loads
• Waveforms at 4 DRAMS
• Marginal signal quality
• Limited timing budget
400.0
200.0
0.00
7.000
8.000
9.000
10.000
11.000
12.000
Time (ns)
13.000
14.000
Date: Friday Oct. 17, 2008 Time: 14:22:50
Show Latest Waveform = YES
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BC-KO, U2U, Nov 2008
15.000
Improving Address/Command Quality and
Timing
Provide a separate (duplicate) signal driver
for each DIMM at the controller
Use 2T timing to allow two clock cycles per
address change
Add a compensation capacitor for each signal
(18-27pF recommended)
—
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BC-KO, U2U, Nov 2008
Only recommended for > 18 memory chip
loads
Address Simulation (2T Timing)
OSCILLOSCOPE
Design file: A_A0_CONSTRAINTS.FFS
HyperLynx V7.7
Designer: Bruce Caryl
V
V
V
V
V
V
1800.0
1600.0
[U19.R8 (EBD-X2) (at pin)]
[U19.R8 (EBD-X1) (at pin)]
[U9.R8 (EBD-X1) (at pin)]
[U9.R8 (EBD-X2) (at pin)]
[U1.R8 (EBD-X2) (at pin)]
[U1.R8 (EBD-X1) (at pin)]
1400.0
1200.0
V ol t ag e -mV -
1000.0
800.0
600.0
• 36 DRAM loads
• Waveforms at 6 DRAMS
• Improved signal quality
• Ample timing budget
400.0
200.0
0.00
0.00
2.000
4.000
6.000
8.000
10.000
Time (ns)
12.000
14.000
16.000
Date: Friday Oct. 17, 2008 Time: 16:51:49
Show Latest Waveform = YES
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BC-KO, U2U, Nov 2008
18.000
Address Constraints
Controller to first DIMM max = 3200 th
First DIMM to second DIMM max = 650 th
Second DIMM to terminator max = 600 th
All Address lines matched to 200 th
All Address lines matched to CK_N0 to 5mm
(200 th)
Prevents clock-to-address skew
— Sometimes implemented as average of clock
lengths
—
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BC-KO, U2U, Nov 2008
Address Constraints in CES
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Command/Control Constraints in CES
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Clock Signals
Differential Signals
On die termination (ODT) is used
AC compensation cap recommended for
DIMMs
Three clock pairs per DIMM when using
unbuffered DIMMs
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BC-KO, U2U, Nov 2008
Clock Topology
Design File: DDR2_differential_clock.ffs
HyperLynx LineSim V7.7
R5
C3
200.0 ohms
1.5 pF
TL84
R4
dimm1
TL142
dimm1
42.2 ohms
21.799 ps
0.140 in
Coupled...
dimm1
200.0 ohms
rcv1_P rcv1_N
TL76
MT47...
CK
rcv3_P rcv3_N
rcv2_P rcv2_N
TL58
MT47...
CK
MT47...
CK
TL85
TL143
42.2 ohms
21.799 ps
0.140 in
Coupled...
49.4 ohms
55.070 ps
0.357 in
Coupled...
49.4 ohms
55.070 ps
0.357 in
Coupled...
TL77
42.2 ohms
21.799 ps
0.140 in
Coupled...
42.2 ohms
21.799 ps
0.140 in
Coupled...
TL59
42.2 ohms
113.669...
0.730 in
Coupled...
rcv4_P rcv4_N
42.2 ohms
21.799 ps
0.140 in
Coupled...
TL67
42.2 ohms
55.589 ps
0.357 in
Coupled...
42.2 ohms
113.669...
0.730 in
Coupled...
TL81
TL147
42.2 ohms
55.589 ps
0.357 in
Coupled...
49.4 ohms
55.070 ps
0.357 in
Coupled...
200.0 ohms
MT47...
CK
TL82
49.4 ohms
55.070 ps
0.357 in
Coupled...
TL60
TL65
42.2 ohms
21.799 ps
0.140 in
Coupled...
TL91
TL83
42.2 ohms
55.589 ps
0.357 in
Coupled...
TL62
42.2 ohms
155.710...
1.000 in
Coupled...
42.2 ohms
73.807 ps
0.474 in
Coupled...
42.2 ohms
73.807 ps
0.474 in
Coupled...
TL57
42.2 ohms
73.807 ps
0.474 in
Coupled...
Connector
TL45
53.0 ohms
45.000 ps
dimm2v-...
DIMM
TL47
53.0 ohms
45.000 ps
dimm2v-...
CLK_drv
P
N
VIRTEX-4
DIFF_SSTL_II_18_P
TL1
TL46
49.4 ohms
77.129 ps
0.500 in
Coupled Stackup
38.2 ohms
469.932 ps
3.000 in
Coupled Stackup
TL2
TL48
49.4 ohms
77.129 ps
0.500 in
Coupled Stackup
38.2 ohms
469.932 ps
3.000 in
Coupled Stackup
Breakout
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BC-KO, U2U, Nov 2008
42.2 ohms
55.589 ps
0.357 in
Coupled...
42.2 ohms
55.589 ps
0.357 in
Coupled...
TL61
TL56
Length of trace
on PCB
MT47...
CK
rcv6_P rcv6_N
TL86
42.2 ohms
73.807 ps
0.474 in
Coupled...
MT47...
CK
TL88
TL87
42.2 ohms
55.589 ps
0.357 in
Coupled...
TL63
42.2 ohms
155.710...
1.000 in
Coupled...
42.2 ohms
21.799 ps
0.140 in
Coupled...
rcv5_P rcv5_N
TL90
42.2 ohms
21.799 ps
0.140 in
Coupled...
TL64
42.2 ohms
21.799 ps
0.140 in
Coupled...
TL146
dimm1
R6
TL80
TL66
42.2 ohms
21.799 ps
0.140 in
Coupled...
dimm1
dimm1
42.2 ohms
155.710...
1.000 in
Coupled...
TL89
42.2 ohms
155.710...
1.000 in
Coupled...
Clock Topology with Vias and AC
Compensation
Design File: A_CK_N0.ffs
HyperLynx LineSim V7.7
RAM Model
TL3
U1.K19
V4FX100
CK_P<0>
U1.L19
V4FX100
CK_N<0>
TL2
TL6
67.1 ohms
3.968 ps
0.028 in
A_CK_P0
58.2 ohms
567.615 ps
3.304 in
A_CK_P0
TL4
67.1 ohms
3.968 ps
0.028 in
A_CK_N0
V1
V2
TL1
mt18htf12872ay-6...
CK0#
X2.185
1
5
1
67.5 ohms
6.926 ps
0.049 in
A_CK_P0
10
5
• Model via transitions
• Model of compensation cap
• Provide complete constraint data
• Lengths
• Route layers
• Via types
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BC-KO, U2U, Nov 2008
67.5 ohms
6.926 ps
0.049 in
A_CK_N0
X2.186
TL5
58.2 ohms
568.057 ps
3.307 in
A_CK_N0
TL7
67.2 ohms
5.510 ps
0.039 in
A_CK_N0
C6
TL8
4.7 pF
67.2 ohms
5.495 ps
0.039 in
A_CK_P0
mt18htf12872ay-6...
CK0
Clock Topology without AC Compensation
OSCILLOSCOPE
Design file: DDR2_DIFFERENTIAL_CLOCK.FFS
HyperLynx V7.7
Designer: Bruce Caryl
V
V
V
V
V
V
2500.0
2000.0
[dimm1.rcv6_P
[dimm1.rcv5_P
[dimm1.rcv4_P
[dimm1.rcv3_P
[dimm1.rcv2_P
[dimm1.rcv1_P
(at
(at
(at
(at
(at
(at
pin)
pin)
pin)
pin)
pin)
pin)
/
/
/
/
/
/
dimm1.rcv6_N
dimm1.rcv5_N
dimm1.rcv4_N
dimm1.rcv3_N
dimm1.rcv2_N
dimm1.rcv1_N
1500.0
1000.0
V ol t ag e -mV -
• Waveform at all receivers
• No compensation cap
• Multiple transitions on rcv6
• Poor overall signal quality
500.0
0.00
-500.0
-1000.0
-1500.0
-2000.0
0.00
4.000
8.000
12.000
Time (ns)
16.000
Date: Thursday Oct. 2, 2008 Time: 16:55:23
Show Latest Waveform = YES
44
BC-KO, U2U, Nov 2008
(at
(at
(at
(at
(at
(at
pin)]
pin)]
pin)]
pin)]
pin)]
pin)]
Clock Topology with AC Compensation
OSCILLOSCOPE
Design file: DDR2_DIFFERENTIAL_CLOCK.FFS
HyperLynx V7.7
Designer: Bruce Caryl
V
V
V
V
V
V
2500.0
2000.0
[dimm1.rcv6_P
[dimm1.rcv5_P
[dimm1.rcv4_P
[dimm1.rcv3_P
[dimm1.rcv2_P
[dimm1.rcv1_P
(at
(at
(at
(at
(at
(at
pin)
pin)
pin)
pin)
pin)
pin)
/
/
/
/
/
/
dimm1.rcv6_N
dimm1.rcv5_N
dimm1.rcv4_N
dimm1.rcv3_N
dimm1.rcv2_N
dimm1.rcv1_N
1500.0
1000.0
V ol t ag e -mV -
• Waveform at all receivers
• 10pF compensation cap
• Good signal quality
• Clean transitions
500.0
0.00
-500.0
-1000.0
-1500.0
-2000.0
0.00
4.000
8.000
12.000
Time (ns)
16.000
Date: Thursday Oct. 2, 2008 Time: 16:52:06
Show Latest Waveform = YES
45
BC-KO, U2U, Nov 2008
(at
(at
(at
(at
(at
(at
pin)]
pin)]
pin)]
pin)]
pin)]
pin)]
Clock Constraints
Controller to DIMM max = 3900 th
DIMM to AC compensation max = 600 th
Clock diff pair match = 25 th
“Clock Differential Pairs” Net Class
—
Inner Layer Routing (layers 3, 5)
—
4 mil trace width with 4 mil spacing
Often specified to be routed on same layer
Coupling may vary based on stackup
100 ohm differential impedance
46
BC-KO, U2U, Nov 2008
Clock Constraints in CES
47
BC-KO, U2U, Nov 2008
Data (DQ) Signals
Single ended nets
On die termination (ODT) is used
Must be matched tightly to data strobes (DQS)
Must be matched between byte lanes (8 bit groups)
For write operation:
—
—
DIMM receiving data is set to 150 ohm ODT
DIMM not receiving data is set to 75 ohm ODT
For read operation
—
—
—
48
BC-KO, U2U, Nov 2008
Controller is set to 150 ohm ODT
DIMM supplying data is set to open
DIMM not supplying data is set to 75 ohm ODT
Data (DQ) Topology
Design File: DDR2_single_ended_data.ffs
HyperLynx LineSim V7.7
dimm1.front
TL38
51.4 ohms
17.583 ps
0.118 in
Coupled Stackup
R1
TL21
22.0 ohms
60.5 ohms
150.677 ps
1.024 in
Coupled Stackup
MT47H128M4FT_1...
DQ0
dimm1.back
TL34
51.4 ohms
17.583 ps
0.118 in
Coupled Stackup
MT47H128M4FT_1...
DQ0
TL13
DIMMs
TL40
60.5 ohms
33.613 ps
0.228 in
Coupled...
51.4 ohms
17.583 ps
0.118 in
Coupled Stackup
TL6
dimm2.front
MT47H128M4FT_1...
DQ0
53.0 ohms
45.000 ps
dimm2v-...
DQ.drv
VIRTEX-4
SSTL18_II
TL43
TL2
TL8
65.0 ohms
200.000 ps
Simple
51.4 ohms
596.031 ps
4.000 in
Coupled Stackup
51.4 ohms
63.328 ps
0.425 in
Coupled Stackup
testload.drv
R5
25.0 ohms
VIRTEX-4
SSTL18_II
49
BC-KO, U2U, Nov 2008
TL27
22.0 ohms
60.5 ohms
150.677 ps
1.024 in
Coupled Stackup
TL42
dimm2.back
TL25
TL23
Vt1
0.9V
R3
53.0 ohms
45.000 ps
dimm2v-DIMM2VL
60.5 ohms
33.613 ps
0.228 in
Coupled...
51.4 ohms
17.583 ps
0.118 in
Coupled Stackup
MT47H128M4FT_1...
DQ0
Data (DQ) Simulation
OSCILLOSCOPE
Design file: DDR2_SINGLE_ENDED_DATA.FFS
HyperLynx V7.7
Designer: Bruce Caryl
V [dimm1.front (at pin)]
1400.0
1300.0
1200.0
1100.0
V ol t ag e -mV -
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
Time (ps)
1600.0
Date: Friday Oct. 3, 2008
50
BC-KO, U2U, Nov 2008
1800.0
Time: 11:09:20
2000.0
2200.0
• Waveform DIMM1 front, write
• DIMMS set to 150 ohm ODT
• No eye opening
Data (DQ) Simulation
OSCILLOSCOPE
Design file: DDR2_SINGLE_ENDED_DATA.FFS
HyperLynx V7.7
Designer: Bruce Caryl
V [dimm1.front (at pin)]
1400.0
1300.0
1200.0
1100.0
V ol t ag e -mV -
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
Time (ps)
1600.0
1800.0
Date: Friday Oct. 3, 2008 Time: 11:12:32
Cursor 1, Voltage = 652.5mV, Time = 885.7ps
Cursor 2, Voltage = 652.5mV, Time = 1.5648ns
Delta Voltage = 0.000V, Delta Time = 679.2ps
51
BC-KO, U2U, Nov 2008
2000.0
2200.0
• Waveform DIMM1 front, write
• DIMM2 set to 75 ohm ODT
• DIMM1 set to 150 ohm ODT
• 680 ps eye opening, 3% jitter
Data (DQ) Constraints
Controller to DIMM max = 3900 th
DIMM X1 to DIMM X2 max = 650 th
Match to all other DQ signals in byte lane
—
Match to corresponding DQS
—
Tolerance = 100 th
“DQ Data” Net Class
—
Tolerance = 100 th
Can be layer restricted
Due to matching with DQS, DQ is also matched to
CK_N0 +/- 25 mm (1 inch)
—
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Results in Byte Lanes matching to 1 inch
Data (DQ) Constraints in CES
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Data Strobe (DQS) Signals
Differential signals
On die termination (ODT) is used
Must be matched tightly to associated data
group
—
Data is clocked in on both edges
Must be matched between byte lanes (8 bit
groups)
Must be matched to Clocks within +/- 25 mm
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Data Strobe DQS Topology
Design File: ddr2_dqs_differential.ffs
HyperLynx LineSim V7.7
TL38
TL40
dimm1
51.3 ohms
front+
17.548 ps
0.118 in
Coupled Stackup
front-
TL37
MT47H128M4FT
DQS#/NU
R1
TL21
22.0 ohms
60.1 ohms
149.568 ps
1.024 in
Coupled Stackup
TL13
60.1 ohms
33.365 ps
0.228 in
Coupled...
TL6
53.0 ohms
45.000 ps
dimm2v-...
51.1 ohms
889.404 ps
6.000 in
Coupled Stackup
controller
+
VIRTEX-4
DIFF_SSTL_II_18_P
25.0 ohms
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BC-KO, U2U, Nov 2008
22.0 ohms
60.1 ohms
149.568 ps
1.024 in
Coupled Stackup
51.3 ohms
17.548 ps
back+
0.118 in
Coupled Stackup
TL33
51.3 ohms
17.548 ps
0.118 in
Coupled Stackup
TL14
60.1 ohms
33.365 ps
0.228 in
Coupled...
25.0 ohms
TL27
22.0 ohms
60.1 ohms
149.568 ps
1.024 in
Coupled Stackup
R4
TL42
TL28
TL25
back-
60.1 ohms
33.365 ps
0.228 in
Coupled...
TL26
22.0 ohms
60.1 ohms
33.365 ps
0.228 in
Coupled...
60.1 ohms
149.568 ps
1.024 in
Coupled Stackup
TL23
TL24
53.0 ohms
45.000 ps
dimm2v-...
TL10
51.3 ohms
17.548 ps
back+
0.118 in
Coupled Stackup
TL41
dimm2
backMT47H128M4FT_1...
DQS
51.3 ohms
17.548 ps
0.118 in
Coupled Stackup
53.0 ohms
45.000 ps
dimm2v-...
TL8
DIMM
51.1 ohms
62.999 ps
0.425 in
Coupled Stackup
R6
R3
dimm1
MT47H128M4FT
DQS#/NU
51.1 ohms
889.404 ps
6.000 in
Coupled Stackup
VIRTEX-4
DIFF_SSTL_II_18_N
TL22
TL9
R5
MT47H128M4FT_1...
DQS
TL34
TL4
U6
front51.3 ohms
17.548 ps
0.118 in
Coupled Stackup
51.1 ohms
62.999 ps
0.425 in
Coupled Stackup
Vt1
0.9V
+
51.3 ohms
17.548 ps
0.118 in
Coupled Stackup
R2
53.0 ohms
45.000 ps
dimm2v-...
TL2
dimm2
51.3 ohms
17.548 ps
front+
0.118 in
Coupled Stackup
TL39
DIMM Connectors
Data Strobe (DQS) Simulation
OSCILLOSCOPE
Design file: DDR2_DQS_DIFFERENTIAL.FFS
HyperLynx V7.7
2500.0
Designer: Bruce Caryl
V [dimm2.back+ (at pin) / dimm2.back- (at pin)]
V [dimm1.back+ (at pin) / dimm1.back- (at pin)]
V [controller.+ (at pin) / controller.- (at pin)]
2000.0
1500.0
1000.0
V ol t ag e -mV -
500.0
0.00
-500.0
-1000.0
• Controller, DIMM1 and DIMM2
-1500.0
-2000.0
4.000
6.000
8.000
10.000
Time (ns)
12.000
Date: Friday Oct. 3, 2008 Time: 11:49:14
Show Latest Waveform = YES
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Data Strobe (DQS) Constraints
Controller to DIMM max = 3940 th
DIMM X1 to DIMM X2 max = 650 th
Match to all DQ signals in corresponding Byte Lane
—
“DQS Differential Pairs” Net Class
—
—
Tolerance = 100 th
Layer restricted to 3 and 5
4 mil trace width with 4 mil spacing
Due to matching with DQ, DQS is also matched to
CK_N0 +/- 25 mm (1 inch)
—
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BC-KO, U2U, Nov 2008
Results in Byte Lanes matching to 1 inch
Data Strobe (DQS) Constraints in CES
59
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Routing Guidelines
60
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DDR2 Routing
Auto Route methodology
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Tuned Clock Route Example
Routed board using Auto Route methodology
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Some Routing Guidelines
Place critical delays on pin pairs, since “trace length”
in CES is actually the sum of all copper on net
Pin pairs will include pin package lengths (set in
CES), and series elements
—
Typically constrain both sides of series element separately
Add virtual pins using Netline Manipulation in
Expedition, or Virtual Pins in CES
—
Pin pairs can be defined from virtual pins to components
Useful for specifying stub length from trace to component or for
balanced topologies
Perform pin swapping within byte groups to improve
routing
If Memory Controller is an FPGA, I/O Designer can improve
route-ability by improving pin position
Auto-route by classes, one class at a time
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More Routing Guidelines
Freescale recommended route order
— 1. Route data
— 2. Route address/command
— 3. Route control
— 4. Route clocks
— 5. Route power
Route each data group (8 bits of DQ, DQS, DM) on the
same layer
Keep data groups away from control and address
signals to minimize crosstalk
Route all signals over reference planes
Route longest trace first in matched groups
Isolate and protect VREF from noise
Manufactures provide more details…
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BC-KO, U2U, Nov 2008
Post Route Analysis for SI and Timing
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Tips for DDR2 setup:
Perform usual BoardSim setup
—
Perform DDR Wizard setup
Interactively probe one net of each type
—
Seven Habits for Highly Successful HyperLynx
data, addr, clk, dqs, cntrl
Find and fix
Model problems
— Set up problems
— Signal Quality problems
—
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Clocks at Receiver Die, Slow
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Address Lines, Fast
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Address Lines, Slow
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Address Lines, Slow, Full Strength
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DQ0 Write @ Receiver, Fast and Slow
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Analyzing DDR2 Timing
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DDR2: The Bad News for SI Simulation
Thorough DDR2 SI measurement is nearly
impossible to do manually!
—
Input buffer hysteresis
complicates SI measurements
—
Programmable ODT and Buffers
Create dozens of new simulation cases
—
Logic switching times change with waveshape
Requires time consuming, manual measurements
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DDR2: The Bad News for Timing Closure
DDR2 timing measurements are much more
complex than previous timing measurements
—
Source-synchronous technology requires
measurement of multiple nets, not individual nets
—
ISI requires setup and hold times to be measured
on multiple clock edges
—
Data + strobes, addr/comm/ctrl + clocks, strobes+clocks
And on every strobe edge (rising and falling) for data
Set up and Hold times must be adjusted for slew
rates that differ from a nominal 1 V/ns
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Example Timing Budget for DDR2 RDIMM
•Register clock to output is determined from the Simulation
•Helps in getting more accurate timing budget
Timing Budget
Description
Clock Period
Measured Delay: Clock to Actual Load
Simultaneous Switching Adder
*Cross Talk Adder
Intersymbol Interference
Clock Skew
Register Clock Shift
DRAM Setup/Hold (derating values)
Derating
* Register Clock Offset
Margin (worst case corners)
Symbol Setup(ps) Hold(ps)
tCLK
3000
N/A
tPD
-2113
1513
Reg_Clk at Vref to Receiver at AC / DC
tSS
-200
N/A
Register Spec
tXTALK
-50
-50
Estimated for non-XTALK SIMM
tISI
N/A
N/A
Included in tPD
tSKEW
-150
-130
PLL jitter/skew + PCB clk skew
tREG
-100
-100
Register clock input skew
tISb/tIHb
-200
-275
DRAM Spec @ ac/dc thresholds
-100
-94
0
0
As needed to help setup or hold
tM
87
79
©2006 Micron Technology, Inc. All rights reserved.
BC-KO, U2U, Nov 2008
864
Unit: ps
DDR2: The Good News for Simulation
Hyperlynx 8.0 DDR/2/3 Wizard Automatically
Determines DDR2 SI and Timing Margins
Performs Multi-Cycle source-synchronous timing
measurements
— Drives batch simulations with PRBS stimulus over
all corners
— Automatically performs Write/Read ODT (on-dietermination) settings
— Automatically computes DDR2 slew de-rating
— Exhaustive Timing Margin calculations
— Automatic report generation in Excel
—
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DDR2: The Good News for Simulation…
HyperLynx v8.0 DDR/2/3 Wizard
DDR Wizard is based on a Set-Up Checklist:
Includes a left-side
contents list
Easy to jump to only a
few specified pages…
…and provides built-in
“context” visibility
83
BC-KO, U2U, Nov 2008
Assign Memory Controller and Data Rate
84
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Assign IBIS Models
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Specify ODT Buffer Activation
89
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Choose Simulation Options
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Choose Run and Report Options
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BC-KO, U2U, Nov 2008
Tips for DDR2 setup:
Run a batch audit and simulation with a few nets of
each type
—
data, addr, clk, dqs, cntrl
Audit will quickly locate these problems:
Missing IBIS-model assignments
Broken signal paths
—
Correct reference-designator mappings
—
For example, DRAMs called “REGx…” resistor
Incorrect DIMM HYP file used
—
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BC-KO, U2U, Nov 2008
Due to missing resistor-pack models, etc.
Main board clock connecting to a DIMM address line, etc.
Automatic Simulation Pre-Check
For most errors,
double-clicking will
jump to the wizard
page
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BC-KO, U2U, Nov 2008
Tips for DDR2 setup:
Watch for problems in IBIS models
—
The Wizard is good, but not all powerful
DDR2 strobes can be single-ended or differential; some
IBIS models force manual editing to make this selection
—
Some x8 DRAMs allow the data mask bit to be used
instead as an extra strobe (“RDQS”) during read
operations
May require more manual changes in the IBIS file
—
—
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In the [Diff_Pin] section
Model Selector
Additional IBIS thresholds
DDR2 Wizard Output Reports
DDR2 output reports / files:
DDR2 Batch
Engine
.LOG file
.XLS report
.XLS report
.XLS report
.XLS report
.XLS
.CSV report
waveform
(optional)
Details about every
operation in the
run; reports any
problems
encountered
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Optionally, every single
waveform created
during simulation;
sufficient for
reproducing all timing
measurements
manually
Comprehensive
output reporting!
- including clearly
formatted Excel
spreadsheets
All files go into a
sub-directory
below the HYP dir,
with a timestamped name
- like
“DDR_Results_Aug.-42008_18h-32m”
DDR2 Signal Integrity Results
Signal distortion at receiver
100
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DDR2 Hold Timing Margin Report
102
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Summary
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Summary
DDR2 presents significant new technical
challenges to designers
Planning and defining constraints is critical
to achieving a successfully routed board
Simulate pre-route to validate constraints
Exhaustive post-route analysis ensures that
timing requirements are met
Mentor board products can help achieve
reliable DDR2 designs
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Credits and Acknowledgements
DDR1/DDR2 Memory Systems Design (AN138), Steve
Foster, Freescale Semiconductor, 2006
DDR2 and DDR3 Challenges, Randy Wolff, Micron
Technology, 2008
DDR2 Technology Workshop, Steve McKinney & Pat
Carrier, Mentor Graphics, 2006
HyperLynx v8.0 DDR2 Simulation, Steve Kaufer, Mentor
Graphics, 2008
JESD8-15A, JEDEC Solid State Technology Assn, 2003
Slew Rate De-rating in IBIS, Randy Wolff, Micron
Technology, 2008
TN-47-01 DDR2 Design Guide for Two-DIMM Systems,
Micron Technology, 2004
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