Transcript Document

Performance estimates for the various types of
emerging memory devices
Victor Zhirnov (SRC) and Ramachandran Muralidhar (Freescale)
Rationale

We seek to identify fundamental physical limits for
various types of memory devices

Best projections for scaling

e.g. “no consolidated theory has been developed for Flash
scaling
Flash Memories,
P. Cappelletti et al
(Eds), Kluwer 2001
2
Attributes of an ideal memory







Nonvolatility with long retention (e.g.. > 10 years)
High density
Low power
In-system rewrittability
Fast read/write
High endurance (the number of erase/write/read cycles)
Integration with CMOS logic:


Matching operational voltage
Matching time (speed)
Focus of
this talk
3
Three Components of Memory Device

Three equally important components of memory
systems:

Focus of this
analysis


Memory cell (Physics of of Write/Erase/Program)
Sensing (Physics of Read/Sense)
“Wires” (implication of the physics of Write and Read to
accessibility)
The key of a cell’s usefulness is whether the cell can be written
to and read from without affecting the surrounding cells.
4
ERD ITWG Memory Discussion
10:45
Quantitative estimates of performance for the various
types of memories
Engineered barrier
Ferroelectric
Nanoelectromechanical
Fuse/Antifuse
Muralidhar and Zhirnov
Waser
Zhirnov
Waser and Akinaga
12:00-12:30
Ionic
Electronic Effects
Macromolecular
Molecular
1:30
Lunch
Waser and Akinaga
Waser and Zhirnov
Zhirnov
Waser
Break - Adjourn Memory Discussion
5
Charge-based Memories
DRAM/SRAM
A
e-
B
Floating Gate Memory
SONOS
Control
Requirements:
1) Efficient charge injection during programming
2) Suppressed back-flow of charge in store/read modes
3) Efficient erase
4) Min. charge/bit: q=e=1.6x10-19 Q
6
Barrier-less Ohmic Transport: The
most efficient injection, but…
Write
I AB ~ V
… difficult retention
Store
Eb
Charge-based memory is a two-barrier system
Example:
DRAM
What is the minimum barrier height for the chargebased NVM?
7
What is the minimum barrier height
for the charge-based NVM?
Thermionic leakage
current (ideal case):
Store
 E 
J th  J th0  exp  b 
 kT 
Eb, eV Max. retention
0.7
80 ms
0.9
28 s
1.1
2.5 h
1.3
1 month
1.5
31 years
Eb
High-barrier are needed for
Non-volatile memory
Ebmin
Problem: In Si devices Ebmax<Eg=1.1 eV
Min. barrier
height for NVM
8
Charge injection problem in highbarrier systems
High-barriers are needed for Non-volatile
memory
BUT: Barrier formed by an insulating material (large Eb)
cannot be suppressed) – charge transport in the presence of
barriers: Non-ohmic charge transport
Hot-electron injection
Tunneling
Newly proposed nanomechanical DRAM
addresses this problem
9
Two-barrier charge-based NVM
Floating gate memory
C. Y. Chang, S. M. Sze (Eds.), “ULSI
Devices” (John Wiley & sons 2000)
SONOS memory
M. H. White,Y. Yang, A. Purwar, and M. L. French,
IEEE Trans. Compon. Packag. and Manufact. Technol.—
Pt A 20 (1997) 190
10
Floating gate memory:
WRITE and STORE modes
‘0’
FET
channel
Control
gate
Floating
gate
WRITE
q CV
tw  
I
I
V
tret
STORE
leakage
q CV
 
I
I
V
11
We need to create an asymmetry in charge transport
through the gate dielectric to maximize the Iwrite/Iret ratio
Floating gate cell:
Write – triangle barrier
Retention – trapezoidal barrier
V
t~
1
TF  N

a  Eb3 2 

~ exp  C1 
V 

tret ~

1
~ exp C2  a 
TDT
Eb

The asymmetry in charge transport between WRITE and
STORE modes is achieved through different shape of
barrier (triangle vs. trapezoidal)
12
Floating Gate Cell Retention and WRITE
characteristics
Retention: direct tunneling
kBT/e <Vstored<Eb
Write: F-N tunneling:
Eb
VF-N>Eb
VF-N
VW
a
The retention time strongly
depends on thickness
Ideal case
VW min  2  VF  N  2Eb
Si/SiO2: Eb=3.1 V, VWSiO2>6.2 V
For lower WRITE voltage Eb should
be decreased:
Ebmin=1.5 eV
a
Barrier
Eb
V Ret
t Ret
Si/SiO2 3.1 eV 2 V
4 nm 4.35 min
Si/SiO2 3.1 eV 2V 5.4 nm 20 y
Min. barrier 1.5 eV 0.025 V 6.3 nm 11 y

Vmin>3 V
Barrier
Eb V WR
a
t WR
Si/SiO2 3.1 eV 6.8 V 5.4 nm 1h
Si/SiO2 3.1 eV 12 V 5.4 nm 30ms
Min. barrier 1.5 eV 4 V 6.3 nm 5ms
13
The Industry Standard Flash Memory Cell
Flash Memories,
P. Cappelletti et al
(Eds), Kluwer 2001
14
Parameters Projections for n-FG

This Analisis SiO2,
 Eb=3.1eV
 Vmin>6.8 V (slow operation)
 V~12 V (ms operation)
 amin>5.4 nm (reliability issue)
 Lmin>15 nm (gate stack AR,
FET issues…)

Standard FLASH SiO2
 Eb=3.1eV
 Flash Memories,
 10-20 V
P. Cappelletti et al
 ~6 nm
(Eds), Kluwer 2001
 ~18 nm
High-K !

‘Optimized’ FG memory cell
 Eb=1.5 eV HfO2
 Vmin>3 V (slow operation)
 V~4 V (ms operation)
 amin~6.3 nm
 Lmin~12 nm
Nanocrystals,
Charge trapping
15
Parameters Projections for n-FG
Cmin
2 0L2
~
a
QFG  CVFG
SiO2
~2x10-18 F
Eb
~C
2e
Q
N el 
e
Emin ~ Nel  Eb
HfO2
~6x10-18 F
Statistical issue
30
1.43x10-17 J
30
7.2x10-18 J
Lower bound (slow operation)
V~12 V (ms operation)
3x10-16 J
16
Materials Challenges of symmetrically graded
barrier : fB
vs. K
fB  Eoffset  Eg
C1
C2
K  1 2  1 2
Eg
f
K1 <K2
f1< f2
Dielectric constant, K
=0.2-0.5
100
90
80
70
60
50
40
30
20
10
0
Kramers-Kronig relation
TiO2
BaZrO3
HfO2
ZrO2
La2O3
Ta2O3
1
Al2O3
Sc 2O3
Gd2O3
0
Y2O3
2
Si3N4
3
4
5
6
Diamond
GdF2
7
8
ZrSiO2
MgO
9
BaF2
CaF2
SiO2
SrF2
10 11 12 13
LiF
14
15
Bandgap, Eg (eV)
17
Symmetrically graded (crested)
barrier
Uses a stack of insulating materials to create
a special shape of barrier enabling effective
transport into/from the storage node
Vw~8 V
(x)
jj(x)
0.5
1.5
2.5
2
-6
-4
-2
-6
-4
-2
-6
-4
-2
-6
-4
-2
0
1
1.5
2
-0.5
0.5
1
-1
1.5
0
-1.5
0.5
-2
-0.5
1
0
-2.5
-1
0.5
-3
-0.5
-1.5
-3.5
0
-1
-2
-4
0
2
4
6
0
2
4
6
0
2
4
6
0
2
4
6
-4.5
-2.5
-0.5
-1.5
V=2*E
V=2
V=0 V b=4 V
V=1
X
X
EbbE=1.5
=1
VV
=0
b=2
Likharev, K.K., Single-electron devices and their
applications, Proc. IEEE 87 (1999) 606-632
18
Engineered tunnel barrier memory
Likharev
19
Charge injection problem in highbarrier systems
14
Ehei ~ 4  Emin / ~ 2 10
eV
More accurate estimates based on
Shockley’s lucky electron model TBD
Hot-electron injection
20
Summary on Floating Gate Memory


Operation voltage cannot be small (e.g. V>6 V for
Si/SiO2)
V-t dilemma
Question: How to reduce the write voltage for the
tunneling based memories?
Answer:
To
perform write operation in direct tunneling mode

In principle, the voltage can be as small as wished

There are two problems though:
1)
Very slow writing
2)
Very small retention
21
SONOS
For lower voltage operation of floating charge memory, direct tunneling
needs to be used for charge injection.
Tunnel insulator must be very thin for reasonably small WRITE time
We now have a problem of of how to create the asymmetry between
WRITE and STORE charge transport paths
M. H. White,Y. Yang, A. Purwar, and M. L. French, IEEE Trans. Compon. Packag.
and Manufact. Technol.—Pt A 20 (1997) 190
22
SONOS : Write and Retention
Retention:
Write: Direct tunneling:
Vtun<3.1 V, awrite=d1
t~

1
~ exp C2  a 
Td t
Eb

aret
aret>awrite
The asymmetry between WRITE and STORE charge
transport paths is achieved by different path length
d1
d2
X. Wang, et al,
IEEE Trans. El.
Dev. 51 (2004) 597
Vw  Vtun
BUT: We now have a problem of of how to create the
symmetry between WRITE and ERASE operations
d3
Barrier
Eb V tun d1
d2
d3 V write
Si/SiO2
3.1 eV 2 V 2 nm 10 nm 4 nm 11 V
"Minimum barrier" 1.5 eV 1 V 2 nm 10 nm 4 nm 5.5 V
d1  d3  d 2 ( K SiO2 / K Si3 N4 )
d1
 5 Vtun
Retention??
?
t write
>1 s
>2 ns
23
Solutions to improve characteristics
of charge-trapping memory?
X. Wang, et al, IEEE Trans.
El. Dev. 51 (2004) 597
HfO2
Ta2O5
HfO2


Alternative dielectrics, e.g. with lower barrier height,
high K
ERM
Is it possible to control/engineer the trap sites in silicon
nitride: concentration, distribution, position, energy levels?
24
Conclusion on ultimate chargebased memories

All charge-based memories suffer from the “barrier”
issue:


High barriers needed for long retention do not allow fast
charge injection
It is difficult (impossible?) to match their speed and voltages
to logic

Voltage-Time Dilemma
Non-charge-based NVMs?
25
Electronic Effects
Electronic Effects Memory

1) Charge injection and trapping



Simmons and Verderber, “New conduction and reversible
memory phenomena in thin insulating films”
2) Mott transition
3) Ferroelectric polarization effects.
27
Simmons-Verderber theory

Unipolar/non-polar switching


Charging trapes in insulator
I
‘Forming process’ is critical

Strongly suggestive of positive ion injection into insulator
2 ns
100 ns
Write
Erase
28
Energy Diagram, V=0
29
Energy Diagram, V>0
V<f0 (energy of localized levels)
V>f0 (energy of localized levels)
30
Memory effect: Charge injection
31
Memory effect: Charge travel
32
Memory effect: Charge storing
33
Memory effect: Charge erase
1 ~ 
1
L
t sw ~  1 
2s
34
Switching (Erase) time estimate
Quantum harmonic Oscillator
h2
E
8m s2
2
4m s

h
 2 2m

 ~ exp 
s Etrap  E 




N
s~
2
1
3
N~1019 cm-3
s~2 nm
Etrap~1 eV
35
Switrching time
1 ~  ~ 30ns
1
L
t sw ~  1 
~ 130 ns
2d
t ~ as2 exp(bs) ~ aN

2
3
1

 
exp  bN 3 




36
Thickness scaling
Lmin  2


L
~2
 0
eN
N~1019 cm-3
~9 nm
Lmin~20nm
37
Scaling limits depend on materials
properties

N
s~
2
~2
1
3
N~1019 cm-3
 0
eN
~9 nm
Etrap~1 eV
s~2 nm
Lmin  2
Lmin~20nm
t ~ L  aN

2
3
1

 
exp  bN 3 




tmin~60ns
38
Macromolecular Memory

Polymer memory
Organic memory

Different mechanisms proposed





Filaments
Ionic
Charged traps in polymer etc
Verbakel et al. “Reproducible resistive switching in
nonvolatile organic memories”, APL 91 (2007)

“Resistive switching in organic memories can be due to the
presence of a native oxide layer at an aluminum electrode”
39