Transcript Slide 1

Five Components of a Computer
Input
Devices
keyboard,
mouse
CPU
Main
Memory
Secondary
Memory
Output
Devices
display screen,
printer
harddisks, floppy disks,
tapes, CD-ROMs
CPU - Central Processing Unit fetches and follows a set of simple
instructions
Main Memory stores the executing program and its data in RAM
( random access memory )
Secondary Memory stores permanent records ( files )
Two Principal Microcomputer System Components
• Hardware
• Software
Hardware: Architecture of a computer - general layout of major Components
BUS
Memory
System
BUS
Microprocessor
(CPU)
Random Access Memory (RAM)
Dynamic, Static
Cache, Flash Memory
Read Only Memory (ROM)
8088/8086
80286, 80386
80486, Pentium
I/O System
Printer, Mouse, DVD
Floppy/Hard Disk
CD, USB, keyboard
Monitor, Tape Backup
System Block Diagram
•Crystal oscillator
•Timing circuitry
(counters dividing to
lower frequencies)
Timing
P +
associated
logic
circuitry:
•Bus controller
•Bus drivers
•Coprocessor
CPU
•ROM (Read Only Memory) (start-up
program)
•RAM (Random Access Memory)
•DRAM (Dynamic RAM) - high capacity,
refresh needed
•SRAM (Static RAM) - low power, fast,
easy to interface
Memory
System bus (data, address & control signals)
Parallel I/O
Many wires, fast.
•Printer (high resolution)
•External memory
•Floppy Disk
•Hard Disk
•Compact Disk
•Other high speed devices
Serial I/O
Simple (only two wires
+ ground) but slow.
•Printer (low resolution)
•Modem
•Operator’s console
•Mainframe
•Personal computer
Interrupt circuitry
At external unexpected events, P
has to interrupt the main program
execution, service the interrupt
request (obviously a short
subroutine) and retake the main
program from the point where it
was interrupt.
The Personal Computer
Speaker
Timer logic
(8253)
Processor
(8086 / 8088
trough
Pentium)
Coprocessor
(8087
trough
80387)
System
ROM
640KB
DRAM
System bus (data, address & control signals)
Keyboard
logic (8253)
Keyboard
DMA
Controller
(8237)
Expansion
logic
Video card
Disk controller
Serial port
...
Extension slots
Interrupt
logic (8259)
Parts of the Central Processing Unit
CPU
Instruction
(Input)
ALU
Result
(Output)
Control
Unit
ALU – Arithmetic and Logic Unit performs mathematical operations
Control Unit coordinates all of the computer’s operations
CPU performs the fetch/decode/execute cycle
Fetch: Control Unit fetches next instruction
Decode: Control Unit decodes instruction
Execute: instruction is executed by appropriate component
High-level languages: designed to be easy for
humans to read and to write programs in, but too
complicated for the computer to understand
Z=X+Y
Low-level languages: consist of simple instructions
which can be understood by the computer after a
minor translation
ADD X Y Z
Machine Language: written in the form of zeros and
ones, can be understood directly by the computer
0110 1001 1010 1011
Evolution of Microprocessors
Computers “generations”
• First generation
ENIAC (vacuum tubes)
• Second generation
(transistors)
• Third generation
(IC - SSI, MSI)
• Fourth generation
(LSI)
• Fifth generation
can think?
Microprocessors
MSI
Intel® 4004™, 8008™
LSI
Intel® 8080™, Zilog® Z80™, Motorola® 6800™
•
8 bit data bus, 16 bit address bus (64kbyte=65536 byte of
•
addressable memory), no multiply and divide instructions
•
VLSI
32…64 bit data bus, 2-300MHz clock, RISC concept
Hardware Terms & Functionality
• CPU: Performs all arithmetic & logical operations
• Memory: Used to store programs & data. Is divided into
individual components called addresses
• Input/Output (I/O) devices: allow communication with the
“real” world
• Mass storage: means of permanently storing programs
and/or data
• System bus: Means by which other components
communicate. Busses are grouped into three categories:
– Data lines: for transmitting data
– Address lines: indicate where information is sent to/from
– Control lines: regulate activity on the bus
In more detail, the architecture may look like the following:
Memory
Module
Timing
CPU
Bus
Control
Memory
Module
I/O
Module
Mass
Storage
I/O
Module
Keyboard
Interfaces frequently implemented in a microcomputer system.
Bus
Support
ROM
Static
RAM
Memory
Control
Data
Communication
Control
Mass
Storage
Control
Display
Control
Keyboard
Control
Hard Copy
Control
Display
Keyboard
Printer
Other
Device
To Mass Storage
To Processor
Dynamic
RAM
The 8086: the first 80x86 Machine
8086
Gen. p. Reg.
Data BUS
Address BUS
Mem. Space
Modes
Coprocessor
Multitasking
Virtual mem.
Virtual address.
Controll Reg.
Internal cache
Arhitecture
ALU Pipeline
BUS Pipeline
Burst R/W
Prefetch Buffer
8088
8/16bit 8/16bit
16
8
20
20
1MB
1MB
Real
8087
8087
80286
80386
8/16bit
16
24
16MB
8/16/32bit
32
32
4GB
80486
Pentium
8/16/32bit
8/16/32bit
32
64
32
32
4GB
4GB
Real/Protected
80287
80387
Internal
Internal (80-bit)
Memory Menagement & Protection /
Integrated Memory Menagement
1GB
64TB
64TB
adrress unit, segment descriptors, gate descriptors
Machine Status Word
Page Fault Liniar Address
Page Directory Base Add.
8KB
8KB data / 8KB instruction
CISC=Complex Instruction Set Computer
CISC/RISC
2 (two integer opp. or one
floating point at a time)
two BUS cycles at a time
32 bytes
32 bytes read at once from
cache
Branch prediction (i.e.
CALL)
Evolution of the Intel Processors
General Purpose Microprocessors
8080
8086/88
80286
80386
8051
80186
80386ex
80486
Pentium
Embedded Microprocessors/Microcontrollers
Pentium II
Pentium
80486
80386
80286
8086/88
Code and System
Level Compatability
The 8086: the first 80x86 Machine
8088 and 8086 pin assignments
GND 1
40 Vcc
A14
A15
A13
A16/S3
A12
A17/S4
A11
A18/S5
A10
A19/S6
___
A9
SS0 ___
A8
MN/MX
___
AD7
RD
AD6
8088
HOLD
AD5
HLDA
___
AD4
WR__
AD3
IO/M
__
AD2
DT/R
____
AD1
DEN
AD0
ALE
_____
NMI
INTA
_____
INTR
TEST
CLK
READY
GND 20
21 RESET
(HIGH)
___ ____
(RQ/GT0)
___ ____
(RQ/GT1)
______
(LOCK)
__
(S2)
__
(SI)
__
(S0)
(QS0)
(QS1)
GND 1
40 Vcc
AD14
AD15
AD13
A16/S3
AD12
A17/S4
AD11
A18/S5
AD10
A19/S6
____
AD9
BHE/S7
___
AD8
MN/MX
___
AD7
RD
AD6
8086
HOLD
AD5
HLDA
___
AD4
WR__
AD3
IO/M
__
AD2
DT/R
____
AD1
DEN
AD0
ALE
_____
NMI
INTA
_____
INTR
TEST
CLK
READY
GND 20
21 RESET
___ ____
(RQ/GT0)
___ ____
(RQ/GT1)
______
(LOCK)
__
(S2)
__
(SI)
__
(S0)
(QS0)
(QS1)
Typical Microprocessor Memory System
Control
CPU
Address
Data
Memory
8086 / 8088 Memory Interface
• Address Bus
– 20 address lines so a 220 byte address space
– Pins A0-A19 provide the address
– For 8086, A0-A15 appear multiplexed with D0-D15 to form AD0AD15
– For 8088, A0-A7 appear multiplexed with D0-D7 to form AD0-AD7
• Data Bus
– For 8086, 16 bit data bus D0-D15 (multiplexed as AD0-AD15)
– For 8088, 8 bit data bus D0-D7 (multiplexed as AD0-AD7)
– 8086 may use only D0-D7 or D8-D15 if appropriate
• Control Bus
– For memory access, the following pins are used:
– RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE’
General Architecture of the
8088/8086 Processors
Segment
Registers
Instruction
Pointer
General
Registers
Address
Generation and
Bus Control
Operands
Instruction
Queue
ALU
Flags
BUS
Real mode and Protected mode
operation
Addressable memory:
8086 20 address lines => 1MB (Mega Byte)
•
•
•Pentium 32 address lines => 4096MB
For compatibility, all the 80x86 family members start running in “Real Mode”,
emulating the 8086 features (i.e. 1MB RAM)
Beginning with 80286, the “Protected Mode” is also available, allowing direct
control of all address lines (all addressable memory), multitasking support,
virtual memory addressing, memory management and protection (against
violation from other task), control over internal data and instruction cache.
Addresses
• Memory locations are comprised of groups of bits.
– 8 bits: 1 byte
– 16 bits: 1 word
– 32 bits: 1 double word
– 64 bits: 1 quad word
• Each byte has an associated address. Addresses are
comprised of groups of bits.
• The set of all possible address bit combinations is called the
ADDRESS SPACE.
The Software Model of 80x86 Family
15 . . . 8,7 . . . 0
AH
BH
CH
DH
AL
BL
CL
DL
15 . . . 8,7 . . . 0
A
B
C
D
B
S
D
X
X
X
X
P
I
I
CS
DS
SS
ES
FS
GS
IP
SP
FLAGS
8 bit registers
16 bit registers
31 . . . . . . 16,15 . . . 8,7 . . . 0
Accumulator
Base
Count
Data
Base Pointer
Source Index
Destination Index
EAX
EBX
ECX
EDX
EBP
ESI
EDI
AH A
BH B
CH C
DH D
B
S
D
X
X
X
X
P
I
I
AL
BL
CL
DL
Code Segment
Data Segment
Stack Segment
Extra Segment
Extended registers, only on
80386 and higher CPUs
Instruction Pointer
Stack Pointer
Flags
IP
EIP
SP
ESP
EFLAGS FLAGS
32 bit registers,
80386 or higher only
Processor Registers
A prefix (66H) allows 15 . . . 8,7 . . . 0
Accumulator
Multiply, divide, accessing I/O...
AX
using 32 bit registers in
Base
BX
the real mode:
Count
Counter in loop operations
CX
db 66h
Data
Multiply, divide, pointer to I/O...
DX
;EAX instead AX
Base Pointer
BP
mov ax,1140h
SI
Source Index
Source index in string operations...
;less significant 16 bits
DI
Destination Index Destination index in string operation
db 058bh
Segment = a 64kbyte memory block
;most significant 16 bits
CS
Code Segment beginning at a multiple by 10H
DS
Data Segment address.
Shift
SS
Stack Segment An effective address is generated as
to left
combination between a segment
16 bit
ES
Extra
Segment
4 bits
register and another register as in
FS
the example.
GS
A000 + Add
Each segment register has a default usage
5F00 16 bit
(class of instructions where apply).
A5F00
Instruction Pointer Pointer in program flow
IP
Stack Pointer
Pointer in Stack
SP
Effective
Flags
Control and status flags
FLAGS
Address
16 bit registers
(20bits)
Flag register
15
-
14
NT
CF
PF
AF
ZF
SF
TF
IF
DF
OF
IOPL
NT
13 12
IOPL
11
OF
10
DF
Carry Flag
Parity Flag
Auxiliary carry Flag
Zero Flag
Sign Flag
Trace Flag
Interrupt enable Flag
Direction Flag
Overflow Flag
I/O Priority Level
Nested Task
9
IF
8
TF
7
SF
6
ZF
5
-
4
AF
3
-
2
PF
1
-
0
CF
Contains Carry out of MSB of result
Indicates if result has even parity
Contains Carry out of bit 3 in AL
Indicates if result equals zero
Indicates if result is negative
Provides a single step capability for debugging
Enables/disables interrupts
Controls pointer updating during string operations
Indicates that an overflow occurred in result
Priority level of current task (two bits)
Indicates if current task is nested
Data Organization
Bits, Bytes, Words, Double-words
Name
Size
Binary
Possible Values
Hexadecimal
Decimal
Bit
Nibble
Byte
Word
Double Word
BInary digiT
4 bits
8 bits
16 bits = 2 bytes
32 bits = 4 bytes
0,1
0...1111
0…1111,1111
0…(16 ‘1’s)
0…(32 ‘1’s)
0,1
0...F
0…FF
0…FFFF
0…FFFFFFFF
0,1
0…15
0…255
0…65,535
0...4,294,967,295
Byte swapping: if a word has to be stored into an 8 bit wide memory at address adr, its
low byte is stored at adr and its high byte at adr+1. If a word is read from an 8 bit
memory at address adr, the low byte is loaded from adr and the high byte from adr+1.
Rule: low significance <=> low address
Instruction types
Data transfer instructions
8086 instruction set
Additional 80386 instructions
IN
LAHF
LDS
LEA
LES
MOV
OUT
POP
POPF
PUSH
PUSHF
SAHF
XCHG
XLAT
LFS
Load pointer using FS
LGS
Load pointer using GS
LSS
Load pointer using SS
MOVSX Move with sign extended
MOVZX Move with zero extended
POPAD Pop all double (32 bit) registers
POPD
Pop double register
POPFD Pop double flag register
PUSHAD Push all double registers
PUSHD Push double register
PUSHFD Push double flag register
Input byte or word from port
Load AH from flags
Load pointer using data segment
Load effective address
Load pointer using extra segment
Move to/from register/memory
Output byte or word to port
Pop word off stack
Pop flags off stack
Push word onto stack
Push flags onto stack
Store AH into flags
Exchange byte or word
Translate byte
Additional 80486 instruction
Additional 80286 instructions
BSWAP Byte swap
INS
OUTS
POPA
PUSHA
Additional Pentium instruction
Input string from port
Output string to port
Pop all registers
Push all registers
MOV
Move to/from control register
Instruction types
Arithmetic instructions
8086 instruction set
AAA
AAD
AAM
AAS
ADC
ADD
CBW
CMP
CWD
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
Additional 80386 instructions
ASCII adjust for addition
CDQ
Convert double-word to
ASCII adjust for division
quad-word
ASCII adjust for multiply
CWDE Convert word to double-word
ASCII adjust for subtraction
Add byte or word plus carry
Additional 80486 instructions
Add byte or word
CMPXCHG
Compare and exchange
Convert byte or word
XADD
Exchange and add
Compare byte or word
Convert word to double-word
Decimal adjust for addition
Additional Pentium instruction
Decimal adjust for subtraction
CMPXCHG8B Compare and
Decrement byte or word by one
exchange 8 bytes
Divide byte or word
Integer divide byte or word
Integer multiply byte or word
Increment byte or word by one
Multiply byte or word (unsigned)
Negate byte or word
Subtract byte or word and carry (borrow)
Subtract byte or word
Instruction types
Bit manipulation instructions
8086 instruction set
Additional 80386 instructions
AND
NOT
OR
RCL
RCR
ROL
ROR
SAL
SAR
SHL
SHR
TEST
XOR
BSF
BSR
BT
BTC
BTR
BTS
SETcc
SHLD
SHRD
Logical AND of byte or word
Logical NOT of byte or word
Logical OR of byte or word
Rotate left trough carry byte or word
Rotate right trough carry byte or word
Rotate left byte or word
Rotate right byte or word
Arithmetic shift left byte or word
Arithmetic shift right byte or word
Logical shift left byte or word
Logical shift right byte or word
Test byte or word
Logical exclusive-OR of byte or word
Bit scan forward
Bit scan reverse
Bit test
Bit test and complement
Bit test and reset
Bit test and set
Set byte on condition
Shift left double precision
Shift right double precision
Instruction types
String instructions
8086 instruction set
CMPS
LODS
MOVS
MOVSB(MOVSW)
REP
REPE (REPZ)
REPNE (REPNZ)
SCAS
STOS
Compare byte or word string
Load byte or word string
Move byte or word string
Move byte string (word string)
Repeat
Repeat while equal (zero)
Repeat while not equal (not zero)
Scan byte or word string
Store byte or word string