8288 bus controller

8288 bus controller

SAP-III

SAP-III

Assembly Language

Basic Microcomputer Design

   clock synchronizes CPU operations control unit (CU) coordinates sequence of execution steps ALU performs arithmetic and bitwise processing data bus registers

Central Processor Unit (CPU)

ALU CU clock address bus control bus Memory Storage Unit I/O Device #1 I/O Device #2

Introduction

 Assembly language is used primarily for direct hardware manipulation, access to specialized processor instructions, or to address critical performance issues. Typical uses are device drivers, low-level embedded systems, and real-time systems.

Reasons for not using assembly

 Development time: it takes much longer to develop in assembly. Harder to debug, no type checking, side effects…  Maintainability: unstructured, dirty tricks  Portability: platform-dependent

Reasons for using assembly

 Educational reasons: to understand how CPUs and compilers work. Better understanding to efficiency issues of various constructs.

 Developing compilers, debuggers and other development tools.

    Hardware drivers and system code Embedded systems Developing libraries. Accessing instructions that are not available through high-level languages.

 Optimizing for speed or space

To sum up

 It is all about lack of smart compilers  Faster code, compiler is not good enough  Smaller code , compiler is not good enough, e.g. mobile devices, embedded devices, also Smaller code → better cache performance → faster code  Unusual architecture , there isn’t even a compiler or compiler quality is bad, eg GPU, DSP chips, even MMX.

Overview

 Virtual Machine Concept  Data Representation  Boolean Operations

Translating Languages

English: Display the sum of A times B plus C.

C++: cout << (A * B + C); Assembly Language: mov eax,A mul B add eax,C call WriteInt Intel Machine Language: A1 00000000 F7 25 00000004 03 05 00000008 E8 00500000

Virtual machines

Abstractions for computers High-Level Language Assembly Language Operating System Instruction Set Architecture Microarchitecture Digital Logic Level 5 Level 4 Level 3 Level 2 Level 1 Level 0

High-Level Language

 Level 5  Application-oriented languages  Programs compile into assembly language (Level 4) cout << (A * B + C);

Assembly Language

 Level 4  Instruction mnemonics that have a one-to-one correspondence to machine language  Calls functions written at the operating system level (Level 3)  Programs are translated into machine language (Level 2) mov eax, A mul B add eax, C call WriteInt

Operating System

 Level 3  Provides services  Programs translated and run at the instruction set architecture level (Level 2)

Instruction Set Architecture

 Level 2  Also known as conventional machine language  Executed by Level 1 program (microarchitecture, Level 1) A1 00000000 F7 25 00000004 03 05 00000008 E8 00500000

Microarchitecture

 Level 1  Interprets conventional machine instructions (Level 2)  Executed by digital hardware (Level 0)

Digital Logic

 Level 0  CPU, constructed from digital logic gates  System bus  Memory

Segment Registers

 Any program has two essential parts  Code  Data  During execution of program  Parameters are passed/returned from one subroutine to another  Processing of interrupts requires storing of program variables  A stack (Data Structure) is essential for passing parameters and processing of interrupts

Segment Registers

 Program Code placed in memory in an area defined as Code Segment (CS)  Program Data placed in memory in an area defined as Data Segment (DS)  Program stack is implemented in memory in an area defined as Stack Segment (SS)  An extra data area is reserved in memory to facilitate data manipulation operations  Extra data area is defined as Extra Segment (ES)

Segment Registers

 Code Segment 16-bit Register  Holds the start address of the section of the memory that holds code  Data Segment 16-bit Register  Holds the address of the section of the memory that holds data  Stack Segment 16-bit Register  Holds the address of section of memory that holds stack

Segment Registers

 Extra Segment 16-bit Register  Holds the address of additional data segment used in string operations to hold destination data

Real-Mode Programming

 Allows access to 1 MB of memory  DOS OS requires microprocessor to operate in the real mode  All Intel processors begin operation in the real mode by default when powered up or when reset

Accessing Memory

 20 bit address is generated by combining a segment address and an offset address  Segment Register = C000 H  Offset Register = 1C78 H  20 bit address = C000 0 + 1C78 = C1C78 H  Also written as C000:1C78  Each segment is of size 64KB

Accessing Memory

 A rightmost 0 is appended to segment register contents  Segment begins on a 16-byte boundary  16-byte boundary known as Paragraph  Some addressing modes combine more than three registers to generate a 20-bit memory address  Modulo 16 used to generate address  Seg. Reg = 4000 H  offset reg = F000 H & 3000 H

Accessing Memory

 Offset address = F000 + 3000 = 12000 H  Modulo 16 = 2000 H  20-bit address = 40000 + 2000 = 42000 H

Default Segment & Offset Registers

 CS and IP  SS and SP or BP  DS and BX, DI, SI, an 8-bit or 16-bit number  ES and DI  Segments can be located anywhere in the memory  Segments can overlap  Allows relocatable programs

Sample Program

mov ax, 5 add ax, 10H add ax, 20 mov sum, ax int 20h

execution

AX=0000 BX=0000 CX=0000 DX=0000 SP=DF12 BP=0000 SI=0000 DI=0000 DS=1FDD ES=1FDD SS=1FDD CS=1FDD IP=0100 NV UP EI PL NZ NA PO NC MOV AX,0005 AX=0005 BX=0000 CX=0000 DX=0000 SP=DF12 BP=0000 SI=0000 DI=0000 DS=1FDD ES=1FDD SS=1FDD CS=1FDD IP=0103 NV UP EI PL NZ NA PO NC ADD AX,0010 AX=0015 BX=0000 CX=0000 DX=0000 SP=DF12 BP=0000 SI=0000 DI=0000 DS=1FDD ES=1FDD SS=1FDD CS=1FDD IP=0106 NV UP EI PL NZ NA PO NC ADD AX,0020 AX=0035 BX=0000 CX=0000 DX=0000 SP=DF12 BP=0000 SI=0000 DI=0000 DS=1FDD ES=1FDD SS=1FDD CS=1FDD IP=0109 NV UP EI PL NZ NA PE NC MOV [0120],AX

Addressing Modes

 Different ways to access operands  Different data structures use different ways to access data values  Stack  Queue  Tree  Array

Instruction Execution Cycle

     Fetch Decode Fetch operands Execute Store output memory op1 op2 PC read I-1 program I-2 I-3 I-4 fetch registers registers I-1 instruction register flags (output) ALU execute

Addressing Modes

The following are the different addressing modes of 8086:  Register operand addressing.  Immediate operand addressing.  Memory operand addressing. The different memory addressing modes are:    Direct Addressing Register Indirect Addressing Based Addressing    Indexed Addressing Based Indexed Addressing and Based Indexed with displacement.

Addressing Modes

 Operands can be of type  Register  Immediate  Memory  Register Addressing  Contents of the register are used  MOV AX, BX  Immediate Addressing  A constant data value is specified  MOV CH, 3AH

Addressing Modes

 Six Memory Addressing Modes are supported  Direct Addressing  Memory address is directly specified  mov [1234H],ax DS x 10H + DISP  mov value, ax  mov ax, buffer  add bl, value  cmp cx, count

Addressing Modes

 Register Indirect Addressing  The effective address of memory is the contents of a register  mov ax, [si]  add bl, [di]  cmp cx, [bx]

Addressing Modes

 Based or Register Relative Addressing  The effective memory address is the sum of a base register and a displacement  List[bx], [bp+1]  mov cl, [bx+4]  mov ax, list[bx] DS x 10H + BX + 4  add bl, [bx+7]  cmp cx, [bp-3]

Addressing Modes

 Indexed Addressing  The effective memory address is the sum of an index register and a displacement  mov [bx+2], bp  List[si], [list + di], [di+2] DS x 10H + BX + 2  mov ax, list[si]  add bl, [number+di]  cmp cx, [di+2]

Addressing Modes

 Base Indexed or Base-Plus-Index Addressing  The effective memory address is the sum of a base register and an index register  [bx+si], [bx][di], [bp+di]  mov [bx+si], bp DS x 10H + BX + SI will use DS as default seg  mov ax, [bx+si]  add bl, [bx][si]  cmp cx, [bp+di]

Addressing Modes

 Base Indexed with Displacement or Base Relative-Plus-Index Addressing       The effective memory address is the sum of base register, index register and a displacement [bx+si+2], list[bx+di] mov array[bx + si], dx DS x 10H + ARRAY + BX + SI mov ax, array[bx+si] add bl, [bx+di+2] cmp cx, 2[bp+di]

Addressing Modes

 Summary The following are the different addressing modes of 8086:  Register operand addressing.   The different memory addressing modes are:  Direct Addressing  Immediate operand addressing. Memory operand addressing. Register Indirect Addressing     Based Addressing Indexed Addressing Based Indexed Addressing and Based Indexed with displacement.

Instruction Set

 Data Movement Instructions  mov, lea, les, lds, push, pop, pushf, popf  Conversions  cbw, cwd, xlat  Arithmetic instructions  add, inc, sub, dec, cmp, neg, mul, imul, div, idiv  Logical instructions  and, or, xor, not, shl, shr, rcl, rcr

Instruction Set

 I/O instructions  in, out  String instructions  movs, stos, lods, scas, cmps  Program flow control instructions  jmp, call, ret, conditional jumps  Misc instructions  clc, stc, cmc, cld, std, cli, sti

Mov Instruction

 Limitations  CS and IP can not be destination registers  Immediate data can not be moved to segment registers  Contents of segment registers can not be moved to segment registers  Source and destination operands have to be of same size

Mov Instruction

 Limitations  Immediate data must not exceed 0FFh or 0FFFFh for 8 and 16 bit data  Memory to memory transfers are not allowed  No flags are affected  Instruction size  Number of clocks

Writing and Assembling Programs

Source Program Sample.asm

Assembler masm.exe

Object Program sample.obj

Optional Listing file sample.lst

Cross reference file sample.crf

Linker link.exe

Executable Program sample.exe

Map file sample.map

Assembly Program Structure

Assembly Program Structure

.model small .stack 100h entr equ 0dh bufsize equ 10h .code

.startup

mov ax,@data mov ds,ax mov si,offset buffer

Assembly Program Structure

a1: mov cx,bufsize mov ah,1 int 21h cmp al,entr je a2 mov [si],al inc si loop a1

Assembly Program Structure

a2: sub charstyped,cl mov ax,4c00h int 21h .exit

.data

charstyped db bufsize buffer db bufsize dup(0) end

Comparing three numbers

.model small .stack 100h .code

main proc mov ax,@data mov ds,ax mov bl,10 mov cx,3 mov si,offset var1

Comparing three numbers

call get numbers call compare numbers call show numbers mov ax,4c00h int 21h main endp

Comparing three numbers

get numbers proc agn1: mov ah,1 int 21h sub al,30h mul bl mov dl,al mov ah,1 int 21h sub al,30h add dl,al mov [si],dl inc si loop agn1 get numbers endp

Comparing three numbers

compare numbers proc mov cx,2 agn2: mov al,var2 cmp var1,al jb l1 xchg var1,al mov var2,al l1: cmp al,var3 jb l2 xchg var3,al l2: mov var2,al loop agn2 compare numbers endp

Comparing three numbers

show numbers proc show: mov dl,var1 mov ah,2 int 21h mov dl,var2 mov ah,2 int 21h mov dl,var3 mov ah,2 int 21h show numbers endp

Comparing three numbers

.data

var1 db 0 var2 db 0 var3 db 0 end main Lecture 20