Transcript 回路設計用モデル開発基盤の構築とこれを用いたマル

The HiSIM Family of Compact-Models
for Integrated Devices
H. J. Mattausch, N. Sadachika, M. Miyake,
H. Kikuchihara, U. Feldmann,
and M. Miura-Mattausch
Hiroshima University
HiSIM Research Center
Research Institute for Nanodevice and Bio Systems
Graduate School for Advanced Sciences of Matter
MOS-AK, San Francisco, Dec. 13, 2008
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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Basic Compact Model Approaches for the MOSFET
Threshold-Voltage-Based Models (e. g. BSIM3, BSIM4)
● currents expressed as functions of applied voltages
● different equations for:
- sub-threshold region
- linear region
- saturation region
Ids  
W
1


Cox Vgs  Vth Vds  Vds 2 
L
2


New Generation of Surface-Potential-Based Models
1
np 0
2 SqNsub
2
QS = COX (V'G  S ( y )) =
[exp   S ( y )   S ( y)  1 +
exp  s ( y)   1]

pp0
● implicit equation for surface potential
● currents determined from drift and diffusion term
of current density equation
● developed calculation methods for the surface potential:
- iterative solution with the exact surface-potential equation
⇒HiSIM
st
nd
- approximate explicit solution by 1 & 2 order perturbation theory,
after prior conditioning of the surface-potential equation
⇒PSP
New Generation of Inversion-Charge-Based Models
● additional approximation to solve for inversion charge
⇒ EKV, BSIM5, ACM
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Basic Equations for Potential-Based Device Model
s
(solved by SPICE)
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Consistency Property of Surface-Potential Model
Q()
n =  E: velocity
=
: mobility
The surface potential consistently determines charges,
capacitances and currents under all operating conditions.
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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Development History of Bulk-MOSFET Model HiSIM
1990 JJAP
1991 SISPAD
Sub-1m MOSFETs
“
1994 ICCAD
“
1995 Siemens Flash-EEPROM
1998 STARC
100-nm MOSFET
short-channel effect model
1st surface-potential-based model
parameter extraction strategy
simulation time & stability verification
concurrent device/circuit development
collaboration start
Release Activity
2001 Oct. release to vendors
2002 Jan. release to public
Oct.
“
HiSIM1.0.0 source code and manual
“
“
HiSIM1.1.1
“
2003 Oct. Test release to STARC clients
2005 May release to CMC members
July
“
Oct.
“
2006 Jan. release to EDA vendors
2007 March
“
2008 Sept. release to CMC members
HiSIM2.0.0 source code and manual
HiSIM2.0.0
“
+ Verilog-A code
HiSIM2.2.0
“
HiSIM2.3.0
HiSIM2.4.0
HiSIM2.4.3 eval. for standardization
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Modeled Phenomena in HiSIM2.4.3
[Phenomena]
[Subjects]
Short Channel:
Reverse-short Channel:
Poly-Depletion:
impurity pile-up
pocket implant
[Phenomena]
Non-Quasi-Static: transient time-domain
AC frequency-domain
Noise:
1/f
thermal
induced gate
cross-correlation
Quantum-Mechanical:
Channel-Length Modulation:
Narrow-Channel:
Temperature Dependency: thermal voltage
bandgap
ni
phonon scattering
maximum velocity
Mobility Models:
Leakage Currents: substrate current
gate current
GIDL current
Source/Drain Resistances:
Junction Diode:
currents
capacitances
universal
high Field
Shallow-Trench Isolation: threshold voltage
mobility
leakage current
Capacitances:
[Subjects]
intrinsic
overlap
lateral-field induced
fringing
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Binning Option
DFM Option
8
HiSIM’s Surface Potentials at Source and Drain
Basic Surface-Potential Equation
n
 ( ( y ) ( y ))
 (V ( y ) ( y ))
Cox (VG'  S )  2 qN {e ( ( y )V )   (S ( y )  Vbs )  1  p [e
e
]}
2
 ox
q
n

Cox 
 f ( Leff )   f (0)  Vds
VG'  Vgs  VFB
n p0  i
kT
tox
p p0
Si
sub
S
bs
p0
S
f
bs
f
1
2
p0
Iterative HiSIM Solution
in Comparison to
2D-Devices Simulation
The absolute values of the HiSIM surface potential
compare well with 2D simulation.
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Surface-Potential Dependence on Applied Voltages
SLsaturates
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Bias Dependence & Derivatives of Surface Potential
HiSIM accurately reproduces even the bias dependence
of the surface-potential derivatives.
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Gummel-Symmetry Properties (HiSIM243)
model parameters: default
Ids vs. Vx
Ids / Vx vs. Vx
Ids2 / Vx2 vs. Vx
Ids3 / Vx3 vs. Vx
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Short-Channel-Effect Model
(approximating a quadratic potential distribution)
M. Miura-Mattausch et al., IEEE TED, 48, p. 2449, 2001.
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Pocket-Implantation Model
Including tail for high pocketdoping concentrations.
H. Ueno et al., IEEE TED, 49, p. 1783, 2002.
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Model Extraction for Advanced 45nm Technology
Wg/Lg=2m/200nm
Wg/Lg=2m/40nm
Measurement
HiSIM
HiSIM can model advanced 45nm technology very
accurately without the necessity of binning.
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Current Derivatives for Advanced 45nm Technology
Measurement
HiSIM
Wg/Lg=
2m/40nm
The current derivatives of a 45nm technology can
likewise be well reproduced with HiSIM.
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HiSIM’s Model Evaluation Time
Arbitrary Units
total CPU
extrinsic device
characteristics
intrinsic device
characteristics
SLiteration
S0 iteration
Vgs
Data: HiSIM2.4.0
Iteration for surface-potential determination requires only
a small fraction of the total model evaluation time.
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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Determination of Involved Potentials
BOX
FOX
2D-Device
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I-V Curve Reproduction and Short-Channel Effect
This Device does not show a floating body effect!
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1/f-Noise Modeling
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Comparison with 1/f-Noise in Bulk MOSFETs
1/f-Noise in the SOI-MOSFET is substantially increased!
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Modeling of the Floating-Body Effect
The floating-body effect is modeled on the basis of
excess hole charge due to impact ionization.
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Modeling of the Dynamic-Depletion Effect
The dynamic-depletion effect is accurately captured due
to the consistently potential-based model concept.
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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Specific Features of the Double-Gate (DG) MOSFET
Tsi
gate
gate
gate
Tsi=40nm
gate
Tsi=20nm
Vgs=1V
Vds=0V
gate
Tsi=10nm
gate
carrier concentration
Body potential is floating.
Tsi
The floating body potential makes modeling difficult.
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HiSIM-DG Accuracy for the Center Surface Potential
The potentials at center and surface are determined with
HiSIM-DG as accurately as in 2D-device simulation.
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Short-Channel Effect in DG MOSFETs
The drastic reduction of the short-channel effect is a big
advantage of the double-gate MOSFET.
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Potential Dependence: Silicon Thickness and Nsub
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TSi
s0 (V)
s0 (V)
Nsub
29
Ids-Vgs Characteristics Reproduction
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C-V Characteristics Reproduction
Reduction of Tsi has only a small influence
on the capacitance.
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Impurity-Concentration Dependence of Vth
TSI=10nm, Tox=1nm, Lg=1um, Vds=50mV
Influence of Qb cannot be ignored.
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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Structure of the Accumulation-Mode MOS-Varactor
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Carrier-Movement Delay in Accumulation Mode
t is
inverse proportional
to the electric field.
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Frequency Dependence of MOS-Varactor Capacity
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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High-Voltage MOSFET Structures
(Asymmetric)
(Symmetric)
Public/Release Activities for HiSIM_HV Model
2006 Oct.
2007 Dec.
2008 June
2008 Dec.
candidate for CMC standardization
selected for CMC standardization
HiSIM_HV1.0.2 release (evaluated as first standard version)
HiSIM_HV1.0.2 named CMC standard model
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HiSIM2 Properties Facilitating Extension to HV-MOS
Complete Surface-Potential-Based Model
HiSIM for Bulk-MOSFET
S0 : at source edge
SL : at the end of the gradual-channel approx.
S(DL) : at drain edge (calculated from SL)
Beyond Gradual-Channel Approximation
Channel-Length
Modulation
Overlap Capacitance
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Consistent Potential Drop Modeling in Drift Region
Ldrift
Ndrift
Potential drop
in the drift region
All important potential values are known.
No sub-circuit for the potential drop is necessary.
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S(DL) : potential determining
LDMOS characteristics
S(DL) [V]
S(DL) [V]
S(DL)
S(DL) [V]
S(DL) [V]
Consistency Evaluation of Key Potential Values
HV
Vgs [V]
HV
Vds [V]
HiSIM reproduces S(DL) calculated by 2D-device simulator.
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Accuracy Comparison of Id-Vgs
: 2D-Device Simulation Results
: HiSIM-HV Results
Vds=10V
gm [S]
Id [A]
Vds=20V
Vds=5V
Vds=0.1V
Good agreement between HiSIM-HV results
and 2D-device simulation results is achieved.
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Accuracy Comparison of Id-Vds
: 2D-Device Simulation Results
: HiSIM-HV Results
Vgs=7.5V
gd [S]
Id [A]
Vgs=10V
Vgs=5V
Vgs=2.5V
Quasi-saturation behavior of LDMOS is reproduced.
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Reproduction of Key Capacitance Features
Ldrift = 1.5m
Vds = 10V
HV
Qinv
 Cdrift
Vgs
Qinv
Vgs
Cdrift
Vgs [V]
Vgs [V]
Charge in the drift region is modeled explicitly.
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Reproduction of Intrinsic Capacitances
Symmetrical
HVMOS
2.0
Capacitance [fF]
Capacitance [fF]
Asymmetrical
LDMOS
Cgg
1.8
1.2
Cgd
Cgb
0.8
0.4
Cgs
Vds=0V
-4
-2
0
Vgs [V]
2
4
Vgs [V]
HiSIM-HV is capable to reproduce all intrinsic
capacitances with good accuracy.
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Concept of the HiSIM-IGBT Compact Model
Schematic structure of a modern trench-IGBT
Jn
n- (base)
Simplified circuit diagram of the HiSIM-IGBT model
Consistent potential extension in HiSIM-IGBT is
achieved by calculation based on Kirchhoff’s laws.
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Fitting Results for the I-V Characteristics of the IGBT
HiSIM-IGBT achieves accurate reproduction of the
IGBT’s I-V characteristic and also scales with the
base doping.
M. Miyake et al., “A Consistently Potential Distribution Oriented Compact IGBT Model”,
IEEE PESC, pp. 998-1003, June 2008
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Outline of Presentation
1. Introduction
2. Modeling Based on a Consistent Potential
Distribution
3. Bulk MOSFET Model HiSIM2
4. Silicon-On-Insulator (SOI) MOSFET
5. Double-Gate MOSFET
6. MOS Varactor
7. High-Voltage Devices


High-Voltage MOSFET
Insulated Gate Bipolar Transistor (IGBT)
8. Thin-Film Transistor (TFT)
9. Conclusion
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Concept of the Thin-Film-Transistor (TFT) Model
Typical structure
of the poly-Si TFT
Effect of Traps on the
I-V characteristic
Gate Electorode
1.E-05
Gate Insulator
Channel
Source
Id(A)
1.E-07
Drain
large
trap density
1.E-09
poli-Si layer
1.E-11
Insulating Substrate
Back side potential
is floating.
 2  
q
 Si
p  n  N
Traps deteriorate
I-V characteristics.

D


 N A  N TD
 N TA
-2
1.E-13
-1
0
1
2
3
4
Vg(V)

(1)

 E fn  EC 
  E fn  EC 




N t 0  N TD
 N TA
 N tK  exp

exp


E1 
E1 


 

TFT modeling is
based on including
the trap charge in the
(6)
Poisson equation.
 Vgs  VFB  S 0  EfnMAX  EfnMIN

S. Miyano et al., “A surface potential based
E fn  EC  tan  
 Efn0 (5)
 TOX  E


Poly-TFT model for circuit simulation”, IEEE
s_K


1
SISPAD, Sept. 2008
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Reproduction of Fabricated TFT-Device Data
measurements
simulations
6.0
4.0
L=2μm
Ids(a.u.)
Ids(a.u.)
4.0
measurements
simulations
5.0
2.0
L=0.5μm
3.0
2.0
1.0
0.0
0.0
0
Vds(V)
1
L=2μm
2
3
1
L=0.5μm
1.E+00
1.E-04
measurements
simulations
1.E-06
1.E-08
-3
-1
Vgs(V)
2
3
1.E+00
1.E-04
measurements
simulations
1.E-06
1.E-08
1.E-10
1.E-10
-5
Vds(V)
1.E-02
Ids(a.u.)
1.E-02
Ids(a.u.)
0
1
3
5
-5
-3
-1
Vgs(V)
1
3
5
Accurate reproduction of I-V characteristic and scaling with
gate length is achieved.
S. Miyano et al., “A surface potential based Poly-TFT model for circuit simulation”, IEEE SISPAD, Sept. 2008
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Conclusion
● HiSIM2 is a compact surface-potential-based
MOSFET model with a minimum number of
approximations, due to its iterative
surface-potential determination.
● HiSIM2 allows to preserve a consistent
potential-based modeling in its extension to
other integrated-device structures containing a
MOSFET core.
A compact-model family covering all integrated
devices containing a MOSFET core and sharing the
same modeling concepts could be developed.
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