Transcript Document

PSP Family of Compact Models
Overview and Recent Developments
MOS-AK
December 13th, 2008
G. Gildenblat, W. Wu, X. Li, Z. Zhu, W. Yao, Q.
Zhou, G. Dessai, and A. Dey
G.D.J. Smit, A.J. Scholten, and D.B.M.
Klaassen
1
Outline
 PSP project overview
 Introduction to bulk PSP
 Recent developments in bulk PSP
 PSP-SOI
 PSP-MGFET
 Conclusions
MOSFET characteristics shown in this presentation are from Philips/NXP,
Freescale and IBM (presented with permission)
Further information about PSP can be found on PSP website:
http://pspmodel.asu.edu
2
PSP Family of Models
 PSP: industry (CMC) standard for bulk MOSFETs
 PSP-based varactor model: industry (CMC) standard
 PSP-SOI-PD: submitted to CMC for evaluation (sponsored by IBM)
 PSP-SOI-DD: submitted to CMC for evaluation (sponsored by Freescale)
 PSP-MGFET
 PSP-LT: PSP model for the extended temperature range for space
applications (NASA/JPL)
 PSP-R2H: PSP-based model for the physics-based real-time evaluation of
radiation, EMP and reliability effects at the circuit level
3
Outline
 PSP project overview
► Introduction
to bulk PSP
 Recent developments in bulk PSP
 PSP-SOI
 PSP-MGFET
 Conclusions
4
s-Based vs. Vth-Based Models
10-4
-5
10
IDS = Idrift + Idiff
IDS (A)
10-6
10-7
10-8
10-9
-10
10
10-11
0
10-7
PSP
1
-10
10
2
interpolation
10-8
10-9
Idrift
asymptotic
10-5
Idiff
10-6
IDS (A)
10-4
10-11
0
VGS (V)
empirical
Vth-based
1
2
VGS (V)
VSB = 0 V; VDS = 1 V
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Advanced Features of PSP
 Non-iterative formulation
 Completely surface-potential-based including the S/D overlap
regions
 Complete symmetry of device characteristics including all higherorder effects
 Advanced mobility model including Coulomb scattering
 Perfect reproduction of gm/Id ratio
 Capability to model harmonic distortion including intermodulation
effects
 Physical gate current model including accurate bias-dependent
partitioning scheme implemented via symmetric linearization
method
6
Advanced Features (cont’d)
 The most complete ever noise model correctly including velocity
saturation effects and all noise sources
 Extensively verified unified large-signal/small signal NQS Model
 Most complete and physical junction diode model (JUNCAP2)
 Inclusion of non-uniform doping
 Accurate CLM modeling in halo-doped devices
 New mathematical structure of the model based on solution of
several long-standing problems of compact modeling (e.g.
symmetric linearization, spline-collocation NQS model, etc.)
7
Normalized Mobility
Non-Universality of the Effective Mobility
Produced by the Coulomb Scattering
Produced by
Coulomb Scattering Term
Effective Field (MV/cm)
8
Drift Velocity
 PSP uses drift velocity model that is conducive to the highly
accurate description of saturation region including high order drain
conductances
Electrons:
Holes:
Vd 
Ey

1  E y Ec

2
Ey
Vd 
1

E y Ec

2
1 E y Ec
 This form also assures compliance with Gummel symmetry
test and non-singular model behavior at Vds= 0.
9
Gm / ID (1/V)
Gm/ID Plots for Two Corners of
the 90 nm Process
10µm/1µm
ID (A)
10µm/0.04µm
ID (A)
VDS = 0.025V, VBS = 0 to -1.2V, and VGS = 0 to 1.2V
10
Output Conductances
W/L=10/0.04µm
gDS (A/V)
gDS (A/V)
W/L=10/1µm
VDS (V)
VDS (V)
VGS = 0V to 1V in steps of 0.2 V, VSB = 0V
T = 250C
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gmi (A/V)
gDSi (A/V)
Higher Order Transconductances and
Conductances
VDS = 0.025V
VGS (V)
VSB=0V, T=250C, W/L=10/0.04µm (nmos),
i=1(lower curve), 2(middle curve), 3(upper
curve)
VGS = 1V
VDS (V)
VSB=0V, T=250C, W/L=10/0.04µm (nmos),
i=1(lower curve), 2(middle curve), 3(upper
curve)
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Traditional Asymmetric Linearization
 Theoretical foundation of PSP is symmetric linearization method: it
is used to simplify surface-potential-based approach and to make it
practical.
 To simplify formulation compact MOSFET models almost always
use bulk and inversion charge linearization. The traditional form is
 s   ss   ( s  ss )

1
2  ss


1
1 

a1  a2 · ss 

 In Vth-based models:  ss  2b  Vsb
 Disadvantage: symmetry between source and drain is lost, accuracy
is poor
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Symmetric Linearization
 Define surface potential midpoint (subscript “m”)
m
1
 ( ss  sd )
2
 For VDS > 0, this is not a geometric midpoint:
L   sd  ss
ym   1 
2
4H

,


H  t  qim m  Hsat
 Set inversion charge (per unit channel area)
 dqi 
qi  qim  
 s  m 

 d s  s  m
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Example of What Symmetric Linearization
can Accomplish
 Original CSM (C. McAndrew
and J. Victory, 2003)
 PSP
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Normalized Transcapacitances
Verification of Symmetric Linearization
0.9
Linearized CSM
Original CSM
Cgg
0.6
Csg
0.3
Cdg
Cbg
0.0
-1
0
1
2
3
4
Vgs (V)
Vds = 2V, Vbs= 0 V, Vfb=-1V
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CV Characteristics
Capacitance (F)
1.00E-015
0.00E+000
CBD
CDB
-1.00E-015
CBG
CGB
CBS
-2.00E-015
CSB
CDS
CSD
-3.00E-015
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
(V)
VdsVd(V)
W/L=10/0.08µm, Vbs=-0.1V, Vgs=1.2V
W/L = 800µm/90nm, Vds=0, Vsb=0
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Gate Tunneling Current Components
Ig
Igsov
Igc
S
Igcs
Igcd
D
 The same form of model and
identical parameters are used in
Igc, Igsov and Igdov
 No scaling parameters are
required to fit the data
Ig, (mA)
Igdov
Vgs, (V)
VDS=0V to 1V in steps of 0.5 V
VSB=0V, W/L=10µm/1µm (nmos)
T=250C
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PSP Noise Model
 Includes thermal channel noise, 1/f
noise, channel-induced gate noise and
shot-noise in the gate-current
 Example
 Thermal channel noise automatically
becomes shot noise below threshold,
so it is not necessary to model this
phenomena separately
 Rigorously includes fluctuations in the
velocity saturation term.
 Takes advantage of symmetric
linearization to simplify expressions
for the spectral densities
 Experimentally verified
Drain (Sid) and gate (Sig) current
noise spectral densities
19
NQS Model Verification: Re[Y11]
PSP, SWNQS=5
PSP, SWNQS=9
MM11, 5 segments
VDS=1.5 V, VGS= 0.5 to 1.5 in 0.5V steps
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Outline
 PSP project overview
 Introduction to bulk PSP
► Recent
developments in bulk PSP
 PSP-SOI
 PSP-MGFET
 Conclusions
21
Recent Developments in PSP
 Optional asymmetric junctions
 Optional separate doping profiles for I(V) and C(V)
characteristics
 Optional suppression of back-bias effect for high back
biases
 GA-based automatic procedure for parameter extraction
(local and global)
 PSP-LT: PSP model for the extended temperature range
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Automatic GALM Parameter Extraction
 GA - Genetic Algorithm, LM - LevenbergMarquardt Algorithm
 Objectives
• Unbiased evaluation of new parameters (are they really needed)
• Ease of parameter extraction
 Example :
2

  mt 
ALP1 qim 
  T2  ALP2  qbm  
  T1   ALP 

2
q





m t 
 im
 qim  mt  

Table I. Relative RMS error (%) on Id (Vd) with ALP2 on and off.
Setting
Fit with ALP2=0
Fit with ALP20
W=L=10m
W/L=10/0.24m
W/L=10/0.06m
1.6
0.63
2.9
1.7
2.5
1.8
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Id (A.U.)
gm (A.U.)
Automatic Parameter Extraction Results
for PSP 102.1
W=L=10m
0
0.5
1
W=L=10m
1.5
0
0.5
Id (A.U.)
W/L=120/65nm
0
1
1.5
Vg (V)
gm (A.U.)
Vg (V)
0.5
1
Vg (V)
1.5
W/ L=120/65nm
0
0.5
1
1.5
Vg (V)
24
L = 45 nm
VDS = 50 mV
VSB = 0 … 1.3 V
Ids (arb. units)
Non-uniform Doping
PSP 102
PSP 103 with NUD
measured
PSP
0.0
0.5
1.0
VGS (V)
25
Non-uniform Doping
Effective body factor
Threshold voltage
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Decouple C-V and I-V
Using aSeparate
single effective
NSUB for
NSUB
I-V for
andboth
C-VI-V and C-V
Shift of Vth due to
lateral halo doping
New C-V fit does not
affect I-V
Achieve better fit using
alternative NSUB for C-V
only
An IBM process using halo doping (from J. Watts)
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Parameter Extraction Flowchart
For PSP 103
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Outline
 PSP project overview
 Introduction to bulk PSP
 Recent development in bulk PSP
► PSP-SOI
 PSP-MGFET
 Conclusions
29
Impact of EVB on DC-IV
 EVB affects IDS linearity at high VGS
 Model can faithfully reproduce the
“humps” in gm characteristics
Drain current, mA
3
2.5
2
1.5
1
0.5
0
0
W/L = 3m/0.13m
2.5
model with EVB
model without EVB
measurement
2
1.5
1
0.5
0
0
1
3.5
Transconductance, mS
Drain current, mA
3
0.5
Drain voltage, V
0.5
1
Gate voltage, V
3
2.5
2
1.5
1
0.5
0
0
0.5
1
Gate voltage, V
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Parasitic BJT
 qB incorporates the Early effect and high level injection
 Recombination current in neutral body region
 Junction diffusion capacitance
G
S
(rec )
I BS
body
D
I BJT
BOX
Substrate
I BJT  I BJT,SAT

 VBS 
 VBD   1


  
 exp
 exp

 φT 
 φT   qB

Bipolar current. mA
0
10-1
10-2
10-3
10-4
10
-5
10-6
10-7
10-8
10-9
10
-10
10
0
model
data
ID
VE=VS=0 V
VG= -0.3 V
VD=VB
IB
0.5
VBS, V
1
W/L = 3m/0.055m
31
Bias-Dependent Body Resistance Model
 Bias independent
R body 
W
R bsh
L
 Bias dependent
Rbody  Rbody W,L,bias
tox
G
QBf
D
S
Qjs
Qnbr
Qjd
L
tsi
tbox
Substrate
 Mobile charges in neutral body region
Based on Freescale in-house
Rbody model (G. Workman et al.)
R body
W2

μBQ nbr
Qnbr  qNEFF t SI WL  QB
 Total bulk charge
Q B  Q Bf  Q js  Q jd  Q E
 B: mobility of majority carriers in the body
 Qnbr: total mobile majority charge in the neutral body region
32
Example: 65nm PD/SOI H-gate
IS
Bs
Body resistance (M )
3.5
S G D
Bf
+
-
If
VBS
nonlinear model
data
3
2.5
2
VbGB = 0 V
1.5
Junction leakage
1
0.5
0
-1
VbGB = -10 V
-0.5
0
0.5
1
Body bias (V)
W/L = 3m / 65nm
VGS = -0.3 V; VDS = 0 V
33
Excess Low Frequency Noise Modeled
Automatically
 Excess LF noise is caused by floating
body effect
-8
10
fc 
f0
 f
1  
 fc



2
1
2 req Ceq
W. Jin et al T-ED 1999
; req
 dI 
  bs 
 dVbs 
1
Ceq  CSB  CDB  CEB  CGB

nT
I bs
Drain noise voltage
spectral density, V2/Hz
S (f ) 
-10
10





  0.7,







VDS=0.6,
0.8,
0.9V
-11
10
CGB
CSB
2
3
4
5
6
7
8
9
D
CDB
req
1
10 10 10 10 10 10 10 10 10
Frequency, Hz
G
S
Excess noise
-9
10
PD/SOI floating body
W/L = 3m/0.055m
CEB
E
34
Body-Contacted PD/SOI
VGS= 0.2, 0.4, 0.6, 0.8, 1.0, 1.3 V
VBS = 0.0 V
2.5
3.5
1.5
1
0.5
1
0
1
0
0.5
0
1
2
0
2
1
g
-3
, mS
0
DS
DS
-2
10
-1
10
-2
10
VDS, V
10
0
10
-1
10
0.5
VDS, V
1
10
-1
10
10
-3
0
0
10
-2
10
-3
1
1
10
-2
10
-4
2
1
10
1
10
10
g
, mS
-1
0.5
VDS, V
10
10
10
0
VDS, V
10
10
0
1
, mS
1
0.5
0.5
VDS, V
10
0
0
DS
0.5
VDS, V
, mS
, mA
1
g
0
DS
2
0.5
0
g
2
55nm
3
DS
, mA
DS
2
65nm
3
I
, mA
1
75nm
2.5
DS
1.5
10
4
I
L=150nm
I
, mA
DS
4
3
2
I
W=3m, L=55nm-150nm
-3
0
0.5
VDS, V
1
10
0
0.5
1
VDS, V
35
BC PD/SOI Cont’d
VBS= -0.2, 0, 0.2, 0.4, 0.6 V
VDS= 0.05 V
0
-1
DS
-4
10
75nm
-5
10
-6
0.5
1
-4
10
65nm
-5
0
0.5
1
-4
10
55nm
-5
-6
10
10
VGS, V
-3
10
10
-6
10
0
-3
10
10
-6
10
, mA
, mA
-3
10
I
, mA
DS
L=150nm
-5
10
10
10
I
, mA
-4
10
I
DS
-3
-2
-2
10
10
10
10
-2
10
-1
-1
10
-2
10
10
DS
-1
10
0
0
10
I
0
10
0
VGS, V
0.5
0
1
0.5
1
VGS, V
VGS, V
1
0.8
0.6
0.6
0.2
0.1
0
0.5
VGS, V
1
, mS
mS
0.2
0
0
0.4
0.5
VGS, V
1
0.4
0.2
0
0
0.6
g
0.4
mS
0.2
g
, mS
mS
0.3
, mS
0.8
0.4
g
g
mS
, mS
0.5
0.8
0
0
0.5
VGS, V
1
0
0.5
1
VGS, V
36
PSP-SOI-PD Harmonic Balance Simulation
-50
n=1
D
I , dB
-100
-150
2
-200
3
-250
4
-300
-350
-60
5
PSP-SOI simulation
Theoretical slope
-50
-40
-30
-20
V IN, dB
PD/SOI floating body; W/L = 3m/0.055m
37
Outline
 PSP project overview
 Introduction to bulk PSP
 Recent development in bulk PSP
 PSP-SOI
►PSP-MGFET
 Conclusions
38
DGFET and SGFET Structures
Double Gate
Surrounding Gate
39
Symmetric Linearization for DGFET
1
1
Exact (Lu et al., TED 2006)
Symmetric linearization
0.6
0
0.4
SL formulation:
0.2
0
0
Relative error [%]
Normalized Cgg
0.8
0.5
1
Vg- [V]
1.5
-1
2
40
Symmetric Linearization for SGFET
1
2
Exact (Yu et al., TED 2007)
Symmetric linarization
0.6
0
0.4
Relative error [%]
Normalized Cgg
0.8
0.2
0
0.5
1
Vg- [V]
1.5
-2
2
41
Conclusions
 Surface-potential-based approach to MOSFETs of all kinds is an
undisputed industry standard
 PSP model includes all relevant device physics and its accuracy is
verified down to 32 nm technology node
 PSP model structure is flexible and is easily extendable to enable the
model to serve as gateway for advanced CMOS design in the
coming years
 Work is in progress to add the latest developments and to maintain
and upgrade the model code
 PSP family includes bulk, varactor, SOI and FinFET models
42
Acknowledgements
 PSP developers are grateful to C. McAndrew, P. Bendix, J. Watson,
and G. Workman for numerous stimulating discussion of the subject
of compact modeling
 The development of PSP is continuously funded in part by SRC
since 1998
 Testing and implementation of PSP is funded in part by CMC
 Past funding from LSI Logic, Mentor Graphics, Freescale, IBM and
TI is gratefully acknowledged
43