Transcript Digital Logic Structures - University of Cincinnati

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Master
title
The Von Neumann Model
style
• Proposed in 1946
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–Secondtolevel
–Second
•Third levellevel
•Third
level
–Fourth
level ideas:
• Two
main
–Fourth
level
»Fifth level
• »Fifth
components
level
of an architecture
• how instructions are processed
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Master title
Basic
Architecture
style
•
contains instructions that comprise
memory
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Master text styles
–Secondtolevel
a program
–Second
•Third levellevel
•
•
•
•
•Third
–Fourth level
level
executes the instructions
processor
–Fourth
level
»Fifth level
»Fifth level
input
output orders the execution of the instructions
control unit
an instruction is a unit of work
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Organization
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style
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–Secondtolevel
–Second
•Third levellevel
•Third
–Fourth level
level
–Fourth
level
»Fifth level
»Fifth level
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Organization
ClickLC-2
to edit
Master title
style
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–Secondtolevel
–Second
•Third levellevel
•Third
–Fourth level
level
–Fourth
level
»Fifth level
»Fifth level
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Memory
style
•
•
Recall the 22 by 3 memory of Ch. 3
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–Secondtolevel
more
realistically, many PCs are
–Second
•Third levellevel
•Third
level
level
•–Fourth
228 address
space (256 MB)
–Fourth
level
»Fifth level
•»Fifth
8 bit
addressability
level
• LC-2 is 216 by 16
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Master title
Special
Registers
style
• MAR: memory address register
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–Secondtolevel
•
• –Second
location to
be read/written
level
•Third level
•Third
level
–Fourthmemory
level
MDR:
•
–Fourth
level
»Fifth level
data level
value
»Fifth
data register
to be read/written
• what has to be asserted for a value to be
written?
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Master title
Contents
of edit
Memory/Registers
style
00
01
10
11
01 0
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to
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Master
–Second
level
111
MAR
–Second
level
0•Third
0 1 level
001
–Fourth
level
0•Third
0 0 level
MDR
WE
111
0
–Fourth
level
»Fifth level
»Fifth level
Memory
00
01
10
11
text styles
Causes memory to be read into MDR
01 0
01 0
110
1
111
110
0 0 0 Causes memory to be written from MDR
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•
•
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Master title
Processing
style
may contain specialized functional units
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tolevel
edit only
Master
textAND,
stylesNOT
LC-2
ALU
has
ADD,
–Second
–Second
operations
•Third levellevel
•Third
–Fourth level
level
–Fourth
level
»Fifth level
»Fifth level
size of information processed by ALU
is the word length of the computer
• LC-2 has 16 bit word length
•
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Master
title
Registers
style
•
•
•
temporary storage used by CPU for
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tolevel
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–Second
intermediate
values of computations
–Second
level
•Third level
•Third
level
DEC
Alpha
–Fourth
level has 32 registers
–Fourth
level
»Fifth level
LC-2
has 8 (R0-R7)
»Fifth level
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9
ClickInput/output
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style
• peripherals
thatMaster
allow computer
to be
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text
styles
–Second level
connected
to the outside world
–Second
level
•Third level
•Third
level
–Fourth
level
• get
data/programs
in and out
–Fourth
level
»Fifth level
»Fifth level
• input:
keyboard, mouse, scanners, disks
• output: monitor, printers, disks
• floppy, hard drives, zip disks, CDs
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ClickControl
to editUnit
Master title
style
• keeps track of current instruction in a
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tolevel
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–Second
program
and
current step in executing an
–Second
level
•Third level
instruction
•Third
–Fourth level
level
–Fourth
level
»Fifth level
• coordinates
activities between components
»Fifth level
• registers
• IR: holds current instruction
• PC: holds address of next instruction
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Master
title
Discuss LC-2 as an Example of
style
a Von Neumann
Architecture
• some
registers
notMaster
yet discussed
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text styles
–Second level
•
•
•
•
–Second
level
KBSR:
status
of keys struck
•Third level
•Third
–Fourth level
level
KBDR:
value of key struck
–Fourth
level
»Fifth level
»Fifth level
CRTSR:
status of monitor
CRTDR: value to be written on monitor
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title
Central ideas of VN architecture
style
•
•Click
editdata
Master
textsequences
styles of
Instructions
and
are both
–Secondtolevel
–Second
level
bits
stored
in
memory
•Third
level
•Third
–Fourth level
level
–Fourth
level
»Fifth level
»Fifth level
•
One instruction at a time is executed
(sequentially)
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•
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to edit
Master title
Instruction
Processing
style
2 parts:
• opcode: what is to be done
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tolevel
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–Second
• –Second
operands:
what data is manipulated
level
•Third level
•Third
–Fourth level
level
–Fourth
level
»Fifth level
• LC-2
instruction:
»Fifth level
• [15:12] opcode
• [11:0] how to locate operands
• How many distinct operations in LC-2?
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•
•
•
ClickADD
to edit
Master title
Example
style
opcode for ADD is 0001
ADD
requires
values
totext
be pre-stored
in
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to
edit
Master
styles
–Second level
registers,
then the result is stored in a
–Second
level
•Third level
register
•Third
–Fourth level
level
–Fourth
level
»Fifth level
Operands
from register2 and register 3,
»Fifth level
result put in register 1
opcode
register 1
register 2
not used
register 3
15………12
11……………9
8……….….6
5…..……..3
2………...0
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15
ClickLDR
to edit
Master title
Example
style
•
•
•
load register with a value from memory
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tolevel
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Master
text styles
causes
value
of 2nd
register
to be added
–Second
–Second
level
•Third
level
to •Third
offsetlevel
value, and value at that location
–Fourth level
is –Fourth
stored
in 1st register
level
»Fifth
level
»Fifth level
opcode for LDR is 0110
opcode
15………12
register 1
11……………9
register2
8…..…….6
offset
5………….0..
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Master
title
LDR cont’d
style
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0110
010
–Secondtolevel
–Second level
•Third level
15………12
11……………9
Master
011 text styles
000110
8……………….6 5………………….….0
•Third
–Fourth level
level
value–Fourth
(2ndlevel
register
+ offset) stored in 1st register
level
»Fifth
»Fifth level
contents of memory in location (R3 + 6) goes into R2
called base + offset addressing mode
addressing mode: describes the computation needed to
yield values for operands
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The Instruction
Cycle title
style
•
•
•
Sequence
ofedit
steps
carried
out
by control
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to
Master
text
styles
–Second
level instructions
unit
to
execute
–Second
•Third levellevel
•Third
level
–Fourth phases
level
called
–Fourth
level
»Fifth level
level all may not be used by each
6 »Fifth
phases,
instruction
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title
Fetch-Decode-Execute
Cycle
style
1. fetch: gets next instruction from
•Click
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Master text styles
memory
into
–Secondtolevel
–Second
level
•Third
level
MAR
PC
•Third
level
–Fourth level
–Fourth
level
»Fifth
level
MDR
contents of memory at
»Fifth level
location given in MAR
IR
MDR
PC PC + 1
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title
Fetch-Decode-Execute
Cycle
style
2. decode: in LC-2, a 4 to 16 decoder
looks
at the
4 opcode
bits
and
asserts the
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Master
text
styles
–Second level
appropriate
output line to indicate the
–Second
•Third levellevel
instruction
•Third
–Fourth level
level to be executed
–Fourth
level
»Fifth level
»Fifth level
3. evaluate address: if a memory address is
to be accessed (as in LDR) this phase
computes the address
not needed in ADD
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Fetch-Decode-Execute
Cycle
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title
4. fetch operands: obtains
style values of
operands
LDR gets
value
from
memory
into
a register
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to
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Master
text
styles
–Second level
–Second
ADDlevel
getslevel
values from registers
•Third
•Third
–Fourth level
level
5. execute:
–Fourth
level carries out instruction in
»Fifth level
»Fifth
ALUlevel
not needed in LDR
6. store result: write result to designated
destination
increment PC, go to 1
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MasterOrder
title
Changing
Execution
• 2 issues:
style
• •Click
how toto
alter
the
execution
order?
edit Master text styles
–Second level
• –Second
how to stop
levelat the end of a program?
•Third level
•Third
–Fourth level
level
•
–Fourth
level
»Fifth level
have
change
»Fifthto
level
the PC before the next
fetch phase
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•
ClickInstruction
to edit Master
Types title
3 kinds of instructions:
style
• operate (e.g., ADD)
tolevel
edit
• •Click
move data
(e.g.,Master
LDR) text styles
–Second
–Second
level
•Third
level
• control instruction (e.g., JMPR)
•Third
–Fourth level
level
–Fourth
level
»Fifth level
»Fifth level
• control instructions load the PC
during the execute phase
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ClickJMPR
to edit
Master title
Example
style
•
•
•
•
puts an address in the PC
•Click
tolevel
edit Master
styles
useful
for executing
loops or text
skipping
around
–Second
–Second
level
•Third
level
uses •Third
base +level
offset addressing
–Fourth level
–Fourth
level is 1100
»Fifth
level
JMPR
opcode
»Fifth level
opcode
15………12
not used
11……………9
register1
8……………….6
offset
5……………….0
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toItedit
Master title
Tying
All Together:
Examplestyle
Algorithm
1. Initialize
aedit
counter
to 12
and
a sum to 0.
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to
Master
text
styles
–Second level
2. If–Second
counter
is 0, go to step 7.
•Third
levellevel
•Third
–Fourth level
level
3. –Fourth
levelget next data item;
»Fifthelse
level
»Fifth level
4.
add item to sum;
5.
decrement counter;
6. Output “sum is:” sum.
7. End
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Machine
Example
Click toLanguage
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title
Corresponding Assembly Language
style
3000 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0
3001 0•Click
1 0 1 0 1 1to
0level
1edit
1 1 0 0Master
000
–Second
3002 0–Second
1 0 1 0 level
1 0 0level
10100000
•Third
3003 0•Third
0 0 1 0 level
10010101100
–Fourth
level
3004 0–Fourth
»Fifth
0 0 0 level
0 level
10000001010
3005 0»Fifth
1 1 0 level
100001000000
3006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0
3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1
3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1
3009 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0
LEA R1, x3100
AND R3, 0
AND R2, 0
ADD R2, 12
BRz R2, x300A
LDR R4, M[R1]
ADD R3, R4
ADD R1, 1
ADD R2, -1
BRnzp x3004
text styles
opcodes
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Example
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to edit
Master title
// assumes an array style
holding 12 integers
// •Click
has been
declared
and
initialized
to
edit
Master
text
styles
–Second level
LEA R1, x3100
–Second
int sum
=level
0; level
•Third
AND R3, 0
•Third
–Fourth level
level
for (int
=level
0; i < 12; i++) AND R2, 0
–Fourth
»Fifthi level
»Fifth level
ADD R2, 12
sum = sum + array[i];
BRz R2, x300A
LDR R4, M[R1]
ADD R3, R4
ADD R1, 1
ADD R2, -1
BRnzp x3004
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Example continued
style
Data memory containing 12 values to sum
Register s used
0
0 0 Master
0 0 0 0 0 text
0 1
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to
edit
styles
R1
– address
–Second level
3100 0 0 0 0 0 0
3101 0 0 0 0 0 0
3102 •Third
0 0 0 0level
0 0
3103 •Third
0 0 0 0level
0 0
–Fourth
level
3104 –Fourth
0 0 0level
0level
0 0
»Fifth
3105 »Fifth
0 0 0level
0 0 0
3106 0 0 0 0 0 0
3107 0 0 0 0 0 0
3108 0 0 0 0 0 0
3109 0 0 0 0 0 0
310A 0 0 0 0 0 0
310B 0 0 0 0 0 0
310C 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–Second level
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
of
data value
R2 – number of
data values left
to add
R3 – Sum of values
which have been
added
R4 – current value
to add to the sum
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to
edit
Master
title
Example continued
style
Contents of Registers, first time thru the loop
•Click
edit
Master text styles
(in
hexadecimal)
–Secondtolevel
–Second
•Third levellevel
•Third
level
–Fourth
level
3100
3101
R1
–Fourth
level
»Fifth level
»Fifth000C
level
R2
R1
R2
000B
R3
0000
R3
0001
R4
0001
R4
0001
After
instruction
3005
After
instruction
3008
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Example continued
style
Contents
of to
Registers,
2nd timetext
thru styles
the loop
•Click
edit
Master
–Second level
(in hexadecimal)
–Second
level
•Third level
•Third
–Fourth level
level
3101
R1 –Fourth
level
»Fifth
level
»Fifth level
000B
R2
R1
3102
R2
000A
R3
0001
R3
0003
R4
0002
R4
0002
After
instruction 3005
After
instruction 3008
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Example continued
style
rd time thru the loop
Contents
of
Registers,
3
•Click
edit Master text styles
–Secondtolevel
(in hexadecimal)
–Second
•Third levellevel
•Third
level
–Fourth
level
3102
3103
R1–Fourth
level
»Fifth level
R1
»Fifth000A
level
R2
R2
0009
R3
0003
R3
0006
R4
0003
R4
0003
After
instruction 3005
After
instruction 3008
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Example continued
style
th time thru the loop
Contents
of
Registers
,
12
•Click
edit Master text styles
–Secondtolevel
(in hexadecimal)
–Second
•Third levellevel
•Third
level
–Fourth
level
310C
310D
R1 –Fourth
level
»Fifth level
»Fifth
level
0001
R2
R1
R2
0000
R3
0042
R3
004E
R4
000D
R4
000D
After
instruction 3005
After
instruction 3008
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Click to for
editProgramming
Master title
Foundation
•
•
•
•
•
styleprograms next
When you write C++
quarter, you know they are translated to
•Click
edit Master
styles
assembly
language
by atext
compiler
–Secondtolevel
–Second
level
•Third
level
then
translated
to
machine
language
to
•Third
level
–Fourth level
be–Fourth
executed
by the hardware
level
»Fifth
level
»Fifth level
hardware consists of functional units in
Von Neumann architecture
functional units are made up of gates
gates are implemented by transistors
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