Transcript Presentation Part A - High Speed Digital Systems Lab
High Speed Digital Systems Lab By :
Genady Paikin, Ariel Tsror
Supervisors :
Inna Rivkin, Rolf Hilgendorf
Page 1
Agenda
Introduction
Learning Process
Environment
LabView
LabView Problems
JTag/ChipScope
Powerpoint Templates
Page 2
Agenda
Hardware
Implemented Blocks
Xilinx Synthesis Part B Blocks
System
Verification Methods Full System Integration
Powerpoint Templates
Page 3
Introduction
The project is part of the Sub-Nyquist sampling and reconstruction card.
Our goal is to implement DSP unit on FlexRio FPGA cards under NI LabView environment.
Includes integration to the full system.
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Introduction Page 4
High Level Architecture
Xampling
Introduction
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Page 5
Sampling stage
The sampling stage contain two units:
Xampling sampling card.
Expand.
Xampling 4X62.5 Mhz digital 12X20.8 Mhz digital Analog in
A/D 62.5 Mhz (250 1:4 decim.) Expand 1:3 Powerpoint Templates
Introduction Page 6
CTF module
Goal : Detects the Support of x(t) and forwards it to DSP unit.
Triggered by :
Initiation.
SCD interrupt.
Based on the OMP (Orthogonal Matching Pursuit) algorithm.
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Introduction Page 7
DSP module
Goal: Reconstructs the signal from the samples.
The unit receives the samples from the memory (latency fifo), matrix A from the memory, and signal support from the CTF unit.
The support and samples are coordinated by the latency fifo.
The unit performs pseudo-inverse of matrix A (calculates As) using the signal support, that is received from the CTF.
Finally the unit multiplies the delayed signal with matrix As.
Introduction Page 8
SCD module
Goal: Detects a change of the signal support.
The unit uses the signal energy to decide if the CTF needs to recalculate the signal support.
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Introduction Page 9
Learning Process
Composed of 2 independent processes :
Algorithm :
o
System main concept.
o
Sampling stage (Xampling and Expand).
o o
CTF module.
DSP module.
LabView :
o
LabView main concepts.
o o o
FPGA under LabView.
Integration.
Implementing basic units.
•
Reading matrix from file to memory on FlexRio FPGA using LabView environment
.
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Learning Process Page 10
LabView
LabView is a System design platform and development environment for a visual programming.
LabView allows simple integration of several FPGAs together and simple control of the FPGAs using Host VI including importing / exporting file to / from the system.
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Environment Page 11
LabView
There are two options of using VHDL in LabView VIs :
CLIP node.
IP integration node.
Environment
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Page 12
LabView
CLIP Node
Environment
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Page 13
LabView
CLIP Node method
Environment
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Page 14
LabView
Environment
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IP Integration Node
Page 15
LabView – Host VI
3 FPGAs
Environment
Writes to FPGA (Clip method)
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Page 16
LabView – Target VI
Reads from Host VI
Environment
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Page 17
LabView Problems
Does not support array implementation in VHDL. Does not support our packages when using VHDL.
Very long compilation process.
LabVIEW software tools don't support multi-core or even multi-thread processes.
LabVIEW does not allow stage separation (compilation, elaboration, synthesizing, rout & map) in order to isolate or at least to save time.
Lack of debug tools. There is no access to the inner signals in the FPGA. ChipScope/JTag is not supported (see JTag-issues) Lack of tutorials that show usage of VHDL in LabVIEW.
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Environment Page 18
LabView Problems
Environment
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Page 19
LabView Problems
Environment
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Page 20
LabView Problems
Environment
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Page 21
JTag / ChipScope
JTag is not supported under LabView environment!
A critical issue because we cannot debug our design in the real hardware.
Environment
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Page 22
Block Diagram
Matrix A (from memory) Signal support (from CTF)
DSP
Pseudo Inverse As+ A1 A2 Signal ’s sample (from memory) Multiplication Reconstructed signal Powerpoint Templates
Hardware Page 23
Pseudo-Inverse Diagram
As
QR Dec
R matrix
Matrix Inverse
Q matrix
Mat Mult Interface
R_inv Pinv(As) Powerpoint Templates
Hardware Page 24
Implemented Blocks
QR-Decomposition.
Matrix Multiplier Interface.
This blocks are Xilinx-oriented.
Hardware
Powerpoint Templates
Page 25
Xilinx Synthesis
While we were trying to convert Altera oriented code to Xilinx one, we unfortunately discovered that Altera’s synthesis is much stronger and also more efficient than the Xilinx one. Code that includes complicated loops (implementing muxes) cannot be synthesized at all.
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Hardware Page 26
Xilinx Synthesis
Hardware
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Page 27
Part B Blocks
Matrix Inverse – upper triangular matrix inverter.
Real Time Multiplier.
SCD (Signal Change Detector).
Hardware
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Page 28
Verification Methods
Small Blocks Verification via Full DSP Block.
After a block is changed from Altera to Xilinx, a full ModelSim simulation is executed.
Furthermore, the block is burned on the FPGA using LabView in order to confirm LabView compatibility and time constrains.
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System Page 29
Verification Methods
We verify that Matrix A is inverted correctly using Matlab.
System
5 10 15 20 5 10 15 20 Powerpoint Templates
Page 30
Full System Integration
Full system integration will be executed during Part B.
Once we confirm that all the Xilinx oriented units work well with LabView, we will replace all the relevant mathscript blocks with real hardware ones.
System
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Page 31
The End
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