Transcript Document

+4
A
D
D
m
u
x
A
D
D
shift 2
BRANCH CTRL
P
C
rs
R1
R Data
1
addr
rt
instr
rd
m
u
x
zero
R2
ALU
R Data
2
WR
addr
r data
INSTR
MEM
w data
W Data
DATA
MEM
Single Cycle
immed
16
Datapath
ALU
CTRL
sign extend
op
32
m
u
x
Multicycle Datapath
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
B
+4
WR
w data
rd
MEMORY
W Data
M
R
fetch
REGISTERS
decode
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
execute
(1..3)
alu
out
Multicycle with Exception/Interrupt Handling
jump addr
shift 2
handler addr
P
C
rs
addr
rt
data
zero
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
overflow
rd
MEMORY
PC - 4
W Data
M
R
E
P
C
REGISTERS
immed
sign
extend
shift 2
00
01
op
fctn
shamt
CONTROL
10
11
C
A
U
S
E
to?
to?
Pipelined Datapath
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
data1
write
data2
Instruction
Memory
m
u
x
A
L
U
addr
m
u
x
r data
w data
w data
Data
Memory
sign
extend
IF
ID
EX
MEM
WB
add rd, rt, rs: Fetch
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
Instruction
Fetch:
Load IR,
PC = PC
IF Register
+4
Contains IR
and PC, and
other values
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
m
u
x
add rd, rt, rs: Decode
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
ID register contains
A, B, and other
values
Instruction Decode: Load data1,
data2 into A, B (part of ID)
m
u
x
add rd, rt, rs: Execute
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Execute: sum of A, B into
ALUout (part of EX)
m
u
x
add rd, rt, rs: MEM
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
MEM: (no memory access)
save ALU result in MEM
m
u
x
add rd, rt, rs: WB
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Write Back: write sum to
register rd
m
u
x
sw rt, offset(rs): Fetch
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
m
u
x
sw rt, offset(rs): Decode
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
ID gets rs, rt,
and
immed+sign
ext
m
u
x
sw rt, offset(rs): Execute
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
EX gets
rs+offset,
and rt
m
u
x
sw rt, offset(rs): MEM
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Write Data
Memory
[address] with
rt value;
nothing of
interest in WD
Data
Memory
sign
extend
m
u
x
sw rt, offset(rs): WB
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
Registers not
written in this
instruction
sign
extend
m
u
x
A program fragment with 6
instructions
1. add r1, r2, r3
2. sw r4, 2232 ( r5 )
3. addi r6, 55
4. lw r7, 1001 (r8)
5. bneq r7, r6, -3
6. add r1, r7, r0
A program fragment with 6
instructions
1. add r1, r2, r3
2. sw r4, 2232 ( r5 )
3. addi r6, 55
4. lw r7, 1001 (r8)
5. slti r7, r6, -3
6. add r1, r7, r0
Six instructions 1,2,3,4,5,6: Step 1
+4
add
add
Registers
m
u
x
P
C
addr
shift
read1
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Fetch 1
m
u
x
Six instructions 1,2,3,4,5,6: Step 2
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Fetch 2
Decode 1
m
u
x
Six instructions 1,2,3,4,5,6: Step 3
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Fetch 3
Decode 2
Execute 1
m
u
x
Six instructions 1,2,3,4,5,6: Step 4
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Fetch 4
Decode 3
Execute 2
Mem 1
m
u
x
Six instructions 1,2,3,4,5,6: Step 5
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Fetch 5
Decode 4
WB 1 (add)
Execute 3
Mem 2 (sw)
m
u
x
Six instructions 1,2,3,4,5,6: Step 6
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Fetch 6
Decode 5
WB 2 (sw: no write)
Execute 4
Mem 3
(addi)
m
u
x
Six instructions 1,2,3,4,5,6: Step 7
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Decode 6
WB 3 (addi)
Execute 5
Mem 4
(lw)
m
u
x
Six instructions 1,2,3,4,5,6: Step 8
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Execute 6
WB 4 (lw)
Mem 5 (slti)
m
u
x
Six instructions 1,2,3,4,5,6: Step 9
+4
add
add
Registers
m
u
x
addr
shift
read1
P
C
read2
out
write
data1
data2
Instruction
Memory
m
u
x
A
L
U
addr
r data
w data
w data
Data
Memory
sign
extend
Mem 6
(add)
WB 5 (slti)
m
u
x
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
B
+4
WR
w data
rd
MEMORY
W Data
M
R
add rd, rs, rt
REGISTERS
immed
sign
extend
shift 2
fetch: load ir,
pc=pc+4
decode
op
fctn
shamt
ALU
CTRL
execute
alu
out
Multicycle Datapath
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
B
+4
WR
w data
rd
MEMORY
W Data
M
R
fetch
REGISTERS
decode
immed
op
fctn
sign
extend
shamt
shift 2
execute
ALU
CTRL
alu
out
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
add rd, rs, rt
REGISTERS
fetch
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
decode:load
A,B registers
execute
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
add rd, rs, rt
REGISTERS
fetch
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
decode
execute (2 cycles)
load alu out; load
register
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
bne rs, rt, addr
REGISTERS
immed
sign
extend
shift 2
fetch: load IR,
pc=pc+4
decode
op
fctn
shamt
ALU
CTRL
execute
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
bne rs, rt, addr
W Data
M
R
REGISTERS
immed
op
fctn
sign
extend
shamt
fetch
shift 2
ALU
CTRL
decode: load A
B, aluout =
immediate
(extendx2)+pc
execute
jump addr
shift 2
z
P
C
rs
addr
rt
data
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
bne rs, rt, addr
W Data
M
R
fetch:
REGISTERS
decode:
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
execute: (1 cycle)
compare A, B
(holding rs, rt); if
neq, load pc with
aluout (holding
branch addr)
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
lw rt, offset ( rs)
REGISTERS
immed
sign
extend
shift 2
fetch: load IR,
pc=pc+4
decode
op
fctn
shamt
ALU
CTRL
execute
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
lw rt, offset ( rs)
REGISTERS
fetch
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
decode: load A B;
offset is ready
execute
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
lw rt, offset ( rs)
REGISTERS
fetch
decode
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
execute: (3 cycles):
load aluout with addr,
load mr with data,
load register rt
Multicycle Datapath
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
alu
out
B
+4
WR
w data
rd
MEMORY
W Data
M
R
Try these:
REGISTERS
sw rt, off(rs)
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
j
addr
andi rd,rs,rt
Multicycle Datapath
P
C
rs
addr
rt
data
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
B
+4
WR
w data
rd
MEMORY
W Data
M
R
REGISTERS
immed
op
fctn
sign
extend
shamt
shift 2
ALU
CTRL
alu
out
R-Format: add, slt, sll
P
C
rs
R1
addr
rt
R Data
1
R2
instr
ALU
R Data
2
WR
rd
INSTR
MEM
DATA
MEM
W Data
fctn
op
shamt
ALU
CTRL
+4
A
D
D
m
u
x
A
D
D
shift 2
BRANCH CTRL
P
C
rs
R1
R Data
1
addr
rt
zero
R2
ALU
instr
R Data
2
WR
INSTR
MEM
DATA
MEM
W Data
immed
ALU
CTRL
sign extend
16
32
op
I-Format bne
I-Format lw, sw
P
C
rs
R1
addr
rt
R Data
1
zero
R2
instr
ALU
addr
R Data
2
R Data
WR
INSTR
MEM
W Data
W Data
DATA MEM
immed
ALU
CTRL
sign extend
16
op
32
m
u
x
+4
A
D
D
m
u
x
A
D
D
shift 2
BRANCH CTRL
address
P
C
R1
addr
R Data
1
zero
R2
instr
ALU
R Data
2
WR
INSTR
MEM
DATA
MEM
W Data
ALU
CTRL
op
J-Format
Multicycle Datapath
jump addr
P
C
rs
addr
rt
data
shift 2
z
R1
R Data
1
A
ALU
R2
I
R
R Data
2
B
+4
WR
w data
rd
MEMORY
W Data
M
R
fetch
REGISTERS
decode
immed
op
fctn
sign
extend
shamt
shift 2
execute
ALU
CTRL
alu
out