Transcript SETA Estrutura e ambiente operacional
IBM Mainframes Assembler
Alberto Romano Schiesari – www.profars.com
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Presentation
Thanks for using this presentation. You are free to use it.
I appreciate if you refer to the author when using it.
I’m sorry about the language errors; my english isn’t so good; I’ll appreciate if you send me any corrections and suggestions to optimize the comprehension to the reader.
The same is valid for any technical error; please help me to make this an error-free text.
Alberto Romano Schiesari – São Paulo - Brazil www.profars.com [email protected]
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Summary
Appendix - Instructions summary
Appendix -
Some EBCDIC characters Some ASCII characters
Appendix -
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Summary
Assembler commands (alphabetically)
These aren’t in the scope of this course: MNOTE, SETA, SETB, SETC AREAD, MACRO, MEXIT, MEND ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, Alberto Romano Schiesari – www.profars.com
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Summary
Machine instructions (alphabetically)
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Architecture
SYSTEM ARCHITECTURE
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Architecture – some components
System CPU (CISC, RISC, hybrid) CISC = Complex Instruction Set Computer Variable length instructions In each instruction, explicitly or implicitly, one must specify: - The operation to be done - The operands used (places with data to process and places to store results): their address !
Operands’ length - Data format RISC = Reduced Instruction Set Computer Fixed length instructions; e.g. 4 bytes; the execution (average) is faster Alberto Romano Schiesari – www.profars.com
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Architecture – some components
Note that...
Mainframes and PC’s = CISC
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Architecture – some components
Storage byte addressing (access)
Real storage? Virtual Storage? In virtual storage systems, hardware must talk with software to achieve the use of virtual storage
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Architecture – some components
In symbolic languages, the reference to a field is made:
Using its name (variable or constant) or
Using its contents (literal) MOVE 1 TO NPAGE.
NPAGE = 1 Alberto Romano Schiesari – www.profars.com
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Architecture – some components
In machine language, referencing a field is made using its address, one must specify a number (hexadecimal / binary) which is the field’s address. There is NO reference to names. This is called ADDRESSING.
The hexadecimal number must have 6 or 8 digits. With 6 digits, if we have to store the address in a storage field, at least 3 bytes are needed. With 8 digits, if we have to store the address in a storage field, 4 bytes are needed. (in many of our examples we use smaller numbers, with 2 or 3 digits, just to simplify the visual and the computing)
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Architecture – some components
Storage bytes addressing (access) Program Instructions F8 3 0 B004 C82F 1C Areas 00 00 00 1C
MOVE instruction in machine language, indicating : (a) it is MOVE [F8]; (b) Sender [literal 1] length 0 (meaning = 1 byte) (c) Receiver [NPAGE] length 3 (meaning 4 bytes) (d) Sender [literal1] address C82F (e) Receiver [NPAGE] address B004 For now forget why and how, but believe me: x’B004’ is the NPAGE address and x’C82F’ is the literal address. Sender field [literal with contents 1]
It has an address !
Receiver field [NPAGE variable]
It has an address !
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Architecture – some components
Storage bytes addressing (access) Real storage X Virtual Storage Add 1 to the contents of field at address x’2B40’ If the contents of the field at address x’2B40’ is not in the real storage, then we (operating system + hardware) must: - Convert address from real to virtual storage - Fetch the contents from the virtual storage to the real storage - Execute the instruction (Remember also that it can happen with the instruction, and with any or all of the operands, too...)
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Architecture – some components
Storage bytes addressing (access)
Direct addressing? Indirect addressing?
Direct addressing example
Add 1 to the field at address x’00002B40’ Indirect addressing example
Add 1 to the field at address x’2000’ + x’0B40’ Notes: (a) in fact, the field address is x’2B40’; it is expressed in a different way (x’2000’ + x’0B40’) (b) the number x’2000’ may be in a place, the number x’0B40’ in another place...
Indirect addressing example
Add 1 to the field at the address x’2000’ + x’0B00’ + x’0040’ Notes: (a) in fact, the field address is x’2B40’; it is expressed in a different way (x’2000’ + x’0B00’ + x’0040’) (b) the number x’2000’ may be in a place, the number x’0B00’ in another place, and x’0040’ elsewhere...
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Architecture – some components
Storage bytes addressing capacity
Storage length; how many “bits” does the mainframe’s CPU have?
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Architecture – some components
Storage bytes addressing capacity Address Bus = to refer to the addresses To address storage up to 64K, address bus must be 16-bit wide.
To address storage up to 16MB, address bus must be 24-bit. etc...
Data Bus = to transfer data between components To transfer (simoutaneously) a half-word, data bus must be 16-bit wide. To transfer (simoutaneously) a full-word the data bus must be 32-bit. Eetc...
Data transfer Data Bus CPU Storage Address Bus Storage address refer Alberto Romano Schiesari – www.profars.com
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Architecture – some components
CPU Instruction Set – types and characteristics
How many, what are the instructions of a CPU Instruction Set?
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Architecture – some components
CPU instruction execution
How is the instruction execution process?
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Architecture – some components
CPU instruction execution – generic process
FETCH (CPU fetchs the instruction from RAM storage to a CPU internal area; “problem”: variable length instructions
Decode = Analysis : what is the instruction length? (not needed in RISC Cpu), what is the operation to be done (wrong code? We could dubb this situation with the name 0C1...), what are the operands, etc Error? Pass control to the operating system, to solve it
OK? Operand(s) data FETCH If they are in real store, good! (Else, lots of things to do...)
Operand contents Validation Error? How about dubb it as 0C7?...
Execution : in some cases (math operations mostly), results must be stored temporarily in CPU areas OK? If needed, STORE results back in RAM storage
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Architecture – some components
Other architectural components
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Architecture – some components
OTHER architectural components
Interruption system
What are the interruptions? E.g. Time, program error (0Cx...)
I/O sub-systems
How does the comm work between controller, storage, CPU and software?
Which information does software receive after I/O operations?
Storage protection system
How does the storage protection work? Is it possible to a program to invade another?
Virtual storage system
Which is the process?
What are the page-in & page-out algorithms?
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IBM Mainframes Architecture
IBM Mainframes Architecture
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IBM Mainframes Architecture
Tribute
We own our jobs to him! Gene Myron Amdahl (1922-)
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IBM Mainframes Architecture
IBM Mainframes : architectural main components CPU ALU GR0 GR4 GR8 GR12 GR1 GR5 GR9 GR13 GR2 GR6 GR10 GR14 GR3 GR7 GR11 GR15 16 General Registers (fixed point registers) 4 bytes each FPR0 FPR2 FPR4 FPR6 4 Floating Point registers (8 bytes each) PSW 1 Special 8 byte Register named PSW (Program Status Word) etc... (cache...)
Storage (RAM) Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
IBM Mainframes : architectural main components CPU PSW cc nia etc PSW : special 8 bytes length register.
2 important “fields" :
CONDITION CODE (*) : 2 BITS. They indicate, after some instructions execution, some condition inherent to the executiosn., e.g., comparison result.
(*) Remember that this is NOT the operating system RETURN CODE (program-finish status indicator ; may be tested using JCL tool)
next instruction address (to be executed – 3 or 4 bytes, depending on the type of addressing mode/PSW) Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
BC mode PSW BYTE 0 BITS 0-5 = channel masks BIT 6 = channel 6 and above masks BIT 7 = external mask BYTE 1 BITS 8-11 = protection key BIT 12 = 0 = Basic Control Mode BIT 13 = machine-check mask BIT 14 = 1 = wait state BIT 15 = 1 = problem program state BYTES 2-3 (BITS 16-31) = Interruption code BYTE 4 BITS 32-33 = ILC = Instruction length code BITS 34-35 = CC = Condition code BITS 36-39 = program mask BYTES 5-7 (BITS 40-63) = Instruction address Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
EC mode PSW BYTE 0 BIT 0 = 0 BIT 1 = PER mask BIT 2 = 0 BIT 3 = 0 BIT 4 = 0 BIT 5 = translation mode BIT 6 = I/O mask BIT 7 = external mask BYTE 1 BITS 8-11 = protection key BIT 12 = 1 = Extended Control Mode BIT 13 = machine check mask BIT 14 = 1 = wait state BIT 15 = 1 = problem program state BYTE 2 BIT 16 = 0 BIT 17 = 0 BITS 18-19 = CC = condition code BITS 20-23 = program mask BIT 20 = fixed-point overflow mask BIT 21 = decimal-overflow mask BIT 22 = exponent underflow mask BIT 23 = significance mask BYTE 3 (BITS 24-31) = 00000000 BYTE 4 (BITS 32-39) = 00000000 BYTES 5-7 (BITS 40-63) = Instruction address
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IBM Mainframes Architecture
XA mode PSW BYTE 0 BIT 0 = 0 BIT 1 = PER mask recording BIT 2-4 = 000 BIT 5 = translation mode BIT 6 = I/O mask BIT 7 = external mask BYTE 1 BITS 8-11 = protection key BIT 12 = 1 BIT 13 = machine-check mask BIT 14 = 1 = wait state BIT 15 = 1 = program problem state BYTE 2 BIT 16 = address space mode (together with bit 5) BIT 17 = 0 BITS 18-19 = CC = condition code BITS 20-23 = program mask BIT 20 = fixed-point overflow mask BIT 21 = decimal-overflow mask BIT 22 = exponent underflow mask BIT 23 = significance mask BYTE 3 (BITS 24-31) = 00000000 BYTE 4 BIT 32 = 0 = 24 bit addressing = 1 = 31 bit addressing BYTE 4/5/6/7 (BITS 33-63) = Instruction address
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IBM Mainframes Architecture
ESA mode PSW BYTE 0 BIT 0 = 0 BIT 1 = PER mask BIT 2-4 = 000 BIT 5 = translation mode BIT 6 = I/O mask BIT 7 = external mask BYTE 1 BITS 8-11 = protection key BIT 12 = 1 BIT 13 = machine-check mask BIT 14 = 1 = wait state BIT 15 = 1 = program problem state
BYTE 2 BIT 16-17 = address space control
= 00 = Primary space mode (bit 5 = 1) = 01 = Access-register mode (bit 5 = 1) = 10 = Secondary space mode (bit 5 = 1) = 11 = Home space mode (bit 5 = 1) BITS 18-19 = CC = condition code BITS 20-23 = program mask BIT 20 = fixed-point overflow mask BIT 21 = decimal-overflow mask BIT 22 = exponent underflow mask BIT 23 = significance mask BYTE 3 (BITS 24-31) = 00000000 BYTE 4 BIT 32 = 0 = 24 bit addressing = 1 = 31 bit addressing BYTE 4/5/6/7 (BITS 33-63) = Instruction address Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
IBM Mainframes : special areas HALFWORD = area with 2 bytes and address multiple of 2 WORD ou FULLWORD = area with 4 bytes and address multiple of 4 DOUBLEWORD = area with 8 bytes and address multiple of 8 QUADWORD = area with 16 bytes and address multiple of 16
• QW • DW • FW • HW • HW • • FW HW • HW • • • DW FW HW • HW • • FW HW • HW • QW • DW • FW • HW etc.
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IBM Mainframes Architecture
IBM Mainframes : program error interruptions (0Cx) Code
0001 0002 0003 0004 0005 0006 0007
Reason OPERATION = the operation code is invalid (it doesn’t refer to any executable instruction) PRIVILEGED OPERATION = the program tried to execute a privileged instruction.
EXECUTE = Execute of another Execute instruction PROTECTION = A program instruction tried to store data outside its authorized range ADDRESSING = A program instruction referenced a non-existent address SPECIFICATION = The instruction specified something with error; e.g., an odd floating-point register DATA = The fields an instruction refers to aren’t in the correct format; e.g., adding 2 packed fields, and one of them (or both) does not meet the packed format rules.
Code Reason
0008 0009 000A 000B 000C 000D 000E
FIXED POINT OVERFLOW = The instruction uses a general register as result operand, but it isn’t large enough to fit the result FIXED POINT DIVIDE = Binary fixed-point division with zero divisor.
DECIMAL OVERFLOW = In an operation with packed fields, the receiver field isn’t large enough to fit the result DECIMAL DIVISION = Packed decimal division with zero divisor.
EXPONENT OVERFLOW = Binary floating-point operations. EXPONENT UNDERFLOW = Binary floating-point operations. SIGNIFICANCE = Binary floating-point operations.
000F
FLOATING`POINT DIVISION = Binary floating-point division with zero divisor.
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
It is needed to address : registers and storage bytes (Remember that a storage field address is the address of its leftmost byte)
DIRECT addressing : only for registers: General Registers = 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F Floating Point Registers = 0,2,4,6
There is NO DIRECT addressing to storage The INDIRECT addressing may be:
Base + Displacement
Index + Base + Displacement Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing Note that, in reality, ALL addresses specified are “real storage” addresses, as if they were in a mirror refleting the address space.
But remember that the things in real life aren’t so nice... Try this way: was once a kingdom where for each address space there was a real storage exactly equal...
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IBM Mainframes Architecture
Base + Displacement
Instructions to Main Avenue Postman : Go to the “Caliente” Restaurant Walk 850 meters, you arrived at the house where the envelope must be delivered!
Walk 850 meters =
Displacement
This is the BASE, an initial reference to start identifying the deliver address
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IBM Mainframes Architecture
Base + Displacement
Hex number in a General Register (by this time dubbed
base register
)
+
Hex number (from x’000’ up to x’FFF’) in the instruction, dubbed
displacement =
Hex number : this is the
Address
Note: the interrupted line box means that the number (address)
IS NOT in a general register, but in an internal CPU area !!!
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IBM Mainframes Architecture
Base + Displacement : specification (2 bytes) x x
x y y y
Base register x x Displacement
3 5 A C
Base Register = 3 Displacement = 5AC Address = Register 3 contents + x’5AC’ x x
D 0 8 D
Base register = 13 (D) Displacement = 08D Address = Register D contents + x’08D’ Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
Base + Displacement x x
x y y y
Base register Displacement Then:
Maximum displacement = x’FFF’ = 4095
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IBM Mainframes Architecture
Base + Displacement : examples Base Register 4 4 15 0 Base register Contents 00002000 00B2F02C 00000000 0046B28C Displacement “Direct” address (it would be necessary 4 bytes to specify it) “Indirect” Address (Base + displacement : 2 bytes are enough to specify it) B40 1A2 DB4 114 00002B40 00B2F1CE 00000DB4 00000114 4B40 41A2 FDB4 0114 The contents of register zero is NOT CONSIDERED computing an address !!!
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IBM Mainframes Architecture
Base + Displacement : Hints and tips You must use it to address “normal” addresses.
What are “normal” addresses?
Give me a break!
(Those we can express using an ... Expression)
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IBM Mainframes Architecture
Base + Displacement : Hints and tips What is an expression?
Again!?
(see in the “Assembler elements” chapter)
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IBM Mainframes Architecture
Index + Base + Shift
Instructions to Main Avenue Postman : Go to the “Caliente” Restaurant.
Walk 850 meters, you’ll arrive at the condo.
In the condo, walk 50 meters then you’ll arrive at the house where the envelope must be delivered!
Walk 850 =
Displacement
Walk 50 = Index This is the BASE, an initial reference to start identifying the deliver address
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IBM Mainframes Architecture
Index + Base + Shift
Binary number in a General Register (by this time dubbed
index register
)
+
Binary number in a General Register (by this time dubbed
base register
)
+
Hex number (from x’000’ up to x’FFF’) in the instruction, dubbed
displacement =
Hex number : this is the
Address
Note: the interrupted line box means that the number (address)
IS NOT in a general register, but in an internal CPU area !!!
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IBM Mainframes Architecture
Index + Base + Displacement : specification (2 1/2 x x x
z x y y y
bytes) Index register Base register Displacement x
7
x x
3 5 A C
Index register = 7 Base Register = 3 Displacement = 5AC Address = register 7 contents + register 3 contents + x’5AC’ x
B
x x
5 F A C
Index Register = 11 (B) Base Register = 5 Displacement = FAC Address = register B contents + register 5 contents + x’FAC’ Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
Index + Base + Displacement : specification (2 1/2 bytes) x
z
x x
x y y y
Index register Base register Displacement Then:
Maximum displacement = x’FFF’ = 4095
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IBM Mainframes Architecture
Index + Base + Displacement : examples Index Register 12 0 Index register Contents Base Register Base Register Contents Displace ment 00100000 00F4CAFE 4 10 00002000 000C8B00 B40 1F0 “Direct” address (it would be necessary 4 bytes to specify it) 00102B40 000C8CF0 “Indirect” Address (Base + displacement : 2 ½ bytes are enough to specify it) C4B40 0A1F0 4 15 00007000 00000000 4 12 00007000 00C42B06 1A2 002 0000E1A2 00C42B08 441A2 FC002 The contents of register zero is NOT CONSIDERED computing an address !!!
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IBM Mainframes Architecture
Index + Base + Displacement : hints and tips In general, one uses to address “abnormal” addresses. What is an abnormal address?
(I’m kidding...) A good example: the elements of a table.
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IBM Mainframes Architecture
Index + Base + Displacement : hints and tips Example: addressing elements of a table
BR US UK IT FR ES AR CA BE AU GE DE PT GR IR
Initial table address : Symbol = TBSTATS (converted by assembler to base + displacement)
Target element address (8th element) = Initial table address + [element length * (number of elements – 1) ] = TBSTATS + [ 2 * (8 – 1) ] = TABSTATS + 2 * 7 = TBSTATS + 14 Target element address (8th element) = Base+Displacement of TBSTATS + Index Register (e.g. 17C0A = Index reg=1, Base reg = 7, displacement = C0A) TBSTATS address : in the instruction, with format Base + Displacement = X’7C0A’
(assembler finds out base register and displacement; let’s suppose Base reg = 7, displacement = X’C0A’)
Contents of Index register : e.g. Reg 1 (
it’s our program’s responsibility to prepare) with contents = X’0000000E’
TBSTATS address in Index+base+displacement format = X’17C0A’
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing Suppose this 256 bytes storage
X’00000000’ X’00000010’ X’00000020’ X’00000030’ X’00000040’ X’00000050’ X’00000060’ X’00000070’ X’00000080’ X’00000090’ X’000000A0’ X’000000B0’ X’000000C0’ X’000000D0’ X’000000E0’ X’000000F0’
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
X’00000000’ X’00000010’
*
X’00000020’ X’00000030’ X’00000040’ X’00000050’ X’00000060’ X’00000070’ X’00000080’
The number in the base register indicates byte
X’00000090’
*
. Q: Using register 12 as base register and with its contents being x’00000000’, how many bytes one has to “walk” (shift) to, leaving the byte pointed by base
X’000000E0’
A: x’048’ = displacement (blue dotted line)
X’000000F0’
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
X’00000000’ X’00000010’
The number in the base register indicates byte
X’00000020’
*
. Q: Using register 12 as base register and with its contents being x’000000A0’, how many bytes one has to “walk” (shift) to, leaving the byte pointed by base
X’00000070’
A: x’048’ = displacement (blue dotted line)
X’00000080’ X’00000090’ X’000000A0’ X’000000B0’
*
X’000000C0’ X’000000D0’ X’000000E0’ X’000000F0’
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing See this case: Target byte = x’00000048’ ; Base register = C (contents = x’00000000’) + (Displacement) x’048’ Remember that Maximum displacement allowed = x’FFF’ In other words: general register C, while used as base register (in this example), with x’00000000’ as contents, can only be used as base register to refer to addresses from x’00000000’ to x’00000FFF’.
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing Maximum displacement allowed = x’FFF’ If an instruction needs to address 2 fields: The first with address x’00000048’, and the second with address x’00001CB0’, at the time of its execution, IT’S NEEDED MORE THAN 1 BASE REGISTER correctly prepared. We can set, for example, register C (12) with x’00000000’ and register D (13) with x’00001000’ .
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing Maximum displacement allowed = x’FFF’ The first field is addressed by base register 12: C048
Base register C (contents = x’00000000’) + Displacement x’048’ The second field is addressed by base register 13: DCB0
Base register D (contents x’00001000’) + Displacement x’CB0’ THERE’S NO WAY in a single instruction (and, by extension, in a program range) to use only 1 base register addressing fields with addresses far from each other longer than x’FFF’.
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Summary: At the same time, one can use a maximum of 15 base registers (remember that the contents of register zero is not considered when computing an address).
This means that the biggest program size addressable simultaneously is (4K * 15) = 60K
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Summary: Using (almost) all registers as base registers: YOU WILL HAVE PRACTICALLY NO WORK REGISTER (only R0) !
Be careful!
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IBM Mainframes Architecture
Mainframes IBM : endereçamento
WOW !
What if the program is bigger (than 20K)?
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
One (there are lots of them) alternative:
Think about what general registers you’ll use as base registers in your program. For example: R3, R4, R5, R6 and R7 They are 5 registers. This is enough to address (5 x 4K) = up to 20K In a 20K “piece” of the program, you (must) set the registers up with the right contents, and use only things (areas and instructions) belonging to this piece.
In another 20K piece, set the registers up with the other contents and use only things of the new piece. And so on...
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing 60K storage 0K 4K 8K Program 12K 16K 20K 24K 28K 32K 36K 40K 44K 48K 52K 56K R3 = x’00000000’ R4 = x’00001000’ R5 = x’00002000’ R6 = x’00003000’ R7 = x’00004000’ R3 = x’00005000’ R4 = x’00006000’ R5 = x’00007000’ R6 = x’00008000’ R7 = x’00009000’ R3 = x’0000A000’ R4 = x’0000B000’ R5 = x’0000C000’ R6 = x’0000D000’ R7 = x’0000E000’
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IBM Mainframes Architecture
Register usage: idea, hints
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IBM Mainframes Architecture
Register usage: idea, hints Reg Use
0 1 2
Avoid using; used by the access methods and operating system routines Avoid using; used by the access methods and operating system routines; used by TRT and EDMK instructions.
Avoid using; use for work; used by TRT instruction Use as base register
3 4 5
Use as base register Use as base register
6 7
Use as base register Use as base register Alberto Romano Schiesari – www.profars.com
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IBM Mainframes Architecture
Register usage: idea, hints Reg
8 9 10 11 12 13 14 15
Use Use as work register Use as work register Use as work register Use as work register Use as work register Avoid using; used as save area by the interface routines between softwares Avoid using; used to save the return address when calling a routine by the caller Avoid using; used as initial base register for called routines, mainly in the access methods Alberto Romano Schiesari – www.profars.com
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Data format
Data format
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Data format
Data format
Alphanumeric data EBCDIC standard
Numeric data Fixed point binary (arithmetic operations : registers or storage) Floating point binary (arithmetic operations : registers or storage) Packed decimal (arithmetic operations : storage) Zoned decimal (arithmetic operations : NOT ALLOWED) Alberto Romano Schiesari – www.profars.com
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Data format - Alphanumeric data
Alphanumeric Data EBCDIC standard Alberto Romano Schiesari – www.profars.com
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Data format - Alphanumeric data
1 byte each character example: to represent the word “ALBERTO”
A L B E C1 D3 C2 C5 1100 0001 1101 0011
Curiosity: in ASCII
1100 0010 1100 0101 A 41 0100 0001 L 4C 0100 1100 B 42 0100 0010 E 45 0100 0101 R D9 1101 1001 R 52 0101 0010 T E4 1110 0100 O D6 1101 0110 T 54 0101 0100 O 4F 0100 1111
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Data format - Alphanumeric data
1 byte each character example: to represent the word “Alberto”
A l b e C1 93 82 85 1100 0001 1001 0011
Curiosity: in ASCII
1000 0010 1000 0101 A 41 0100 0001 1 6C 0110 1100 b 62 0110 0010 e 65 0110 0101 r 99 1001 1001 r 72 0111 0010 t A4 1010 0100 o 96 1001 0110 t 74 0111 0100 o 6F 0110 1111
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Data format - Numeric data
Numeric data Formats: - Zoned decimal or - Packed decimal or - Fixed point binary or - Floating point binary
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Data format - Numeric data
ZONED DECIMAL 1 byte each algarism, up to 16 bytes = up to 16 algarisms Each byte : left half = x’F’ right half = algarism Rightmost byte : left half = sign positive number or zero : x’F’ or x’C’ negative number : x’D’ IMPORTANT !!!
1
With this format, it’s NOT allowed to do arithmetic operations, it’s just to receive data (e.g. terminal data entry) or to format output data (e.g. terminal, printer).
2
Numbers: only INTEGERS.
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68
Data format - Numeric data
ZONED DECIMAL
Number 123 : 3 bytes needed 1111 0001 F1 1111 0010 F2 F3 1111 0011 Number –123 : 3 bytes needed 1111 0001 F1 1111 0010 F2 D3 1101 0011 Atention !!! : if printed (or seen), in character mode this configurations corresponds to the letter “L”
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F0
Data format - Numeric data
ZONED DECIMAL
Number 123 in a 5 bytes length field F0 F1 F2 F3 1111 0000 1111 0000 1111 0001 1111 0010 1111 0011 F0 Number -123 in a 5 bytes length field F0 F1 F2 D3 1111 0000 1111 0000 1111 0001 1111 0010 1101 0011 Atention !!! : if printed (or seen), in character mode this configurations corresponds to the letter “L”
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70
Data format - Numeric data
PACKED DECIMAL ½ byte each algarism, ½ byte for the sign Up to 8 bytes = up to 15 algarisms Rightmost byte : right half : sign positive number or zero : x’F’ or x’C’ negative number : x’D’ IMPORTANT !!!
1
In this format arithmetic operations are only allowed with storage fields (there is NO instructions to manipulate packed decimal data in registers) 2
Numbers: only INTEGERS.
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71
Data format - Numeric data
PACKED DECIMAL
02 0000 0010 Number
23
: 2 bytes needed 02 0000 0010 3F 0011 1111 3C 0011 1100 Number -
23
: 2 bytes needed 02 0000 0010 3D 0011 1101 Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters
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72
Data format - Numeric data
PACKED DECIMAL
12 0001 0010 Number
123
: 2 bytes needed 12 0001 0010 3F 0011 1111 3C 0011 1100 Number
-123
: 2 bytes needed 12 0001 0010 3D 0011 1101 Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters
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00
Data format - Numeric data
PACKED DECIMAL
Number 123 in a 5 bytes length field 00 00 12 3C 0000 0000 0000 0000 0000 0000 0001 0010 0011 1100 00 Number -123 in a 5 bytes length field 00 00 12 3D 0000 0000 0000 0000 0000 0000 0001 0010 0011 1101 Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters
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Data format - Numeric data
FIXED POINT BINARY Only fixed length fields: 2 bytes (1 bit for sign + 15 bits for the number) or 4 bytes (1 bit for sign + 31 bits for the number) or 8 bytes (1 bit for sign + 63 bits for the number) The quantity of algarisms (in the equivalent decimal numbers) depends on the number being represented (see next slide table) Leftmost bit = sign positive number or zero : 0 ; negative number : 1 BUT...
If positive, it’s the number’s representation If negative, the contents is the complement to the next 2 power IMPORTANT !!!
1
In this format arithmetic operations are only allowed with data in registers or in registers and storage fields (there is NO instructions to manipulate fixed point binary numbers only in storage; one of the operands must be in register) 2
Numbers: only INTEGERS.
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Data format - Numeric data
FIXED POINT BINARY Bytes Magnitude Sample use Numbers that may be represented 2 4 8 Thousands (32K) (US Bilions) (2G) (US Quintillions) (9Exa) Person’s age, line counter Employee salary, Part code, Customer code Company revenues, World population, astronomical distances From –32,768 to 32,767 From –2,147,483,648 to 2,147,483,647 From –9,223,372,036,854,775,808 to 9,223,372,036,854,775,807
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76
Data format - Numeric data
FIXED POINT BINARY Why complement?
+123 in binary = 1111011 –123 in binary = ...1111111111111111111111110000101
Subtracting 1 step by step... See (0 – 1) subtraction 000000100 - 000000001 ---------- 000000011 000000001 - 000000001 ---------- 000000000 111111110 - 000000001 ---------- 111111101
4 - 1 ---- 3 1 - 1 ---- 0 -2 - 1 ---- -3
000000011 - 000000001 ---------- 000000010 000000000 - 000000001 ---------- 111111111
Etc...
3
-1
---- 2 0 - 1 ---- -1 Etc...
000000010 - 000000001 -------- 000000001 -
2
1
---- 1
111111111 - 000000001 ---------- 111111110
-1 - 1 ---- -2
110000110 - 000000001 ---------- 110000101
-122 - 1 ---- -123
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77
Data format - Numeric data
FIXED POINT BINARY How to convert a decimal negative number to binary?
Convert the correspondent positive number to binary (consider only the significant digits)
Invert them: 1 becomes 0 and 0 becomes 1
Add 1
Fill to the left with 1’s to complete a half-word, a full-word or a double-word Example: let’s suppose decimal –123; +123 is 1111011
Convert the correspondent positive number to binary Invert them: 1 becomes 0 and 0 becomes 1
1111011 0000100
Add 1 0000100 + 1
------ 0000101
Fill to the left with 1’s to complete a half-word, a full-word or a double-word 1111111110 1111.1111.1111.1111 1111.1111.10
000101 F F 8 00.0101 F F 8 5 1111.1111.1111.1111.1111.1111.
1111.1111.1111.1111 1111.1111.10
00.0101 F F F F F F F F F F F F 8 5
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Data format - Numeric data
FIXED POINT BINARY How to convert a binary negative number to decimal?
Subtract it from X’....FFFFFF’ (the 1st X’...F’ number greater than the number to be converted)
Add 1; result is the POSITIVE desired number. Convert it to negative Example: let’s suppose X’FFE8’
Subtract FFFF - FF85
--- 007A
Add 1 007A 1
--- 007B
X’7B’ is the hexadecimal equivalent to decimal 123.
Desired number is decimal -123 Alberto Romano Schiesari – www.profars.com
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Number
123
Data format - Numeric data
FIXED POINT BINARY
In a half-word
0
0000000 01111011 X’007B’ In a full-word
0
0000000 00000000 00000000 01111011 X’0000007B’ In a double-word
0
0000000 00000000 00000000 00000000 00000000 00000000 00000000 01111011 X’000000000000007B’
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80
Number -
123
Data format - Numeric data
FIXED POINT BINARY
In a half-word In a full-word
1
1111111 10000101 X’FF85’
1
1111111 11111111 11111111 10000101 X’FFFFFF85’ In a double-word
1
1111111 11111111 11111111 11111111 11111111 11111111 11111111 10000101
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81
Data format - Numeric data
FLOATING POINT BINARY
Sorry... It isn’t in the scope of this course
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82
Instruction format
INSTRUCTION FORMAT
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Instruction formats
Instructions : main formats
RR = 2 bytes
RX = 4 bytes RS = 4 bytes SI = 4 bytes
SS = 6 bytes 2 bytes : operation codes between x’00’ and x’3F’ (b’0000 0000’ a b‘0011 1111’) 4 bytes : operation codes between x’40’ and x’BF’ (b’0100 0000’ a b‘1011 1111’’) 6 bytes : operation codes between x’C0’ and x’FF’ (b’1100 0000’ a b‘1111 1111’)
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Instruction formats
Instructions : main formats
RR – generally 2 operands, both in general registers
RX – 2 operands: 1 general register 1 storage field : address specification : Index + [ Base + Displacement ]
RS – 3 operands, 2 registers and 1 storage field 2 registers (they may indicate a range) 1 storage field : address specification: [ Base + Displacement ]
SI – 2 operands, both in storage 1 immediate storage (only 1 byte, within the instruction; no need to address it) 1 storage field : address specification : [ Base + Displacement ]
SS – 2 operands, both storage fields Both addresses specified as [ Base + Displacement ] Alberto Romano Schiesari – www.profars.com
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Instruction formats
Instructions : main formats
RR – (normally) 2 operands, both registers
Operation code
1st. Operand register x 2nd. Operand register CO x R1 R2 x
0 5 E F
Operation code = X’05’ 1st operand register = X’E’ (register 14) 2nd operand register = X’F’ (register 15)
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Instruction formats
Instructions : main formats
RX – 2 operands: 1 of them: register The other one : storage (address specified via Index register + [ Base register + Displacement ]
Operation code
1st. Operand register x 2nd. Operand Index Register
2o. Operand Base + Displacement
CO x R1 X2 B2 D2 x D2 D2 x
4 5 E 0
x
3 C 2 8
Operation code = X’45’ ; 1st operand register = X’E’ (register 14) ; 2nd operand index register = X’0’ (register 0); 2nd operand base register = X’3’ (register 3); 2nd operand displacement = X’C28’
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Instruction formats
Instructions : main formats
RS – 3 operands, 2 of them are registers, the other one in storage (address specified via [ Base register + Displacement ] )
Operation code
1st. Operand Register 3rd. Operand Register
2o. Operand Base + Displacement
CO x R1 R3 B2 D2 x D2 D2 x
9 8 E C
x
D 0 0 0
Operation code = X’98’ ; 1st operand register = X’E’ (register 14) ; 3rd operand register = X’C’ (register 12); 2nd operand base register = X’D’ (register 13); 2nd operand displacement = X’000’
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Instruction formats
Instructions : main formats
SI – 2 operands, both in storage 1 of them is immediate operand = 1 single byte (it is the instruction 2nd byte) The other one in storage: address specified via [ Base register + Displacement ]
Operation code
Immediate Operand (2nd. Operand)
1st. Operand Base + Displacement
CO x I2 B1 D1 x D1 D1 x
9 2 5 C
x
5 6 D 2
Operation code = X’92’ ; 2nd operand (immediate operand) = X’5C’ ; 1st operand base register = X’5’ (register 5); 1st operand displacement = X’6D2’
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Instruction formats
Instructions : main formats
SS-L – 2 operands, both in storage; 1 length specified (valid for both operands). Both addresses are specified as [ Base register + Displacement ]
Operation code 1st and 2nd operands length - 1 1st. Operand Base + Displacement 2o. Operand Base + Displacement
CO L x B1 D1 D1 D1 x B2 D2 D2 D2
D 2 4 F
x
3 B 9 4
x
6 F 2 A
Operation code = X’D2’ ; Both operands length = X’4F’ (80 bytes); 1st operand base register = X’3’ (register 3); 1st operand displacement = X’B94’; 2nd operand base register = X’6’ (register 6); 2nd operand displacement = X’F2A’
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Instruction formats
Instructions : main formats
SS-L1/L2 – 2 operands, both of them in storage; 2 lengths specified (1 for each operand). Both addresses are specified as [ Base register + Displacement ]
Operation code 1st. Operand length - 1 2nd. Operand length - 1 1st. Operand Base + Displacement 2o. Operand Base + Displacement
CO L1 L2 x B1 D1 D1 D1 x B2 D2 D2 D2
F 8 4 0
x
3 7 7 E
x
4 D 6 2
Operation code = X’F8’ ; 1st operand length = X’4’ (5 bytes) ; 2nd operand length = X’0’ (1 byte); 1st operand base register = X’3’ (register 3); 1st operand displacement = X’77E’; 2nd operand base register = X’4’ (register 4); 2nd operand displacement = X’D62’
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Instruction formats
Exercise
See the result here ONLY after trying hard to solve it
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Assembler Language
ASSEMBLER LANGUAGE
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Assembly / linkedit / execution flow
SYSLIB
Macros/Copys
SYSIN
Source prog
LOADER SYSUT1
Work
IEV90 SYSPUNCH
Object prog
SYSGO
Object prog
SYSPRINT
List
Storage SYSIN
Control stmts
SYSLIN
Object prog
SYSUT1
Work
IEWL SYSPRINT
List
SYSLIB
Other inputs
LINKLIB
SYSLMOD
Executable
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Assembler program structure Assembler program structure
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Assembler program structure It can be this way...
Program I (Instructions) A (Areas) LOAD POINT = ENTRY POINT
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Or this way...
Program A (Areas) Assembler program structure I (Instructions) LOAD POINT
ENTRY POINT Alberto Romano Schiesari – www.profars.com
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This way too...
Program I A I Assembler program structure A I A I LOAD POINT = ENTRY POINT
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Assembler program structure Even like this ...
Program I A I A I A I A I A I A I A I LOAD POINT = ENTRY POINT
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Assembler program structure Or like this...
Program A I A I A I A I A I A I A I A ENTRY POINT LOAD POINT
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Assembler program structure Remember that a reentrant program may be like this...
P1 Program P1 instructions ( manipulating A1, and, concurrently or in parallel, manipulating A2, manipulating A3, etc... manipulating An) + A1 A2 A3 ....
An P1 is in fact:
P1 instructions
P1 areas (A1 or A2 or etc)
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Assembler program structure In fact, an Assembler program’ structure may be ...
Anyway !
If you do not branch (GO TO / Jump ) , CPU will try to “execute” areas as they were instructions...
It is the von Newman architecture...
See the blue stripe and the branch just before...
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Statement Assembler STATEMENT
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Statement Positon 1 : With an *, the whole statement is a comment Position 1 to 8 : Symbol Position 9 to 14 : Instruction Mnemonic Code Position 16 to 71: Operands and comments; continuation must begin from position 16 Position 72 : If filled with any character, indicates that this statement continues in the next one Positions 73 a 80: Identification & sequence 123456789012345678901234567890123456789012345678901234567890123456789012 * THIS WHOLE STATEMENT IS A COMMENT FILLING MVC PRAREA,=CL133‘ ' COMMENT = CLEARS PRAREA XI *+5,X’F0’ COMMENT = FORCE BRANCH BC 0,TOGGLE COMMENT = SOMETIMES NOP * SOMETIMES BRANCH HERE EQU * WMESSAGE DC C’AJK001A – FILE BEING OPENED HAS NO DD STATEMENT IN THE– JCL. WAKE UP AND INCLUDE IT!.’ Continuation HERE WE HAVE A COMMEN Symbol Instruction Operands & Comments
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Statement Start smelling Assembler way of life...
INIT TITLE ‘INITIALIZATION ROUTINE' SEGINIT DFHEIENT CODEREG=7,DATAREG=(10,11),EIBREG=9 B BEGIN SKIP CONSTANTS DC C‘HI! COPYRIGHT ARS 2001' DC CL17'***VERSION 1.0***' DC CL28'***LAST UPDATE 10/23/2001***' BEGIN EXEC CICS ADDRESS CWA(R13) L R12,DFHEICAP LOAD COMMAREA ADDRESS ST R13,TWSVCWA SAVE CWA ADDRESS LA R2,TWAREA LOAD R2 WITH TWAREA ADDRESS LA R3,JREND R3 = JREND ADDRESS SR R3,R2 COMPUTE LENGTH STH R3,TWLENGTH STORE LENGTH SPACE 2
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Statement “Smell” #2 (yellow = Instructions, blue = areas, white = commands to the assembler) ...
COPY COVER CWA DSECT USING *,R13 COPY CWAREA COPY TADSECT COMMAREA DSECT USING *,R12 COPY TWAREA DFHEISTG DSECT DFHEISTG DFHEIEND EJECT T131 TITLE ‘SAMPLE PROGRAM‘ SPACE 2 ENTRYPT DFHEIENT CODEREG=(7,9),DATAREG=(10,11),EIBREG=5 B BEGIN SKIP CONSTANTS DC C‘HI! COPYRIGHT ARS 2001' DC CL17'***VERSION 1.0***' DC CL28'***LAST UPDATE 10/23/2001***' BEGIN L R12,DFHEICAP L R8,TWSVTERM L R13,TWSVCWA
... back to program structure ...
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Statement “Smell” #3 (yellow = Instructions, blue = areas, white = commands to the assembler) ...
* ================================================================== * 00000360 * SEQUENCE OF INSTRUCTIONS TO BE EXECUTED * 00000370 * ================================================================== * 00000410 LA R2,TRLT 00000420 TRLTLOOK CLI 0(R2),X'FF' TABLE END ? 00000430 BE ERROR TRLT NOT IN TABLE 00000440 CLC TWDBL(6),0(R2) IS TRANSACTION CODE IN THE TABLE? 00000450 BE TRL0100 YES 00000460 SR R15,R15 CLEAR REGISTER 15 00000470 IC R15,40(R2) LOAD R15 WITH INPUT LENGTH 00000480 N R15,=F'127' ZERO LEFTMOST BIT OF REGISTER 15 00000490 AR R2,R15 POINT TO NEXT ITEM IN THE TABLE 00000500 B TRLTLOOK BACK TO THE SEARCH 00000510 TRL0100 MVC TWTRLT,0(R2) MOVE TRLT TO TWA 00000520 EXIT EXEC CICS RETURN RETURN 00000530 ERROR LA R2,25 WRONG CODE 00000540 OI TWSW,X'01' TURN ON CANCEL SWITCH 00000550 LA R3,7 R3 = MESSAGE LENGTH 00000560 LA R1,TWMSG R1 = MESSAGE WORKAREA ADDRESS 00000570 STC R2,0(R1) STORE SG NUMBER TO WORKAREA 00000580 B EXIT RETURN 00000590 LTORG 00000600
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Statement “Smell” #4 (yellow = Instructions, blue = areas, white = commands to the assembler) ...
* ================================================================== * 00000620 * MY MACROS USED TO DEFINE MY CONVERSION DATA * 00000630 * ================================================================== * 00000640 TRLT TRLT CODE=000301, X00001540 TIT=‘NORMAL CREDIT ', X00001550 MAPN='NOT', X00001560 PTCM=01, X00001570 SPEC=14, X00001580 MNEM=‘NCR' 00001590 TRLT CODE=000302, X00001600 TIT=‘NORMAL DEBIT ', X00001610 MAPN=‘YES', X00001620 PTCM=02, X00001630 SPEC=14, X00001640 MNEM=‘NDB' 00001650 END ENTRYPOI 00009330
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Assembly program Assembler elements
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Assembly program Element 1 = Location Counter
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Assembly program Location Counter There’s 1 for each Section (Control and Dummy)
-
It is a counter beggining at x’00000000’ and it is Incremented each time storage is allocated (e.g. by declaring areas or by
-
specifying instructions) Changed when explicitly demanded by the use of any Assembler command that affects it (e.g. ORG)
00000 34 BLOCO1 EQU * 000000 35 DS CL4096 001000 00000 36 ORG BLOCO1 000000 37 DS CL1024 000400 38 A DS CL16 000410 39 B DS CL16 40 * . . 000420 3400 41 DC S(A) 000422 3410 42 DC S(B) 000424 400040165000502C 43 DC S(C,D,E,F) 00042C 6000604270007058 44 DC S(G,H,I,J) 45 * . . 000434 D20F 3400 3410 00400 00410 46 MVC A,B 00043A D215 4000 4016 01000 01016 47 MVC C,D 000440 D22B 5000 502C 02000 0202C 48 MVC E,F 000446 D241 6000 6042 03000 03042 49 MVC G,H 00044C D257 7000 7058 04000 04058 50 MVC I,J
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Assembly program Element 2 = Output List (some of the things listed are also present in the object program)
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Assembly program External Symbol Dictionary : List of elements that must be treated by the Linkage Editor and Loader
EXTERNAL SYMBOL DICTIONARY SYMBOL TYPE ID ADDR LENGTH LD ID FLAGS PROGDEMO SD 0001 000000 000AF3 00 FORA ER 0002 Z LD 000844 0001 SUBROT ER 0003
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Assembly program Program List
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT 49 * VOU MUDAR PARA PRINT DATA 50 PRINT DATA 00003B C1D3C2C5D9E3D6 51 DC CL7'ALBERTO' 000042 C1D3C2C5D9E3D65C 52 DC CL8'ALBERTO*' 00004A C1D3C2C5D9E3C9D5 53 DC CL10'ALBERTINHO' 000052 C8D6 54 * VOU RESTAURAR O DEFAULT 55 PRINT NODATA 000054 C1D3C2C5D9E3D6 56 DC CL7'ALBERTO' 00005B C1D3C2C5D9E3D65C 57 DC CL8'ALBERTO*' 000063 C1D3C2C5D9E3C9D5 58 DC CL10'ALBERTINHO' 59 *---------------------------------- 60 * PRINT ON/OFF
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Assembly program Relocation Dictionary : more work to the Linkage Editor and Loader
RELOCATION DICTIONARY POS.ID REL.ID FLAGS ADDRESS 0001 0001 0C 000070 0001 0001 08 0001B9 0001 0001 0C 000860 0001 0001 0C 000864 0001 0001 0C 000868 0001 0001 0C 00086C 0001 0001 0C 000874 0001 0001 0C 0008A4 0001 0001 0C 0008A8 0001 0001 04 000A46
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Assembly program Cross Reference / Symbol Table It is being built each time a statement with its own symbol is encountered.
Symbols (labels)
CROSS REFERENCE SYMBOL LEN VALUE DEFN REFERENCES AAALIN 00001 000A68 0272 0297 ANO 00002 000AE6 0319 ARIMP 00133 0001C0 0130 0129 A1 00004 000848 0220 0229 A11 00001 000878 0231 0231 A12 00001 000879 0232 0232 A13 00001 000881 0233 0233 A2 00004 00084C 0221 0230 A3 00004 000854 0222 A4 00004 000858 0223 A5 00004 00085C 0224 0225 0226 0227 0261 0262 0263 BYTE ****UNDEFINED**** 0285 BYTEON 00001 000000FF 0085 CAMPO 00001 00008A 0091 0092 CAMPO 00001 00000000 0321 ****DUPLICATE**** COCIENTE 00012 00000074 0082 0256 DATA 00006 000AE2 0316 .
Addresses
.
Length attribute
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Assembly program Remember forever and ever:
If you use a symbol that will be converted to a BASE + DISPLACEMENT address and the conversion isn’t possible (the assembler is not able to do it):
ADDRESSABILITY ERROR = There is no base register to “serve” this address.
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Assembly program Diagnostics
DIAGNOSTIC CROSS REFERENCE AND ASSEMBLER S THE FOLLOWING STATEMENTS WERE FLAGGED 000028 000119 000120 000122 000123 000125 000134 000142 000149 000156 000 000205 000212 000256 000261 000262 000263 000264 000265 000266 000267 000 30 STATEMENTS FLAGGED IN THIS ASSEMBLY 12 WAS HIGHEST SEVERITY CO OVERRIDING PARAMETERS LINECOUNT(50),XREF(FULL) OPTIONS FOR THIS ASSEMBLY DECK, NOOBJECT, LIST, XREF(FULL), NORENT, NOTEST, NOBATCH, ALIGN, ESD, R FLAG(0), SYSPARM() NO OVERRIDING DD NAMES 312 CARDS FROM SYSIN 216 CARDS FROM SYSLIB 572 LINES OUTPUT 73 CARDS OUTPUT
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Assembly program Element 3 = Expressions
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Assembly program EXPRESSIONS
Set of terms with a value and maybe will be used as an address.
If it’s an address, it may be converted to base + displacement format.
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Assembly program EXPRESSIONS May contain:
- Symbols - Self-defining terms
(decimal, binary, character or hexadecimal)
-
- Length attributes Location Counter reference
-
Arithmetic operators ( + - * / )
-
Paired parenthesis
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Assembly program EXPRESSIONS Examples Expression The resulting value corresponds to the LPOUP leftmost byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP is x’000A000C’)
This expression : only 1 term: a symbol [LPOUP]
LPOUP+0 leftmost byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+0 is x’000A000C’)
This expression : 2 terms: 1 symbol [LPOUP] and 1 decimal self-defining term [0]
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the LPOUP+3 4th byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+3 is x’000A000F’)
This expression : 2 terms: 1 symbol [LPOUP] and 1 decimal self-defining term [3]
LPOUP+15 16th. byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+15 is x’000A001B’)
This expression : 2 terms: 1 symbol [LPOUP] and 1 decimal self-defining term [15]
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the LPOUP+B’1111’ 16th. byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+B’1111’’ is x’000A001B’)
This expression : 2 terms: 1 symbol [LPOUP] and 1 binary self defining term [B’1111’]
LPOUP+C’F’ 199th. byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+C’F’’ is x’000A00D2’)
This expression : 2 terms: 1 symbol [LPOUP] and 1 character self defining term [C’F’] Note that C’F’ = X’C6’ X’000A000C’ + X’C6’ = X’000A00D2’
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the WAREA+50+X’100’+B’1100’+C’ ’ 383th. byte de WAREA (Suppose WAREA address= x’000A000C’; the value of expression WAREA+50+X’100’+B’1100’+C’ ‘ is x’000A018A’)
This expression : 5 terms: 1 symbol [WAREA] 1 decimal self-defining term [50] 1 hexadecimal self defining term [X’100’] 1 binary self defining term [B’1100’] 1 character self defining term [C’ ‘] Note that : Decimal 50 = X’32’; B’1100’ = X’C’ ; C’ ‘ (space) = X’40’ X’32’ + X’100’ + X’C’ + X’40‘ = X’17E’ = decimal 382 X’000A000C’ + X’32’ + X’100’ + X’C’ + X’40’ = X’000A018A’
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the WAREA+L’WAREA 1st byte after (whole) WAREA
This expression : 2 terms: 1 symbol (WAREA) and 1 length attribute [L’WAREA]
WAREA+1 1st byte after the beginning of WAREA (2nd byte of WAREA)
This expression : 2 terms: 1 symbol (WAREA) and 1 decimal self-defining term [1]
WAREA+L’WAREA-1 last byte of (whole) WAREA
This expression : 3 terms: 1 symbol (WAREA) and 1 length attribute [L’WAREA] 1 decimal self-defining term [1]
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the WAREA+L’FIXDLEN+1000
This expression : 3 terms: 1 symbol (WAREA) + 1 length attribute [L’FIXDLEN] + 1 decimal self-defining term [1000]
Suppose WAREA is composed by an area named FIXDLEN +
an area with 1000 bytes The value of this expression WAREA+L’FIXDLEN+1000 corresponds to the first byte after whole WAREA (WAREA + FIXDLEN length + 1000)
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the L’WATERM1+L’WATERM2+L’WATERM3
This expression : 3 terms: 3 length attributes [L’WATERM1, L’WATERM2, L’WATERM3]
length of WATERM1 area + length of WATERM2 area + length of WATERM3 area Suppose length of WATERM1 is 1000 bytes, length of WATERM2 is 2000 bytes, length of WATERM3 is 3000 bytes (Total length is 6000 bytes [decimal]) The value of the expression L’WATERM1+ L’WATERM2+ L’WATERM3 is X’1770’
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Assembly program EXPRESSIONS Expression The resulting value corresponds to the *+1 address in the location counter + 1
This expression : 2 terms: 1 Location Counter reference (*) + 1 decimal self-defining term [1]
*+L’WAREA address in the location counter + x bytes (x = WAREA length)
This expression : 2 terms: 1 Location Counter reference (*) + 1 length attribute [L’WAREA]
L’COMM+L’REGTYP1 COMM length + REGTYP1 length
This expression : 2 terms: 2 length attributes [L’COMM, L’REGTYP1]
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Assembly program Element 4 = Explicit and Implicit Operand reference
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Assembly program Explicit and implicit operand reference Registers: allways referenced explicitly AR 1,6 LR R5,R14 LR 5,14 LR R5,14 Syntax OK if there is R5 EQU 5 , but... * Don’t do that! Why reg 5 with symbol * and reg 15 don’t?
LR 5,R14 Syntax OK if there is R14 EQU 14 , but...
* Don’t do that! Why reg 14 with symbol * and reg 5 don’t?
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced RX instructions : Explicit reference: op reg1st,disp2nd(index2nd,base2nd) L 14,12(13) L R14,12(R13) IF EQUATES PROVIDED ST 7,96(8) ST 7,96(R8) IF R8 EQU 8 PROVIDED Implicit reference: op reg1st,expression
(assumed index register = 0)
or op reg1st,expression(index2nd) L 14,SAVE14 L 14,SAVEAREA+12 ST 7,WSAVEA(7) ST 7,WSAVAREA+(7*4)
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced RS Instructions : Explicit reference : op reg1st,reg3rd,disp2nd(base2nd) LM 14,12,12(13) STM 7,11,0(R12) Implicit reference : op reg1st,expression LM 14,12,SAVEAREA+12 STM 14,12,THERE
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SI Instructions : Explicit reference : op disp1st(base1st),immed2nd MVI 10(R12),C’*’ XI 0(15),X’FF’ OI 15(R8),X’80’ Implicit reference : op expression1st,immed2nd MVI FLAGS+77,C’*’ XI TOGGLE,X’FF’ OI PRINTED,X’80’
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L Instructions : Implicit reference : op expression1st,expression2nd
(assumed length = length of 1st operand)
MVC ARIMP+77,C’*’ T-A-K-E C-A-R-E!!!
* I THINK THIS IS NOT YOU WANNA DO !!!
MVC ARIMP+77,=C’*’ * I THIS THIS IS NOT ALSO ... !!!
MVC ARIMP+77(1),=C’*’ * WOW ! PROBABLY IT’S THE RIGHT OPTION !!!
CLC AGENTCOD,CODWANT
(length implicit = length of AGENTCOD)
CLC IVSAM(3),CODWANT CLC IVSAM+68(3),CODWANT CLC IVSAM+68,CODWANT
(length = 3 = explicitly indicated) (length = 3 = explicitly indicated) (length implicit = length of IVSAM)
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L Instructions : Explicit reference : op disp1st(lengthboth,base1st), disp2nd(base2nd) MVC 0(18,7),=C’ERROR’ CLC AGENTCOD,25(14) CLC AGENTCOD+33,25(14) CLC AGENTCOD+33(2),25(14) CLC 3(22,8),7(15)
(length = 18 = explicitly indicated) (length assumed = length of AGENTCOD) (length assumed = length of AGENTCOD) (length = 2= explicitly indicated) (length = 22 = explicitly indicated)
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L1-L2 Instructions : Implicit reference : op expression1st,expression2nd
(1st operand assumed length = length of 1st operand; 2nd operand assumed length = length of 2nd operand)
AP COUNTLIN,=P’1’ ZAP TOTVAL,=P’0’ AP BIGTOT,SUBTOT MP WNUM,=P’12’ MP WNUM+44(3),=P’12’
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Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L1-L2 Instructions : Explicit reference : op disp1st(length1st,base1st), disp2nd(length2nd,base2nd) AP 0(4,3),=P’1’ ZAP 17(16,12),=P’0’ AP BIGTOT,127(2,5) MP WNUM+44(8),222(3,R6)
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Assembly program Statement types - Assembler commands - Machine instructions - Macro-instructions
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Assembly program Assembler commands - Area definition:
,
- Program sectioning and linking :
,
,
,
, - Base register control:
-Listing control:
, ,
,
- Misc control:
,
,
,
,
,
- Macro instruction definition: AREAD, MACRO, MEXIT, MEND
- Conditional assembly (normally used to do macro instructions):
ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, MNOTE, SETA, SETB, SETC
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Assembly program (Some) Machine instructions
-
Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCI - Register to Storage move : ST, STH, STM, STC, STCM, CVD - Storage to Register move : L, LH, LM, IC, ICM, CVB
-
Register to Register move : LR, LPR, LNR, LCR, LTR - Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP - Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR
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Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL - Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR - Branch : BC, BCR - Loop Control : BCT, BCTR, BXH, BXLE - Edition : ED, EDMK - Byte Translation and test: TR, TRT - Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA - Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC - Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM - Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS
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Assembly program Macro-instructions Installation’s e.g. ASCEBC, etc...
IBM’s (from operating system, access methods) DCB (to declare datasets) OPEN, CLOSE, GET, PUT, READ, WRITE GETMAIN, FREEMAIN, ATTACH, DETACH etc...
IBM’s (specific for CICS, DB2, etc...) DFHMSD, DFHMDF, etc...
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Assembler commands Assembler commands
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Instructions to the assembler - commands Assembler commands (alfabetically)
These aren’t in the scope of this course): MNOTE, SETA, SETB, SETC AREAD, MACRO, MEXIT, MEND ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP,
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Instructions to the assembler - commands Assembler commands (by group)
-Source statement and listing control:
,
,
,
,
- Program sectioning and linking :
,
- Base register control:
,
,
- Direct Location Counter manipulation:
,
- Use of external objects or external use of internal objects: ,
,
,
,
,
,
- Declare literals:
- Area definition:
,
- Macro instruction definition: AREAD, MACRO, MEXIT, MEND
- Conditional assembly (normally used to do macro instructions):
ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, MNOTE, SETA, SETB, SETC
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Assembler commands - AMODE
AMODE (Adressing Mode) This command is used to indicate to the assembler the addressing mode associated to a Control Section.
[symbol] AMODE n
n
may be 24 or 31 or ANY.
Symbol is optional.
If omitted, the addressing mode will be associated to the blank (no name) Control Section that must exist in the program.
If specified, the addressing mode will be associated to the Contro,l Section with the same name as indicated in the symbol.
The operand indicates the addressing mode that must be associated with the Control Section. One must specify 24 (24 bit addressing), 31 (31-bit addressing) or ANY (the Control Section isn’t sensitive to the addressing mode).
There must be only one AMODE for each Control Section. The AMODE command may be specified at any point in the program. AMODE 24 is not compatible with RMODE ANY.
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Assembler commands - AMODE AMODE (Adressing Mode) If only AMODE or RMODE is specified (or even none of them) the defaults are: Specified Assumed None AMODE 24 and RMODE 24 AMODE 24 RMODE 24 AMODE 31 RMODE 24 AMODE ANY RMODE 24 RMODE 24 AMODE 24 RMODE ANY AMODE 31
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Assembler commands – CCW / CCW0 / CCW1 CCW / CCW0 / CCW1 (Channel Command Word) Sorry. It’s not in the scope of this course.
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Assembler commands - CNOP CNOP (Conditional Nop) CNOP command aligns the Location Counter to a Half-word boundary.
The skipped bytes are filled with X'0700' (NOPR instruction). Syntax: CNOP a,b Where: a - 0, 2, 4 or 6. Indicates to what byte positition in a Full-Word or Double-Word the Location Counter must be advanced.
b - 4 (full-word) or 8 (double-word).
Example: CNOP 2,4
• •
0,8 0,4
• •
2,8 2,4
• •
4,8 0,4
• •
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Assembler commands - COM COM (Blank Common Control Section) This command identifies and allocates a commom storage area. It can be referred to by independent modules linkedited and loaded as a unique program.
No symbols nor operands are allowed.
Only one COM is allowed in each program, although many COM commands may be issued, the first one indicating the COM beginning, and the others indicating the continuation(s). Sintax: COM Example: CSPRG 0 A B START .
.
COM DS DS .
.
END CL3 CL4
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Assembler commands - COPY COPY COPY command copies source statements from a source library. Syntax: COPY symbol The symbol refers to the name of the library member to be copied.
Among the copied commands, the commands ICTL or ISEQ are not allowerd. Example: COPY EQUREG
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Assembler commands - CSECT CSECT (Control Section) CSECT command identifies the beginning or the continuation of a Control Section.
[symbol] CSECT CSECT command have no operands. If symbol is specified, it names the CSECT. Commands and instructions specified after CSECT command will be part of it, up to another CSECT or DSECT command.
Many CSECT commands with the same symbol may appear in a program. The first one names the CSECT (and is the range of its first “piece”). The others identify their continuations (the other “pieces”).
To “interrupt” a DSECT, use another DSECT command or a CSECT command.
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Assembler commands - CSECT CSECT (Control Section) PROG1 CSECT .
.
.
END Is the same as PROG1 START .
.
.
END (In both cases) there is a Location Counter (for PROG1 section).
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Assembler commands - CSECT CSECT (Control Section) PROG1A START .
.
PROG1B CSECT .
.
PROG1B CSECT .
.
END There is a Location Counter for PROG1A section, another for PROG1B section, and a 3rd to PROG1C section.
Is the same as PROG1A CSECT .
.
PROG1B CSECT .
.
PROG1B CSECT .
.
END There is a Location Counter for PROG1A section, another for PROG1B section, and a 3rd to PROG1C section.
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Assembler commands - CSECT CSECT (Control Section) A CSECT CSECT A = 1 + 4 . 1 CSECT B = 2 . CSECT C = 3 + 5 B CSECT . 2 .
C CSECT . 3 .
A CSECT . 4 . C CSECT . 5 END There is a Location Counter for A section, another for B section, and a 3rd for C section.
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Assembler commands - CSECT CSECT (Control Section) CSECTs of last slide is the same as this set of CSECTs: A START CSECT A = 1 + 4 . 1 CSECT B = 2 . CSECT C = 3 + 5 B CSECT . 2 .
C CSECT . 3 .
A CSECT . 4 . C CSECT . 5 END There is a Location Counter for A section, another for B section, and a 3rd for C section.
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CXD (Control Section)
Assembler commands - CXD
CXD command defines a Full-Word. Linkage Editor (ou o Loader) will put in this full-word the length of all external DSECTs specified in the source programs (being linkedited or loaded) using this DSECTs. Syntax: symbol CXD No operands are allowed. Example: TOTALLEN CXD
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DC (Define Constant) Assembler commands - DC
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Assembler commands - DROP DROP (Por de lado, Deixar) DROP command indicates to the assembler that one (or more) register(s) previously assigned as base registers (via USING command) is (are) no longer base register(s) (teh assembler must drop them from the base register table). Syntax is: DROP [R1[,R2,R3 ..........R16]] Where R1 .........R16 is the list of registers not to be used as base registers anymore. Example: DROP 3,8 If no operand is specified, all base registers will be unassigned.
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Assembler commands - DS DS (Define Storage)
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Assembler commands - DSECT DSECT (Dummy Section) DSECT command defines a section used to do address convertions to Base+Shift format; it doesn’t allocate areas, it’s just used by the assembler to build the symbol table and determine the displacements of the fields it contains. It’s often used to describe an area ‘ structure., without phisically allocating storage for it. Syntax is: symbol DSECT DSECT command have no operands. The symbol names the DSECT.
Many DSECT commands with the same symbol may appear in a program. The first one names the DSECT (and is the range of its first “piece”). The others identify their continuations (the other “pieces”).
To “interrupt” a DSECT, use another DSECT command or a CSECT command.
Example:
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Assembler commands - DSECT DSECT (Dummy Section) CSN1 START C DS .
.
DSN1 DSECT A DS CL2 B DS CL20 D DS CL10 CSN1 CSECT .
.
END To use the DSECT fields as instruction’s operands, it’s the programmer’s responsibility to set the base(s) register(s) up with the correct value(s), and, at codeing time, provide the assembler with the information about what is the base register(s) for the DSECT (USING command).
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Assembler commands - DXD DXD (Define Dummy External) DXD command defines an external DSECT. Syntax: symbol DXD operand Symbol must be referenced as operand ina Q-type constant. It is the external DSECT’ first byte address, and its length attribute is 1.
The operand has the same syntax as in the DS command. Assembler computes the amount of storage and the alignment required by the external DSECT, based on the area specified as operand. Example: CONST DXD 5F .
.
DISPLAC DC Q(CONST)
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Assembler commands - EJECT EJECT EJECT command causes a page skip in the sorce listing. No operands allowed.
EJECT
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Assembler commands - END END END command must be the last source statement. Syntax: END [Symbol] If symbol is omitted, the first byte of the program is assumed as the ENTRY POINT.
If symbol is specified, the ENTRY POINT is the address indicated by te expression specified as ioperand.
END INICIO
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Assembler commands - ENTRY ENTRY This command identifies the symbols defined in the program, abd used externally (in another program). Syntax: ENTRY symbol[,symbol...] In the external program that uses the symbol, it must be defined with an EXTRN command.
* ROUTINE IS DEFINED HERE IN PROG1 PROG1 START 0 . . * ROUTINE IS REFERENCED HERE IN PROG2 PROG2 START 0 ROUTINE EQU * . . ENTRY ROUTINE END . . . . EXTRN ROUTINE END
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Assembler commands - EQU EQU (Equate - Igualar) EQU command associates an expression (value / address) to a symbol, adding them (symbol + value) to the symbol table. Syntax: Symbol EQU a Symbol EQU a,b Symbol EQU a,b,c Symbol EQU a,,c Where: a – expression whose value must be associated to the symbol.
b – auto-defined term indicating the length attibute desired to be associated to the symbol..
If b is omitted, the length of the first (or only) term of the expression is assumed to be the length attribute of the symbol: --- If it is a Location Counter reference (*), an auto-defined term or a length attribute reference (L’x), 1 is assumed. --- If it is a symbol used in a DC or DS, it’s assumed the symbol’s length attribute. --- If it’s a symbol used in a machine instruction, the length of the instruction is assumed as length attribute (2,4 or 6 Bytes) --- If it’s a symbol used in a assembler command (except DC, DS and CCW), 1 is assumed. c – auto-defined term indicatiing the type attribute desired to be associated to the symbol. If omitted, U assumed.
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Assembler commands - EQU EQU (Equate - Igualar) Examples: R5 EQU 5 ...
LA R5,TABLE Normally one uses to equate the registers numbers (addresses) to a symbol (e.g. R0 up to R15 to the general registers, and FP0 etc to the floating point registers), to “force” the references to them to be listed in the cross-reference produced by the assembler.
INST EQU * LA R13,SAVEAREA Is often used rather than INST LA R13,SAVEAREA Note that the address will probably be the same: the location counter has the same value in both cases, unless in the first case there’s an area definition with odd nymber of bytes.
The choice for the use of QUE is just for “elegance purposes”.
Note that with the EQU the length attribute for INST symbol is 1, and using the symbol in the LA instruction the length attribute is 4 (LA instruction length).
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Assembler commands - EQU EQU (Equate - Igualar) Examples: OFF EQU X'00' ON EQU X'FF' PAID EQU X'80‘ This type of use is common also due to the listing of symbols in the cross-reference. If one uses the symbols rather than the values in instructions that need a mask, it’s easier to find (via cross-reference) which are the instructions manipulating the masks; if the auto defined terms are used, no references are listed in the cross-reference.
Rather than NI FLAGUSED,OFF RESET USE FLAG OI FLAGERR,ON SET ERROR FLAG TM FLAGPAY,PAID TEST PAYMENT NI FLAGUSED,X’00’ RESET USE FLAG OI FLAGERR,X’FF’ SET ERROR FLAG TM FLAGPAY,X’80’ TEST PAYMENT
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Assembler commands - EXTRN EXTRN (External - Externo) This command identifies the symbols referred to in the program, but defined externally (in another program).
EXTRN symbol[,symbol...] In the program that defines the symbol therre must be an ENTRY command for the symbol.
* ROUTINE IS DEFINED HERE IN PROG1 PROG1 START 0 . . * ROUTINE IS REFERENCED HERE IN PROG2 PROG2 START 0 ROUTINE EQU * . . ENTRY ROUTINE END . . . . EXTRN ROUTINE END
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Assembler commands - ICTL ICTL (Input Control) As seen in the assembler statements syntax: --- Symbol must begin at position 1 --- Last position is 71 --- Continuation (if exists) must begin at position 16 ICTL command, if used, must be the first statement in the source program (only 1 ICTL in the source program), and it’s used to change the structure above remembered. Syntax: ICTL ICTL ICTL a a,b a,b,c or or Where: a – specifies the 1st position of the symbols. May be from 1 up to 40.
b – specifies the last position of an instruction (from 41 up to 80); if omitted, 71 is assumed. It must be greater than or equal to a+1.
c –specifies the continuation position. It may be from 2 up to 40. If omitted or if 80 is specified assembler assumes that continuation is not allowed.
ICTL 4,70,71
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Assembler commands - ISEQ ISEQ (Input Sequence) Indicates to the assembler to validate the input sequence of the source statements.Syntax: ISEQ [a,b] Where: a – sequence field 1st position b - sequence field last position OBS:- a <= b Wow! It was used when the source statements were in cards, to assure that they weren’t messed!
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Assembler commands - LOCTR LOCTR (Multiple Location Counters) This command is used to specify multiple location counters to a Control Section. Syntax: symbol LOCTR The first location counter of a section is automatically defined when assembler gets each first START, CSECT, DSECT and COM, and it works as if the assembler gets the section name and uses it as the counter’s name .
Using the LOCTR command, one specifies another name, used to christen the 2nd location counter of the section, and so on.
If one specifies a name already used, the location counter use is resumed.
See the example following
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Assembler commands - LOCTR LOCTR (Multiple Location Counters) PROGRAM Active Loc.Counter
PGM1 CSECT PGM1 part 1 X AREA1 AREA2 PGM1 Y TAB1 TAB2 PGM1 X AREA11 AREA12 PGM1 .
.
.
LOCTR DS DS LOCTR .
.
.
LOCTR DS .
.
DS LOCTR .
LOCTR DC DC LOCTR LTORG END CL80 CL4 CL10000 CL20000 C'*' F'0' PGM1 part 1 PGM1 part 1 PGM1 part 1 X part 1 X X part 1 part 1 PGM1 part 2 PGM1 part 2 PGM1 part 2 PGM1 part 2 Y Y part 1 part 1 Y part 1 PGM1 part 3 PGM1 part 3 PGM1 part 3 PGM1 part 3 X part 2 X X part 2 part 2 PGM1 part 4 PGM1 part 4 Generated Object
CSECT PGM1 (with “ 7 parts ” )
PGM1 = (part 1 of loc counter PGM1) + (part 2 of loc counter PGM1) + (part 3 of loc counter PGM1) + (part 4 of loc counter PGM1) + (part 1 of loc counter X) (part 2 of loc counter X) (part 1 of loc counter Y) + +
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Assembler commands - LTORG LTORG LTORG command causes the declaration of all literals so far referenced.
Before definition, Location Counter is aligned to a boundary 8 address. Because of this characteristic, you’ll sometimes find 2 LTORGS one followed by another: the first to align and declare all literals, and the second one just to align the location counter. One could use , instead of the 2nd LTORG, a CNOP 0,8 or a DS 0D.
No symbol nor operands are allowed.
LTORG LTORG , DECLARING LITERALS LTORG , ALIGNMENT Note that to insert the coments, as no operands are allowed, one must insert the comma before the comments to indicate the operands absence.
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Assembler commands - LTORG LTORG 000476 0000 0000 0000 00000 00000 IEV044 *** ERROR *** 59 UNDEFINED SYMBOL 00047C D241 6000 B021 03000 00021 000482 D257 7000 B02C 04000 0002C 000488 D20A B037 B042 00037 00042 60 61 62 00048E 41C0 7FFF 000492 0000 0000 IEV034 *** ERROR *** 04FFF 63 * 64 00000 65 ADDRESSABILITY ERROR 000496 0000 0000 IEV034 *** ERROR *** 00000 ADDRESSABILITY ERROR 00049A 58C0 34A8 004A8 00049E D20F 3400 34AC 00400 004AC 66 67 68 0004A8 0004A8 00005000 0004AC 5C 69 * 70 71 72 73 * 0004AD 00 0004AE D20F 3400 40E4 00400 010E4 0004B4 0000 0000 IEV034 *** ERROR *** 0004B8 58C0 40E0 00000 75 ADDRESSABILITY ERROR 010E0 74 76 MVC MVC MVC MVC .
LA LA LA E,DSEKCOP3 G,DSEKCPO4 I,DSEKCPO5 DSEKCPO6,DSEKCPO7 .
12,Z-1 12,Z+1 12,Z L MVC 12,=A(Z) A,=C'*' .
.
LTORG , .
=A(Z) =C'*' .
MVC LA L A,=C'*' 12,Z 12,=A(Z)
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Assembler commands - OPSYN OPSYN (Operation Synonim) The OPSYN command establishes an equivalence between a symbol and an operation code of a machine instruction or an Assembler command. Syntax: Symbol OPSYN [code] Where: Symbol – any valid Assembler symbol or operation code (if the operand is omitted).
Code – any valid operation code. If omitted, the command unassigns the operation code previously assigned as symbol.
The OPSYN command must be inserted after ICTL (if ICTL is present) and can br preceded only by EJECT, ISEQ, PRINT, SPACE and TITLE. Example: MYMOVE MVC OPSYN OPSYN MVC
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Assembler commands - ORG ORG The ORG command alters the value of the Location Counter, setting it up with the value of the expression specified as operand. Syntax: symbol ORG [expression] If the operand is omitted the value set in the Location Counter is the highest it has reached. Example: Note: the symbols used as ORG operands must be defined before ORG command.
Loc.Counter Loc.Counter
Before After . . . . . . . . . 0AB84C 0AB94C 0AB94C 0AB93C 0AB93C 0AB946 0AB946 0AB94C TABNUM DC ORG DC ORG . . . 256X'FF' Location Counter reaches 0AB94C TABNUM+240 Return to 0AB93C 10X'00' Reaches 0AB946 Return to the highest so far: 0AB94C
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Assembler commands - POP POP The POP command restores the PRINT and/or USING status saved by PUSH command. Syntax: POP PRINT POP USING POP PRINT,USING POP USING,PRINT
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Assembler commands - PRINT PRINT The PRINT command is used to control the contents of the listing the assembler produces. Syntax: PRINT options The options must be specified separeated by commas, and they indicate to the assembler what must be printed or not. Valid options are: ON OFF GEN NOGEN DATA NODATA Listing is produced Listing not produced (at least until next PRINT ON) Macro-instruction-generated instructions must be listed.
Macro-instruction-generated instructions mustn’t be listed.
The contents of the defined areas must be listed.
The contents of the defined areas must have its first (or max) 8 bytes listed. PRINT OFF,DATA If no PRINT command is specified (or until it is specified) it is assumed PRINT ON,GEN,NODATA One can use as many PRINT commands as necessary / desired.
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Assembler commands - PUNCH PUNCH The PUNCH command indicates to the Assembler to write to the object file 1 record which value is the value specified as the PUNCH operand. Syntax: PUNCH a Where a is a string from 1 to 80 characters between apostrophes. If the character is an apostrophe (') or an ampersand (&), it must be twice specified. Example: PUNCH ' CATALR MOD' The result record is: pos pos pos pos pos 1-2 3-8 : : 9-10 : 11-13 : 14-80 : spaces CATALR spaces MOD spaces
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Assembler commands - PUSH PUSH The PUSH command saves the status of PRINT and USING. Syntax: PUSH PUSH PUSH PUSH PRINT USING PRINT,USING USING,PRINT
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Assembler commands - REPRO REPRO The REPRO command indicates to the Assembler to write to the object file 1 record which value is the value of the statement following the REPRO command. No symbol nor operands are allowed.
CATALR REPRO MOD At this point a record with “ CATALR MOD ” is written to the SYSPUNCH file.
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Assembler commands - RMODE RMODE (Residence Mode) This command is used to indicate to the assembler the residence mode associated to a Control Section.
[symbol] RMODE n n may be 24 or ANY.
Symbol is optional.
If omitted, the residence mode will be associated to the blank (no name) Control Section that must exist in the program.
If specified, the residence mode will be associated to the Contro,l Section with the same name as indicated in the symbol.
The operand indicates the residence mode that must be associated with the Control Section. One must specify 24 (24-bit residence = the CSECT must reside bellow the 16MB line), or ANY (24-bit or 31-bit residence = the CSECT may reside bellow or above the 16MB line).
There must be only one RMODE for each Control Section. The RMODE command may be specified at any point in the program. RMODE ANY is not compatible with AMODE 24.
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Assembler commands - RMODE RMODE (Residence Mode) If one specifies only AMODE or RMODE (or even none of them) the defaults are: Specified Assumed None AMODE 24 and RMODE 24 AMODE 24 RMODE 24 AMODE 31 RMODE 24 AMODE ANY RMODE 24 RMODE 24 AMODE 24 RMODE ANY AMODE 31
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Assembler commands - SPACE SPACE The SPACE command, when detected by the assembler, results in a skip of n lines in the SYSPRINT listing, where n is specified in the operand (if omitted, 1 is assumed).
SPACE [n] Example: SPACE 3
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Assembler commands - START START This command sets the initial value in the LOCATION COUNTER. It must be one of the first commands in the source program (it can’t have any instruction or command that alters the Location Counter before the START command). The syntax is: [symbol] START a where: Symbol: START command defines the first Control Section (CSECT) of the program. If the symbol is specified, it will be the section’s name. If not specified, the first control section is considered as no name. a = Auto-defined term = its value must be multiple of 8.Tit indicates the initial value of the Location Counter. If omitted, zero is assumed. PROG1 START X'308' START 10240 If START command is omitted, START 0 is assumed.
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Assembler commands - TITLE TITLE The TITLE command specifies the title of the listing produced by the Assembler. Syntax: [symbol] TITLE a Symbol --- in VSE : 1 to 4 characters (it will be used to fill positions 73 to 76 of the object program records).
a -- 1 to 100 characters string between apostrophes. If a character must be an apostrophe (') or an ampersand (&), it must be twice specified.
Example: P001 TITLE 'EMISSAO NOTAS FISCAIS' At each TITLE command a page skip is provided.
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Assembler commands - USING USING (Usando) The USING command is used to provide addressability to symbols, by indicating to the Assembler: a) The value of the 1st base register (1st operand) b) The base register(s) of the program (2nd operand, 3rd operand and so on) Syntax: USING a,1br[,2br,[3br] .......[16br]] Where a is an expression indicating to the Assembler the value the first base register [1br] is assumed to have when the program is running. If a second base register [2br] is specified, it is assumed to have a+4096 when program is running.
If a third base register [3br] is specified, it is assumed to have a+8192 when program is running. And so on.
USING *,3,8 In this example: registers 3 and 8 are the base registers.
Register 3 is assumed to have the value of the Location Counter when the program is running.
Register 8 is assumed to have the value of the Location Counter+4096 when the program is running.
Note that the USING command only warns the Assembler about the value at execution time; it DOES NOT LOAD the value. It’s the programmer’s responsibility to load the correct value (in the example corresponding to the values of the Location Counter and Location Counter+4096.
Normally one uses the BALR instruction to load the first base register and LA to load the other ones.
For DSECTs : specify the DSECT symbol as the first operand.
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Assembler commands - WXTRN WXTRN (Weak Extrn) This command is similar to the EXTRN command, but: - with the EXTRN command the Linkage Editor searches autoimatically the libraries to find the modules that contains the symbols specified as operands in teh EXTRN command(s).
- with the WXTRN command no auto search is provided. The references will be solved by the Linkage Editor only if the specified symbols are defined: -- in a module link-edited and loaded together with the program with the WXTRN command OR -- in a module linked from a library because it has an EXTRN command in another module (linkedited and loaded together with the program with WXTRN).
Syntax: WXTRN symbol[,symbol ....... ] Example: WXTRN MOD
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Assembler commands - Defining areas Defining Areas
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Assembler commands - Defining areas DC = Define Constant to define areas WITH contents (storage allocation, with contents, with a name [symbol], address [value], length attribute and type attribute) DS = Define Storage to define areas WITHOUT contents (storage allocation, with a name [symbol], address [value], length attribute and type attribute)
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Assembler commands - Defining areas What does exactly mean to allocate an area without contents (without an initial value)? (e.g. DS in Assembler, or a field declared without the VALUE clause in Cobol)
Executable Storage
???????????
LOADER ???????????
Instructions Areas with contents (DC) Areas without contents (DS)
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Assembler commands - Defining areas General syntax: Da = duplication attibute: how many areas to define Type = contents (value) type; it’s used to attribute the value and to establish the length attibute if La is not specified.
NO validation is done at assembly time.
La = Length attribute Ic = initial contents (value)
[name] DC
[Da] type [La]
Ic [name] DS
[Da] type [La
][Ic]
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Assembler commands - Defining areas Examples:
[name] DC
[Da] type [La]
Ic
SEPARAT1 DC 132 C L1 ’*’
Da=132;Type=C;La=L1;Ic=‘*’
* Declares 132 areas, 1 byte each (all 132 bytes with *)
SEPARAT2 DC C L132 ’*’
Da=omitted;Type=C;La=L132;Ic=‘*’
* Declares 1 area, length=132 bytes ( 1st byte has * all others with spaces )
CONTLIN DC P L2 ’99’
Da=omitted;Type=P;La=L2;Ci=‘99’
* Declares 1 area 2 bytes long (value=99 in packed decimal)
ADRSTAB DC A (TABAGE)
Da=omitted;Type=A;La=omitted;Ic=(TABAGE)
* Declares 1 área 4 bytes long (value = address of TABAGE)
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Assembler commands - Defining areas Examples:
[name] DS [Da]type[La][Ic]
SEPARAT1 DS 132CL1
Da=132;Type=C;La=L1;Ic=omitted
* Declares 132 areas, 1 byte each (NO INITIAL CONTENTS)
SEPARAT2 DS CL132
Da=omitido;Type=C;La=L132;Ic=omitted
* Declares 1 area, length=132 bytes (NO INITIAL CONTENTS)
CONTLIN DS PL2
Da=omitted;Type =P;La=L2 ;Ic=omitted
* Declares 1 area 2 bytes long (NO INITIAL CONTENTS)
ADRSTAB DS A
Da=omitted;Type =A;La=omitted ;Ic=omitted
* Declares 1 area 4 bytes long (NO INITIAL CONTENTS)
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Defining areas – DC (define constant)
DC - Define Constant Area WITH value (initial contents)
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Assembler commands - Defining areas - Summary Area types - summary Typ e C X B A Y S F H P Z D Length assumed enough enough enough 4 bytes 2 bytes enough enough 8 bytes 4 bytes 2 bytes 2 bytes Alignment byte byte byte FullWord HalfWord Byte Byte DoubWord FullWord HalfWord HalfWord Valid Length 1 to 256 1 to 256 1 to 256 1 to 8 1 to 8 1 to 16 1 to 16 1 to 8 1 to 4 1 to 2 2 Constants p/operand 1 multiple multiple multiple multiple multiple multiple multiple multiple multiple multiple Filled From-To L
R R
L R
L R
L R
L R
L R
L -x L
R L
R -x remarks:- (1) 0's if positive number; 1's if negative number (2) Up to 2**31 - 1 (3) Up to 2**15 - 1 (4) Decimal-point does not use any space (5) The sign uses 1/2 byte
Filled with spaces X’0’ B’0’ (1) (1) X’0’ C’0’ -x B’0’ B’0’ -x Truncat ed at Right Left Left Left Left Left Left -x Left Left -x Valid characters qualquer 0 to F 0 to 1 + - 0 to 9 + - 0 to 9 + - 0 to 9 + - 0 to 9 + - 0 to 9 expression expression expression Each char 1 byte ½ byte 1 bit (2) (4) (3) (4) ½ byte (5) 1 byte -x -x -x -x Alberto Romano Schiesari – www.profars.com
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Defining areas – Type C (character)
C-type DC (character) [name] DC [Da] C [La]Ic
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Defining areas – Type C (character) Each character occupies 1 bytes (EBCDIC format) If no length attribute specified: assumed (the default is) the enough to fit the initial contents.
If length attribute (La) specified: the La will be considered rather than the enough to fit the value.
If La specified is greater than the enough to fit the value, the remaining bytes to the right will be filled with spaces (X'40').
If the length attribute specified is less than the enough to fit the value specified, the rightmost characters of the value will be truncated (error will be flagged).
Se o tamanho for insuficiente, será feito truncamento à direita (e será indicado erro).
Maximum length = 256 bytes.
When the desired character in value is apostrophe (“’”) or ampersand (“&”) it is needed to specify it twice.
DC 1CL1'*' 5C DC 2CL1'*' 5C5C DC CL1'*' 5C DC CL2'*' 5C40 DC 2CL2'*' 5C405C40 DC C'ABC' C1C2C3 DC CL1'ABC' C1 DC C'A&&B' C150C2 DC C‘JO''S' D1D67DE2 DC C'''' 7D
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Defining areas – Type X (hexadecimal)
X-Type DC (hexadecimal) [name] DC [Da] X [La]Ic
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Defining areas – Type X (hexadecimal) Valid characters: hexadecimal algarisms (0 to F) Each hexadecimal algarism occupies ½ byte.
Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be filled with x’0’.
If La specified is less than the enough to fit the value, the leftmost half-bytes will be truncated.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example).
DC DC DC DC DC DC 1XL1'0B' 3X'5C' XL3'5C' XL2'AB0C14' X'1A2' X'00A,B,5A8' 0B 5C5C5C 00005C 0C14 01A2 000A0B05A8
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Defining areas – Type B (binary)
B-type DC (binary) [name] DC [Da] B [La]Ic
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Defining areas – Type B (binary) Valid characters: binary algarisms (0 and 1) Each binary algarism occupies 1 bit.
Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining bits to the left will be filled with binary zeros.
If La specified is less than the enough to fit the value, the leftmost bits will be truncated.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example). DC DC DC DC DC DC BL1'0' B'0101' BL2'1' 00 BL2'010001001' 0089 05 0001 2B'1' 0101 B'1,00101,001' 010501
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Defining areas – Type F (full word)
F-type DC (full-word) [name] DC [Da] F [La]Ic
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Defining areas – Type F (full word) The value must be specified in decimal (Assembler will convert it to binary to fill the full-word) If no sign is specified, number will be assumed positive.
If sign is specified, it must be unique, and must come before the value.
If no La is specified, ALIGNMENT will be done to next address multiple of 4, before the area allocation.
If La is specified, NO ALIGNMENT will be done.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example). DC DC DC DC F'138' F'+138' F'-138' F'4,392' 0000008A 0000008A FFFFFF76 0000000400000188
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Defining areas – Type H (half word)
H-type DC (half-word) [name] DC [Da] H [La]Ic
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Defining areas – Type H (half word) The value must be specified in decimal (Assembler will convert it to binary to fill the half-word) If no sign is specified, number will be assumed positive.
If sign is specified, it must be unique, and must come before the value.
If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area allocation.
If La is specified, NO ALIGNMENT will be done.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example). DC DC DC DC H'138' H'+138' H'-138' H'4,392' 008A 008A FF76 00040188
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Defining areas – Type P (packed)
P-type DC (Packed) [name] DC [Da] P [La]Ic
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Defining areas – Type P (packed) The value must be specified in decimal. Each decimal algarism occupies ½ byte, plus ½ byte to the sign. Maximum length = 16 bytes (31 algarisms). Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be filled with binary zeros.
If La specified is less than the enough to fit the value, the leftmost half-bytes will be truncated.
If no La is specified, it will be allocated the enough to fit the value (including ½ byte for the sign).
Remember that if you specify an even number of algarisms, it will be needed one more half-byte to complete the field.
Multiple definitions per constant are allowed (see 3rd example). DC DC DC DC DC DC DC DC P'122' P'10' P'-345,45,21.6,7' P'0' P'+66' PL3'1' PL2'43556' 3P'1' 122C 010C 345D045C216C7C 0C 066C 00001C 556C 1C1C1C
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Defining areas – Type Z (zoned)
Z-type DC (zoned) [name] DC [Da] Z [La]Ic
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Defining areas – Type Z (zoned) The value must be specified in decimal. Each decimal algarism occupies 1 byte.
Maximum length = 16 bytes (16 algarisms). Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be filled with zoned zeros (x’F0’).
If La specified is less than the enough to fit the value, the leftmost bytes will be truncated.
If no La is specified, it will be allocated the enough to fit the value.
Multiple definitions per constant are allowed (see 2nd example). DC DC DC DC DC DC Z'122' Z'-345,45' Z'+66' ZL3'1' ZL2'43556' 3Z'1' F1F2C2 F3F4D5F4C5 F6C6 F0F0C1 F5C6 C1C1C1
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Defining areas – Type A (address)
A-type DC (address) [name] DC [Da] A [La]Ic
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Defining areas – Type A (address) The value must be specified as an expression (Assembler will convert it to a value / address to fill the full-word) If no La is specified, ALIGNMENT will be done to next address multiple of 4, before the area allocation.
If La is specified, NO ALIGNMENT will be done.
Multiple definitions per constant are allowed (see last example). CAMPO DC DC DC DC DC DC DC DC A(TABELA) A(TABELA-50) A(*) A(259) 3A(*-CAMPO) A(TCABC+28*52) A(FIM-COMECO) A(1,2,3) 00000103 00000000.00000004.00000008
00000001.00000002.00000003
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Defining areas – Type A (address) IMPORTANT: Addresses with relocatable values Loader; the absolute addresses (red) (green) are updated by Linkage Editor and keep unchanged .
CAMPO DC DC DC DC DC DC DC DC A(TABELA) A(TABELA-50) A(*) A(259) 3A(*-CAMPO) A(TCABC+28*52) A(FIM-COMECO) A(1,2,3) 00000103 00000000.00000004.00000008
00000001.00000002.00000003
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Defining areas – Type A (address) Example: (part of a program) 0008A0 47F0 38AC 0008A4 000008B2 0008A8 000008B5 008AC 008A4 008AC (part of the RELOCATION DICTIONARY of the program) 244+ 245+IHB0004 246+ 247+ B EQU DC DC 248+IHB0004A EQU RELOCATION DICTIONARY POS.ID
REL.ID
FLAGS 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0C 08 0C 0C 0C 0C 0C 0C 0C 04 04 04 04 ADDRESS 000070 0001B9 000860 000864 000868 00086C 000874 0008A4 0008A8 000A46 000A48 000A54 000A56 IHB0004A * A(ENTRA) A(SAI) *
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Defining areas – Type A (address) Example:
Souce program (VALIDATE routine; Assembler suppose that VALIDS address is X’00001BC0’) ...
VVV DC A(VALIDS) ...
...
...
VALIDS DC C’AEIOUaeiou’ ...
Object program to be called (suppose length = 4K = X’1000’) ...
00001BC0
...
...
...
C1C5C9D6E481858996A4 ...
...
...
...
Caller (main) object program (suopose length = 40K = X’A000’) CALL VALIDATE ...
...
...
Caller : from X’0000’ to X’9FFF’) Caller : from X’0000’ to X’9FFF’) Called routine: starting address = X’A000’ : occupies in the executable from X’A000’ to X’AFFF’ Executable
Lked Adds called routine to the caller program and ADJUSTS the relocatable address variables.
VVV contents is adjusted to X’0000BBC0’ ...
0000BBC0
...
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Defining areas – Type A (address) Example:
Executable program ...
0000BBC0
...
Loader Loads the executable program into storage (e.g. at address X’0BC40000’) and ADJUSTS the relocatable address constants.
VVV contents is adjusted to X’0BC40000’ + X’0000BBC0’ = X’0BC4BBC0’ Storage Executable program loaded (LOAD POINT) at address X’0BC40000’ ...
0BC4BBC0
...
Load Point = X’0BC40000’
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Defining areas – Type Y (2-byte address)
Y-type DC (address with 2 bytes) [name] DC [Da] Y [La]Ic
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Defining areas – Type Y (2-byte address) The value must be specified as an expression (Assembler will convert it to a value / address to fill the half-word) If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area allocation.
If La is specified, NO ALIGNMENT will be done.
Multiple definitions per constant are allowed (see last example). Note that the maximum allowed value is x'FFFF‘.
DC DC DC DC DC DC DC Y(TABELA) Y(TABELA-50) Y(*) Y(259) Y(TCABC+28*52) Y(FIM-COMECO) Y(1,2,3) 0103 0001.0002.0003
IMPORTANT: Addresses with relocatable values are updated by Linkage Editor and Loader; the absolute addresses keep unchanged .
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Defining areas – Type S (Base+Shift address)
S-type DC (base + shift address) [name] DC [Da] S [La]Ic
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Defining areas – Type S (Base+Shift address) The value must be specified as an expression (Assembler will convert it to a base+shift addres to fill the half-word) If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area allocation.
If La is specified, NO ALIGNMENT will be done.
Multiple definitions per constant are allowed (see last example). DC DC DC DC DC S(TABELA) S(TABELA-50) S(*) S(TCABC+28*52) S(*,*+2,*+4)
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Defining areas – Type V (external address)
V-type DC (external address) [name] DC [Da] V [La]Ic
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Defining areas – Type V (external address) It is analogue to the A-type constant, with the difference that the address is not possible to be solved at assembly time due to external symbol reference (e.g. an external routine).
The value is set to zero, and is filled in the object program at linkedit / load time.
DC V(ROUTINE)
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Defining areas – Type Q (external DSECT address)
Q-type DC (external DSECT shift) [nome] DC [ad] Q [at]ci
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Defining areas – Type Q (external DSECT address) This constant is used to do reference to a shift in an external DSECT.
The value is set to zero, and is filled in the object program at linkedit time.
The value must be specified as an expression (Assembler will conThe symbol refered to in the value must be previously externally defined as a DXD symbol or as a DSECT.
DC Q(DUMMYEXT)
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Defining areas - DS
DS - Define Storage Areas WITHOUT initial contents
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Defining areas - DS DS command is used to define an area without initial contents.
The syntax is analogue to the DC command.
WARNING! If initial contents is specified it WON’T BE CONSIDERED.
DS CL3 DS XL4 DS PL4'0' DS 3CL8
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Defining areas - DS DS command allows zero (0) duplication attribute. Examples: READAREA DS 0CL80 CODE DS CL10 DATE DS CL8 NAME DS CL50 CITY DS CL12 The duplication attribute does not define any area, it only “warns” that the next 80 bytes will be the area named READAREA (READAREA length attribute is 80).
In other words, the field starting at the byte pointed by the Location Counter is 80 bytes length and is named READAREA.
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Defining areas - DS The duplication attribute zero is often used to do alignment: FLDWITH4 DS 0F BYTE1 DS CL1 BYTE2 DS CL1 BYTE3 DS CL1 BYTE4 DS CL1 In this case, the assembler: - aligns to the next boundary 4 address (address multiple of 4) due to the F-type specified), and then allocates the fields BYTE1, BYTE2, BYTE3 e BYTE4.
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Defining areas - DS Another example of alignment use: ALFA DC F ’ 0 ’ BETA DC C ’ XYZ ’ DS 0H GAMA DS CL1 DELTA DS CL1 Alfa Beta (no name) Gama Delta ALFA is aligned because the F-type constant do the alignment.
BETA is aligned due to the alignment and length of ALFA.
GAMA, if it was declared just after BETA, won’t be aligned because BETA has 3 bytes. To align GAMA (to a boundary 2 address) it was included the H-type DS declaration with duplication attribute of zero.
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Defining areas - DS
Another use of DS command is to redefine areas (to attribute different names to same physical areas). See bellow: AREA1 DS 0CL80 A1PART1 DS CL10 A1PART2 DS CL10 A1PART3 DS CL10 A1PART4 DS CL10 A1PART5 DS CL10 A1PART6 DS CL10 A1PART7 DS CL10 A1PART8 DS CL10 ORG , RETURN TO AREA1 ADDRESS AREA2 DS 0CL80 A2PART1 DS CL20 A2PART2 DS CL20 A2PART3 DS CL20 A2PART4 DS CL20 ORG , RETURN TO AREA1 ADDRESS AREA3 DS 0CL80 A3PART1 DS CL5 A3PART2 DS CL5 A3PART3 DS CL20 A3PART4 DS CL30 A3PART5 DS CL3 A3PART6 DS CL4 A3PART7 DS CL13
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Machine Instructions MACHINE INSTRUCTIONS
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Machine Instructions – Hints and Tips Hints and Tips
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Machine Instructions – Hints and Tips 1 1 - STORE = FROM register TO storage 2 - LOAD = FROM storage TO register 3 xxxxR = RR instruction, operands are both registers 4 Example: AR,SR, LR, MR, DR, LTR xxxxI = SI instruction, 1 operand is an immediate operand; it is the 2nd byte of the instruction, and is specified via an self-defining term (1 byte length) 5 Example: MVI, SI, NI, OI, XI, etc xxxxP = SS instruction, decimal packed operands, 2 lengths specification Example: AP, SP, MP, DP, ZAP 6 xxxxH = RX instruction, operands are 1 register and 1 halfword storage field Example: LH, SH, AH
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Machine Instructions – Hints and Tips 2 7 Nxxxx = boolean instruction AND 8 Example: NI, NC, N, NR Oxxxx = boolean instruction OR 9 Example: OI, OC, O, OR Xxxxx = boolean instruction Exclusive OR Example: XI, XC, X, XR 10 Most instructions (except CVD and the STORE ones STC, ST, STH, STCM, STM ): symbol instruction receiver_operand,emitter_operand 11 STORE and CVD instructions: symbol instruction emitter_operand,receiver_operand
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Machine Instructions – Hints and Tips 3 12 - SS-L instructions (only one length) are: MVN, MVC, MVZ, NC, CLC, OC, XC, TR, TRT, ED, EDMK, MVCIN Maximum length of each operand is 256 bytes.
13 - SS-L1/L2 instructions (2 lengths) are: MVO, PACK, UNPK, ZAP, CP, AP, SP, MP, DP Maximum length for each operand is 16 bytes.
14 – SRP instruction is an exception in the SS group: it has a reference to a length (1st half of the 2nd byte), and a round (in the other half of the 2nd byte)
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Machine Instructions – Hints and Tips 4 15 – Use of Boolean instructions: OR = To force bits to 1 (turn ON bits) This can be used to (for instance) : (a) Set program flags to ON (b) Transform lowercase leters into uppercase letters (mask 0100 0000 : note in an EBCDIC table that the difference between lowercase and uppercase letters is always x’40’ (b’0100 0000’); turning the 2nd bit ON one can transform a lowercase letter into an uppercase letter. (c) Transform a binary number into the nearest high odd number (turning rightmost bit ON) Example: 1111 1110 is decimal 254. Turning rightmost bit ON: 1111 1111 it becomes decimal 255
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Machine Instructions – Hints and Tips 4 15 – Use of Boolean instructions: AND = Force bits to 0 (turn bits OFF) This can be used to (for instance) : (a) Set program flags to OFF (b) Transform uppercase leters into lowercase letters (mask 1011 1111 : note in an EBCDIC table that the difference between uppercase and lowercase letters is always x’40’ (b’0100 0000’); turning the 2nd bit OFF one can transform an uppercase letter into a lowercase letter. (c) Transform a binary number into the nearest low even number (turning rightmost bit OFF) Example: 1111 1111 is decimal 255. Turning rightmost bit OFF: 1111 1110 it becomes decimal 254
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Machine Instructions – Hints and Tips 4 15 – Use of Boolean instructions: XOR (ou exclusivo) = To invert bit setting (turns OFF if it is on, turns ON if it is OFF) This can be used to (for instance) : (a) Inverte program flags (toggle flags) (b) Transform lowercase into uppercase letter and vice-versa (mask 0100 0000) : letter x1xx xxxx becomes x0xx xxxx letter x0xx xxxx becomes x1xx xxxx (c) Transform binary even numbers into odd numbers and vice versa: (mask 0000 0001) : rightmost bit is inverted (d) Exchange the contents of 2 area without a 3rd auxiliary area : XOR A,B + XOR B,A + XOR A,B (e) “Clear” (move binary zeros) an area : XOR A,A
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Machine Instructions – Hints and Tips 4 16 – Arithmetic and bit shift operations (algebraic / logic operations): Unless othewise stated, these operations are done algebraically.
This is always true for decimal packed fields.
For binary fixed point numbers (in storage and/or registers) some operations that work algebraically and other operations work logically.
Algebraic operations uses: 15-bit binary numbers + 1 bit sign for 2 byte numbers 31-bit binary numbers + 1 bit sign for 4 byte numbers 63-bit binary numbers + 1 bit sign for 8 byte numbers Logical operations assume numbers are always positive and uses: 16-bit binary numbers for 2 byte numbers 32-bit binary numbers for 4 byte numbers 64-bit binary numbers for 8 byte numbers
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Machine Instructions
Machine instructions (alphabetically)
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Machine Instructions (Some) Machine instructions (by group)
-
Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCIN - Register to Storage move : ST, STH, STM, STC, STCM, CVD - Storage to Register move : L, LH, LM, IC, ICM, CVB
-
Register to Register move : LR, LPR, LNR, LCR, LTR - Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP - Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR
-
Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL - Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR - Branch : BC, BCR - Loop Control : BCT, BCTR, BXH, BXLE - Edition : ED, EDMK - Byte Translation and test: TR, TRT - Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA - Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC - Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM - Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS
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Machine Instructions Hints: what instruction do I have to use to move data from a place to another?
Origin
Storage Register Storage (zoned) Storage (packed) Register Storage (binary) Storage (packed) Register (binary) (address) (address)
Destination
Storage Register Storage (packed) Storage (zoned) Storage Register Register (binary) Storage (packed) Register Storage (contents=address)
Instruction
MVC LR PACK UNPK (maybe, additionally, MVZ / OI) ST L CVB CVD LA [ or L reg,=A(address) ] LA + ST [ or L + ST ]
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Machine Instructions - A A (ADD)
Machine Instruction Code Condition code 5A (RX Instruction) 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0005,0008 Possible Interruptions Instruction A adds algebraically the binary number in the 1st operand and the bynary number in a storage field (2nd operand – a full-word). Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after A 5,=F'259' 00.00.BF.D2 00.00.01.03 00.00.C0.D5 00.00.01.03
A 7,FULL 00.00.00.0D 00.00.01.03
00.00.01.10 00.00.01.03
A 7,4(2,8) 07.FF.FF.FE 00.00.00.01
07.FF.FF.FF 00.00.00.01
A 7,4(2) 07.FF.FF.FF FF.FF.FF.FF
07.FF.FF.FE FF.FF.FF.FF
A 7,4(,8) 00.00.00.00 FF.FF.FF.FF
FF.FF.FF.FF FF.FF.FF.FF
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Machine Instructions - AH AH (Add Halfword)
Machine Instruction Code Condition code 4A (RX Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0005,0008 This instruction adds algebraically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage half-word specified as 2nd operand.
Before the operation is executed, the half-word is internally expanded to 32 bits by repeating (to the left) the leftmost bit (sign bit). Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AH 5,=H'259' 00.00.2B.C4
01.03
00.00.2C.C7 01.03
AH 5,HALF 00.00.00.0D 01.0D
00.00.01.1A 01.0D AH 5,4(2,8) 11.11.11.11 (decimal 286331153) 88.88 (decimal –30584) 11.10.99.99 (decimal 286300569) 88.88
AH 5,4(2) 11.11.11.11 (decimal 286331153) 11.11.89.99 (decimal 286362009) 78.88 (decimal +30856) 78.88
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Machine Instructions - AL AL (Add Logical)
Machine Instruction Code Condition code 5E (RX Instruction) 00 Result = 0, sign not lost 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost 0005 Possible Interruptions This instruction adds logically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage full-word specified as 2nd operand. Both numbers are considered as positive 32-bit numbers. Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AL 5,=F'259' 00.00.00.00
00.00.00.00
00.00.01.03
00.00.01.03 00.00.01.03
AL 5,FULL 00.B0.C4.E2 00.00.00.01
00.B0.C4.E3 00.00.00.01
AL 5,4(2,8) 7F.FF.FF.FF 00.00.00.01
80.00.00.00 00.00.00.01
AL 5,4(2) FF.FF.FF.FF 00.00.00.01
00.00.00.01
AL 5,4(,8) 80.00.00.00 00.00.00.01
80.00.00.01 00.00.00.01
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Machine Instructions - ALR ALR (Add Logical Register)
Machine Instruction Code 1E (RR Instruction) Condition code 00 Result = 0, sign not lost 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions No interruptions occur This instruction adds logically the contents of two binary numbers, both located in registers.
Both numbers are considered as positive 32-bit numbers.
Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after ALR 7,12 00.B0.C4.E2
00.B0.C4.E3
00.00.00.01
00.00.00.01
ALR 8,8 ALR ALR 10,10 10,10 7F.FF.FF.FF
80.00.00.00
FF.FF.FF.FF
00.00.00.00
80.00.00.00
00.00.00.00
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
80.00.00.00
80.00.00.00
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Machine Instructions - AP AP (Add Packed)
Machine Instruction Code Condition code Possible Interruptions FA (SS Instruction – L1 e L2) 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0001,0004,0005,0007,000A This instruction adds the contents of two packed numbers, both located in storage fields.
Both numbers must be in the decimal packed format.
Result is stored into 1st operand field.
Examples: AP FLDA,FLDB before after FLDB 12.3C 12.3C
FLDA 12.34.5C 12.46.8C
AP FLDA,FLDA before after FLDA 45.2C 90.4C
See more examples following:
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Machine Instructions - AP AP (Add Packed)
Machine Instruction Code Condition code FA (SS Instruction – L1 e L2) 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0001,0004,0005,0007,000A Possible Interruptions Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after AP HOWMANY,=P'1' 00.00.5F 1C 00.00.6C 1C AP ARL+2(5),ARL+7(2) 01.23.40.00.0C 98.7C
01.23.40.98.7C 98.7C AP TOTAL,2(3,7) 55.66.77.78.8C 11.11.1D
55.66.66.67.7C 11.11.1D AP 4(3,8),WALFA 01.99.9F 02.0C
02.01.9C 02.0C AP 7(07,8),14(2,3) 00.00.00.00.01.23.4C 00.5C
00.00.00.00.01.23.9C 00.5C
AP GRANDTOT,SMALLTOT 00.00.00.0C 00.10.1C
00.00.10.1C
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Machine Instructions - AR AR (Add Register)
Machine Instruction Code Condition code Possible Interruptions 1A (RR Instruction) 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0008 This instruction adds the contents of two binary numbers, both located in registers.
The value of the register 2nd operand is added to the value of the register 1st operand.
Result is stored into register 1st operand. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AR 7,8 00.00.FF.FF
00.00.00.01
00.01.00.00
00.00.00.01
AR 2,2 00.00.FF.FF 00.00.FF.FF
00.01.FF.FE 00.01.FF.FE
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Machine Instructions – BAL BAL (Branch And Link)
Machine Instruction Code Condition code 45 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur BAL instruction is similar to the BALR instruction; the difference is that the address where the branch is to be made to (specified by the 2nd operand) is the instruction address in the base+displacement format (rather than the address in the register as in the BALR instruction).
Note that to load the next instruction address (generally used as the return address when branching to execute a routine) BAL loads the last 4 bytes of PSW into 1st operand register. Examples: BAL 9,ROUTINE BAL 14,WRTHDR BAL 7,2(5) BAL 7.2(,8) BAL 7,2(5,8) ...
...
BAL 9,ROUTINE RETINS EQU * continuation ...
...
ROUTINE ST 9,SAVEREG9 ....
....
L 9,SAVEREG9 BR 9
BAL loads the address of instruction labeled RETINS into register 9 Save register 9 (return address) into SAVEREG9 Restore return address Goback (to RETINS)
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Machine Instructions - BALR BALR (Branch And Link Register)
Machine Instruction Code Condition code 05 (RR Instruction) Remains unchanged Possible Interruptions No interruptions occur BALR instruction is similar to the BAL instruction; the difference is that the address where branch is to be made to (specified by the 2nd operand) is the value of the register 2nd operand (rather than the address in the base+displacement format as in the BAL instruction).
Important: if the second operand is register zero, branch won’t be executed.
Note that to load the next instruction address (generally the return address) BALR loads the last 4 bytes of PSW. Examples: BALR 3,0 BALR 14,15
LA loads the address of instruction labeled ROUTINE into register 15
...
LA 15,ROUTINE BALR 14,15 RETINS EQU * continuation ...
...
ROUTINE ST 14,SAVEREG ....
....
L 14,SAVEREG BR 14
BALR loads the address of instruction labeled RETINS into register 14 Save register 14 (return address) into SAVEREG Restore return address Goback (to RETINS)
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Machine Instructions - BAS BAS (Branch And Save)
Machine Instruction Code Condition code Possible Interruptions 4D (RX Instruction) Remains unchanged No interruptions occur The address of the next instruction (following BAS) is loaded in the register 1st operand: - Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register - Leftmost byte of register 1st operand is set to zero (this is the difference between BAS and BAL) After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand.
Example:
BAS 14,ROUTINE
...
...
BAS 9,ROUTINE RETINS EQU * continuation ...
...
ROUTINE ST 9,SAVEREG ....
....
L 9,SAVEREG BR 9
BAS loads the address of instruction labeled RETINS into register 9 bytes 1,2,3 and sets byte 0 with zero Save register 9 (return address) into SAVEREG Restore return address Goback (to RETINS)
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Machine Instructions - BASR BASR (Branch And Save Register)
Machine Instruction Code Condition code 0D (RR Instruction) Remains unchanged Possible Interruptions No interruptions occur The address of the next instruction (following BASR) is loaded in the register 1st operand: - Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register - Leftmost byte of register 1st operand is set to zero (this is the difference between BASR and BALR) After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand.
Example:
BASR 14,15 LA loads the address of instruction labeled ROUTINE into register 15 Restore return address Goback (to RETINS)
...
LA 15,ROUTINE BASR 14,15 RETINS EQU * continuation ...
...
ROUTINE ST 14,SAVEREG ....
....
L 14,SAVEREG BR 14
BASR sets register 14 byte 0 with zero and loads the address of instruction labeled RETINS into bytes 1,2,3 of register 14 Save register 14 (return address) into SAVEREG
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Machine Instructions - BASSM BASSM (Branch And Save and Set Mode)
Machine Instruction Code Condition code 0C (RR Instruction) Remains unchanged Possible Interruptions No interruptions occur The address of the next instruction (following BASSM) is loaded in the register 1st operand: - Bytes 4, 5, 6 and 7 (last 4 bytes of PSW) are loaded into bytes 0, 1, 2, 3 of the register 1st operand - The value of register 2nd operand is loaded into bytes 4-7 of PSW; it includes leftmost bit (addressing mode) and (next) instruction address.
Due to this, the addressing mode is (re)set and a branch is provided.
Example:
BASSM 14,15 LA loads the address of instruction labeled ROUTINE into register 15 ICM sets addressability mode into register 15 bits Restore return address Goback (to RETINS)
LA 15,ROUTINE ICM 15,8,AMODE BASSM 14,15 RETINS EQU * continuation ...
...
ROUTINE ST 14,SAVEREG ....
....
L 14,SAVEREG BR 14
BASSM : - Sets register 14 with the address of instruction labeled RETINS into register 14 (taken from PSW)
- Loads contents of register 15 into
PSW bytes 4-7 (Addressing mode is set [from reg. 15 into PSW] ) and (Branch to ROUTINE is executed) Save register 14 (return address) into SAVEREG
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Machine Instructions - BC BC (Branch on Condition)
There are 2 branch instructions: BC (RX Instruction) and BCR (RR Instruction).
But they have many auxiliary mnemonic codes, named extended mnemonic codes.
The branch instruction execution is based upon the status of Condition Code (remember?
Those 2 bits of PSW) and the mask provided in the instruction (in the left half of its 2nd byte).
The 4 different status Condition Code can be are: 00, 01, 10 and 11.
For each one of them there is a corresponding code: STATUS 00 01 10 11 CODE 8 4 2 1 The MASK occupies half byte and indicates the condition in which branch MUST be done.
It can vary from X'0' to X'F' (decimal 0 up to 15).
MASK 8, CC B'00‘ = Branch executed MASK 4, CC B'01‘ = Branch executed MASK 2, CC B'10“ = Branch executed MASK 1, CC B’11’ = Branch executed
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Machine Instructions - BC BC (Branch on Condition)
One can do a combination of the masks, by adding their value.
For instance, if mask is X'C', it means that branch must occur if Condition Code is in the 8 (8 + 4 = 12).
or
4 status If mask is zero, no branch will be done (NOP/NOPR = no operation).
If mask is 15 (X'F') branch will be done no matter waht is the Condition Code setting, because 15 = all codes added (8+4+2+1); it is an unconditional branch.
Branch instructions with masks from 1 to 14 are conditional branches: the branch will only be done if Condition Code is apropriately set.
See in the following slide the list of mnemonic codes, the valid masks and the extended mnemonic codes.
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Machine Instructions - BC BC (Branch on Condition)
------------------------------------------------------------------------- USE General MNEMONIC B or BR MEANING Allways branches BC/BCR EQUIVALENCE ------------------------------------------------------------------------- BC 15 or BCR 15 After NOP or NOPR BH or BHR Never branches Branch if A > B BC BC 0 2 or or BCR 0 ------------------------------------------------------------------------- BCR 2 Compare BL or BLR BE or BER Branch if A < B Branch if A = B BC BC 4 8 or or BCR BCR 4 8 BNH or BNHR BNL or BNLR Branch if A < or = B Branch if A > or = B BC BC 13 11 or or BCR BCR 13 11 After BNE or BNER BO or BOR Branch if A not = B Branch if overflow BC BC 7 1 or or BCR 7 ------------------------------------------------------------------------- BCR 1 Arithmetic BP or BPR Instructions BM or BMR BZ or BZR Branch if R > 0 Branch if R < 0 Branch if R = 0 BC BC BC 2 4 8 or or or BCR BCR BCR 2 4 8 BNP or BNPR BNM or BNMR Branch if R < or = 0 Branch if R > or = 0 BC BC 13 11 or or BCR BCR 13 11 After TM BNZ or BNZR BO or BOR Branch if R not = 0 Branch if all bits 1 BC BC 7 1 or or BCR 7 ------------------------------------------------------------------------- BCR 1 BM or BMR BZ or BZR Branch if mixed Branch if all bits 0 BC BC 4 8 or or BCR BCR 4 8 BNO or BNOR Branch if some are 1 BC 14 or BCR 14 ------------------------------------------------------------------------- Notes: A = 1st operand ; B = 2nd operand ; R = 1st operand after compute
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Machine Instructions - BC BC (Branch on Condition)
The extended menmonic codes are: B NOP BH BL BE BNH BNL BNE BO BP BM BZ BNP BNM BNZ BO BM BZ BNO = Branch = No Operation = Branch High = Branch Low = Branch Equal = Branch Not High = Branch Not Low = Branch Not Equal = Branch If Overflow = Branch If Plus = Branch If Minus = Branch If Zero = Branch If Not Plus = Branch If Not Minus = Branch If Not Zero = Branch If Ones = Branch If Mixed = Branch If Zeros = Branch If Not Ones
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Machine Instructions - BC BC (Branch on Condition) BC (Branch on Condition) Machine Instruction Code
Condition code 47 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur This instruction branches (or not) to another instruction. The format is: 1st byte = operation code = 47 2nd byte – 1st half = mask 2nd byte – 2nd half = index register for 2nd operand (branch instruction address) 3rd and 4th byte = 2 bytes with base+displacement of 2nd operand (branch instruction address) 1st operand is the mask; it indicates the condition branch must be done (or not).
2nd operand address is the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BC).
If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand.
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Machine Instructions - BC BC (Branch on Condition) BC (Branch on Condition) Machine Instruction Code
Condition code 47 (RX Instruction) Remains unchanged Possible Interruptions If one uses the No interruptions occur mnemonic code, only one “operand” must be specified: the address to branch to; in this case the mask is implicit in the mnemonic. Example: BC is the same as BE BE is the same as BC 8.
8,AGAIN AGAIN In this case, the branch will be done when condition code is 00. Other examples: B READ same as BC 15,READ BH AGAIN same as BC 2,AGAIN BL BE BE BE NOP COMPARE 0(2) 0(,4) 0(2,4) TOGGLE1 same as same as same as same as same as BC 4,COMPARE BC 8,0(2) BC 8,0(,4) BC 8,0(2,4) BC 0,TOGGLE1
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Machine Instructions - BC BC (Branch on Condition) BC (Branch on Condition) Machine Instruction Code
Condition code 47 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur Other examples: B BNH BNL BNE BZ BNZ BM READ LOOP1 LOOP2 0(2) 0(,4) 0(2,4) BTAB(15) same as same as same as same as same as same as same as BC 15,READ BC 13,AGAIN BC 11,COMPARE BC 7,0(2) BC 8,0(,4) BC 7,0(2,4) BC 4,BTAB(15)
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Machine Instructions - BCR BCR (Branch on Condition Register) BCR (Branch on Condition Register) Machine Instruction Code
Condition code Possible Interruptions 07 (RX Instruction) Remains unchanged No interruptions occur BCR instruction is similar to BC instruction.
SEE BC INSTRUCTION.
The format is: 1st byte = operation code = x’07’ 2nd byte – 1st half = mask (1st operand) 2nd byte – 2nd half = register 2nd operand containing the branch instruction address 1st operand is the mask; it indicates the condition branch must be done (or not).
2nd operand register must contain the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BCR).
If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand.
If one uses the mnemonic code, only the register 2nd operand must be specified.
See examples following:
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Machine Instructions - BCR BCR (Branch on Condition Register) BCR (Branch on Condition Register) Machine Instruction Code
Condition code Possible Interruptions 07 (RX Instruction) Remains unchanged No interruptions occur BCR is the same as BER BER is the same as BCR 8.
8,15 15 In this case, the branch will be done when condition code is 00. Other examples: BCR 2,10 same as BHR 10 BR 7 same as BCR 15,R7 BNER 10 same as BCR 7,R10 BLR 15 same as BCR 4,R15
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Machine Instructions - BCT BCT (Branch on CounT)
Machine Instruction Code Condition code 46 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur This instruction has 2 operands: the first one is a register, and the second is an instruction address.
BCT subtracts 1 from the register 1st operand and after it compares the resulting number with zero.
If result not equal to zero, it will provide a branch to the instruction referred in the 2nd operand If result is zero the branch won’t be done, processing will resume at the next instruction after BCT.
Examples: BCT 5,AGAIN BCT 2,0(4,7) BCT 2,0(4) BCT 2,0(,7) ...
L 11,=F’200’ AGAIN CLC 0(3,5),CODE BE FOUND ...
...
....
....
...
BCT 11,AGAIN NOTFND EQU * FOUND EQU *
L loads into register 11 number of times loop must be repeated At the end of the set of loop instructions, BCT subtracts 1 from register 11. If zero not reached, branchs to AGAIN.
If zero, resumes execution at NOTFND
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Machine Instructions - BCTR BCTR (Branch on CounT Register)
Machine Instruction Code Condition code 06 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur BCTR instruction has 2 operands, both in registers.
BCTR subtracts 1 from the register 1st operand and after it compares the resulting number with zero.
If result not = zero, a branch is provided to the instruction whose address is in the register 2nd operand If result is zero the branch won’t be done, processing will resume at the next instruction after BCTR.
IMPORTANT: If 2nd operand is register zero, branch won’t be done; this is often used just to subtract 1 from a register, rather than, for instance, the S or SH instructions.
Examples: BCTR 2,7 BCTR 4,0
LA loads into register 15 the address of AGAIN instruction
LA 15,AGAIN L 11,=F’200’ AGAIN CLC 0(3,5),CODE BE FOUND ...
...
....
....
...
BCTR 11,15 NOTFND EQU * FOUND EQU *
L loads into register 11 number of times loop must be repeated At the end of the set of loop instructions, BCTR subtracts 1 from register 11. If zero not reached, branchs to AGAIN.
If zero, resumes execution at NOTFND
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Machine Instructions - BSM BSM (Branch and Set Mode)
Machine Instruction Code Condition code 0B (RR Instruction) Remains unchanged Possible Interruptions No interruptions occur (a) (b) The PSW’s addressing mode (bit 32) is loaded into bit 0 of the register 1st operand; bits 1-31 remain unchanged , and after that PSW’s Bytes 4-7 is loaded with contents of register 2nd operand (including addressing mode bit and next instruction address) Thus a addressing mode setting is done followed by a branch.
If 2nd operand is register zero, branch is not executed.
Example:
BSM 14,15
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Machine Instructions - BXH BXH (Branch on indeX High)
Machine Instruction Code Condition code 86 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur 1st and 2nd operands are registers.
3rd operand is an instruction address.
(a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with: Contents of register 2nd operand (if it is an odd register) or Contents of register following register 2nd operand (if it is an even register) If the compare result is Greater than it will be executed a branch to the instruction addressed by 3rd operand Less than or equal to the branch will not be executed; processing resumes at the instruction following BXH
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Machine Instructions - BXH BXH (Branch on indeX High)
Machine Instruction Code Condition code 86 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur Examples: BXH 7,8,AGAIN R7 = R8 + R7; If R7 > R9 Branch to AGAIN; * If R7 <= R9 next instruction BXH 7,9,AGAIN R7 = R9 + R7; If R7 > R9 Branch to AGAIN; * If R7 <= R9 next instruction BXH 7,9,8(4) R7 = R9 + R7; If R7 > R9 Branch to instruction * whose address is [ (contents R4) + x’008’ ] * If R7 <= R9 next instruction
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Machine Instructions - BXH BXH (Branch on indeX High)
Machine Instruction Code Condition code 86 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur Example: Use in a search loop: R7 = begins with table address; incremented by element table length via R8 R8 = Table element length R9 = Last element address NOTFOUND : all table read, desired item not found.
L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH) NEXTITEM pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXH R7,R8,NOTFOUND B NEXTITEM TABLSEEN ...
BXH 7,8,NOTFOUND R7 = R8 + R7; * If R7 > R9 all table already read; end search * If R7 <= R9 table not exhausted; continue search
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Machine Instructions - BXLE BXLE (Branch on indeX Less or Equal)
Machine Instruction Code Condition code 87 (RS Instruction) Remains unchanged Possible Interruptions No interruptions occur BXLE is similar to BXH instruction; the difference is that the branch is done if the result of the compare is Less or Equal. 1st and 2nd operands are registers.
3rd operand is an instruction address.
(a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with: Contents of register 2nd operand (if it is an odd register) or Contents of register following register 2nd operand (if it is an even register) If the compare result is Less or Equal to : it will be executed a branch to the instruction addressed by 3rd operand Greater than : the branch will not be executed; processing resumes at the instruction following BXLE
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Machine Instructions - BXLE BXLE (Branch on indeX Less or Equal)
Machine Instruction Code Condition code 87 (RS Instruction) Remains unchanged Possible Interruptions Examples: No interruptions occur BXLE 7,8,AGAIN R7 = R8 + R7; If R7 <= R9 Branch to AGAIN; * If R7 > R9 next instruction BXLE 7,9,AGAIN R7 = R9 + R7; If R7 <= R9 Branch to AGAIN; * If R7 > R9 next instruction BXLE 7,9,8(4) R7 = R9 + R7; If R7 <= R9 Branch to instruction * Whose address is [ (contents R4) + x’008’ ] * If R7 > R9 next instruction
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Machine Instructions - BXLE BXLE (Branch on indeX Less or Equal)
Machine Instruction Code Condition code 87 (RS Instruction) Remains unchanged Possible Interruptions No interruptions occur Example: Use in a search loop: R7 = begins with table address; incremented by element table length via R8 R8 = Table element length R9 = Last element address NOTFOUND : all table read, desired item not found L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH) NEXTITEM compare pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXLE R7,R8,NEXTITEM NOTFOUND ...
TABLSEEN ...
BXLE 7,8,NOTFOUND R7 = R8 + R7; * If R7 <= R9 table not exhausted; continue search * If R7 > R9 all table already read; end search
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Machine Instructions - C C (Compare)
Machine Instruction Code Condition code 59 (RX Instruction) 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after C 0005 Possible Interruptions C performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a full-word, the 2nd operand). Example: C 9,CPO C 8,=F'0' C 13,=A(TABLE+430) C 1,2(4) C 1,2(,4) C 1,2(7,4)
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Machine Instructions - CDS CDS (Compare Double and Swap)
Machine Instruction Code Condition code BB (RS Instruction) Possible Interruptions 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS 1st and 3rd operands are even registers. They are considered an indication of: 1st operand: double-word composed by R1 and R1+1 3rd operand: double-word composed by R3 and R3+1 2nd operand is an storage field (double-word).
Contents of 1st operand (R1 and R1+1) is compared with the contents of the double-word 2nd operand.
If they are equal, the contents of the 3rd operand (R3 and R3+1) is stored into the 2nd operand double-word.
If they are not equal, the contents of the double-word 2nd operand is loaded into the 1st operand (R1 and R1+1).
See the following examples:
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Machine Instructions - CDS CDS (Compare Double and Swap)
Machine Instruction Code Condition code BB (RS Instruction) Possible Interruptions 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS CDS 4,8,DW Before: R4/R5 00.BF.C4.20.50.CC.A0.00 R8/R9 7D.48.C0.00.00.00.00.02
DW 00.BF.C4.20.50.CC.A0.00
After: R4/R5 00.BF.C4.20.50.CC.A0.00 R8/R9 7D.48.C0.00.00.00.00.02
DW 7D.48.C0.00.00.00.00.02
CDS 4,8,DW Before: R4/R5 00.CC.DD.EE.FF.FF.FF.FF R8/R9 7D.48.C0.00.00.00.00.02
DW 00.BF.C4.20.50.CC.A0.00
After: R4/R5 00.BF.C4.20.50.CC.A0.00
R8/R9 7D.48.C0.00.00.00.00.02
DW 00.BF.C4.20.50.CC.A0.00
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Machine Instructions - CH CH (Compare Halfword)
Machine Instruction Code Condition code 49 (RX Instruction) 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CH Possible Interruptions 0005 CH performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a half-word, the 2nd operand). To do that, the 2nd operand is expanded (internally in the CPU) to 4 bytes, by repeating (to the left) 16 times the leftmost bit of the half-word.
Example: CH 9,FLD 1st operand = R9; 2nd operand = FLD field CH 8,=H'0' 1st operand = R8; 2nd operand = half-word with zeros CH 13,=Y(TAB+430) 1st operand = R13; 2nd operand = half-word with address of TAB+430 CH 1,2(4) 1st operand = R1; 2nd operand = storage half-word which * address = value of index register R4 +0[base register omitted] + x’2’ CH 1,2(,4) 1st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +0[index register omitted] + x’2’ CH 1,2(7,4) 1st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +R7[index register] + x’2’
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Machine Instructions - CL CL (Compare Logical)
Machine Instruction Code Condition code 55 (RX Instruction) Possible Interruptions 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CL 0005 The CL instruction compares logically the contents of register 1st operand and the contents of a storage full-word (2nd operand).
Logical compare is done left to right, one bit at a time; the first couple of unequal bits finish the operation..
Examples: CL 9,CPO 32 bits of register 9 compared with 32 bits of 4-byte CPO CL 8,=F'0' 32 bits of register 8 compared with 32-bit of 4-byte full-word with zero CL 1,2(4) 32 bits of register 1 compared with 4-byte storage field * ( 2nd operand address = contents of index reg. 4 + displacement X’2’ [base reg. omitted = zero = not considered] ) CL 1,2(,4) 32 bits of register 1 compared with 4-byte storage field * ( 2nd operand address = [ index reg. Omitted = zero = not considered] + displacement X’2’ + base reg.4 ) CL 1,2(7,4) 32 bits of register 1 compared with 4-byte field * ( 2nd operand address = contents of index reg. 7 + displacement X’2’ + contents of base reg. 4 )
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Machine Instructions - CLC CLC (Compare Logical Character)
Machine Instruction Code D5 (SS Instruction – L) Condition code Possible Interruptions 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLC 0005 This instruction compares logically (left to right, one bit at a time) two storage fields. The first not equal couple of bits finish the compare. Examples: CLC CPOA,CPOB Only one length used = length of CPOA (e.g. 100 bytes) CLC AE+78(2),=C'*1' 2-byte (AE+78 and AE+79) storage field is compared with * 2-byte storage field referenced via literal (contents = X’5CF1’) CLC 4(2,7),2(9) 2 bytes field (address = base register 7 + displacement X’4’) * is compared with storage field ( address = base register 9 + displacement X’2’ ) CLC ID,2(7) n-byte storage field ID is compared with n-byte storage field * (address = base register 7 + displacement X’2’ ) CLC 194(5,11),AE+3 5-byte storage field (address = base register 11 + displacement X’C2’) * is compared with 5-byte storage field ( address = AE+3 )
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Machine Instructions- CLCL CLCL (Compare Logical Character Long)
Machine Instruction Code Condition code 0F (RR Instruction) Possible Interruptions 00 1st operand = 2nd operand or both operands have zero length.
01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL 0005,0006 This instruction compares two storage fields, in a similar way the CLC does.
Both 1st and 2nd operands must be even registers. They indicate (each one of them) a pair of even-odd registers. We’ll call them: 1st pair = R1st and R1st+1; 2nd pair = R2nd and R2nd+1 The 1st operand (receiver field) address must be in the last 3 bytes (righmost) of R1st.
The 2nd operand (sender field) address must be in the last 3 bytes (righmost) of R2nd.
The 1st operand length must be in the last 3 bytes (rightmost) of R1st+1.
The 2nd operand length must be in the last 3 bytes (rightmost) of R2nd+1.
The leftmost byte of R2nd+1 must have the padding character.
The leftmost byte of R1st, the leftmost byte of R2nd and the leftmost byte of R1st+1 are not considered in the operation. Example: CLCL 2,8 R2=1st operand register (dubbed as R1st above); note that R1st+1 = register 3 R8=2nd operand register (dubbed as R2nd above); note that R2nd+1 = register 9
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Machine Instructions- CLCL CLCL (Compare Logical Character Long)
Machine Instruction Code Condition code 0F (RR Instruction) Possible Interruptions 00 1st operand = 2nd operand or both operands are zero length.
01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Compare is done one bit at a time, from left to right. When not 2 bits unequal are found OR when length of greater operand is exhausted compare is finished.
If the operands have no equal kengths, the smaller one is extended with the padding character (internally, without any change in the field).
If compare is finished due to 2 bits unequal encountered: - From the value in the rightmost 3 bytes of R1st+1 and R2nd+1 is subtracted the amount of equal bytes; if the difference was found with the padding character the rightmost 3 bytes of R1st OR R2nd+1 are zeroed (the ones who have the smallest length).
- To the value of the rightmost 3 bytes of R1st and R2nd is added the amount of equal bytes.
If both operands are equal (including the padding character, if needed): - The 3 rightmost bytes of R1st+1 AND R2nd+1 are zeroed.
- To the 3 rightmost bytes of R1st AND R2nd is added the amount of equal bytes.
In both cases : the leftmost byte of R1 and the leftmost byte of R2 are zeroed, and the leftmost byte of R1st+1 and R2nd+1 remain unchanged.
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Machine Instructions- CLCL CLCL (Compare Logical Character Long)
Machine Instruction Code Condition code 0F (RR Instruction) Possible Interruptions 00 1st operand = 2nd operand or both operands are zero length.
01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Example:
LA loads into register 8 the BUFERIN address LA loads into register 9 the BUFERIN length CLCL executes the compare between a 12000-byte field (BUFEROUT) and a 20000 byte field (BUFERIN)
...
... ...
...
...
LA 2,BUFEROUT LA 3,12000 LA 8,BUFERIN LA 9,20000 ICM 9,B'1000',C' ' AGAIN CLCL 8,9 BE EQUALS DIFFS EQU * EQUALS EQU *
LA loads into register 2 the BUFEROUT address LA loads into register 3 the BUFEROUT length ICM inserts padding character into leftmost byte of register 9
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Machine Instructions - CLI CLI (Compare Logical Immediate)
Machine Instruction Code Condition code 95 (SI Instruction) Possible Interruptions 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLI 0005 This instruction compares logically (left to right, one bit at a time) two storage fields. The first operand is a “normal” storage field with its address expressed with a base+displacement address.
The second operand is also a storage field, but it is located IN the instruction: it is the instruction’s 2nd byte. It’s not necessary to specify its address, only its contents.
Examples (note that b1d1d1d1 is the address of the 1st operand, in the base+displacement format): CLI AE+79,C'*' Machine code = 95.5C.
b1d1 .
d1d1 Compare with asterisk CLI 2(5),X'00' Machine code = 95.00.50.02 Compare with binary zeros CLI BYTE,B'11110000' Machine code = 95.F0.
b1d1 .
d1d1 Compare with character zero CLI NOP+1,240 Machine code = 95.F0.
b1d1 .
d1d1 Compare with character zero
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Machine Instructions - CLM CLM (Compare Logical under Mask)
Machine Instruction Code Condition code BD (RS Instruction) Possible Interruptions 00 Selected bytes are equal, or mask is zero 01 Selected field of the 1st operand is less than 2nd operand 10 Selected field of the 1st operand is greater than 2nd operand 11 Condition code is not set as 11 after CLM The contents of register 1st operand is logically compared (left to right, one bit at a time) with the contents of the 2nd operand, based on the control of the mask 3rd operand. The result is reflected in the setting of the condition code.
It’s a RS instruction, with the following format: Byte 1= x’BD’ (operation code); operand; right half = M3 =(mask) Byte 2 = left half = R1 = register 1st Bytes 3 and 4 = 2nd operand address (base+displacement) The 4-bit mask, left to right, are related to the 4 bytes of the register 1st operand. The register bytes whose bits in the mask are ON are considered as a contiguous field, and compared with the storage field specified in the 2nd operand (the 2nd operand must have a length equal to the number of bits ON in the mask.
The register bytes whose bits in the mask are OFF are not considered in the operation. Example: CLM 5,B'1011',ARCOMP The “field” composed by 1st , 3rd and 4th bytes of register 5 is compared with the 3-byte field named ARCOMP.
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Machine Instructions - CLR CLR (Compare Logical Register)
Machine Instruction Code 15 (RR Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLR Possible Interruptions No interruptions occur The CLR instruction compares logically the contents of the 2 registers (1st operand and 2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits found finish the operation. Examples: CLR 4,5 32-bit “string” of register 4 compared with 32 bit “string” of register 5 CLR 8,13 32-bit “string” of register 8 compared with 32-bit “string” of rregister 13
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Machine Instructions - CP CP (Compare Packed)
Machine Instruction Code Condition code F9 (SS Instruction – L1 e L2) Possible Interruptions 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CP 0005,0007 The CP instruction compares the contents of 2 storage fields ( 1st and 2nd operands). Both must be in the decimal packed format, and remain unchanged. The lengths can be different: the values are compared, not the sizes. Examples: CP FLDA,FLDB If FLDA = X’00000009999C’ and FLDB = X’10000C’ * Result is : 1st operand less than 2nd operand CP COUNTLIN,=P'1' If COUNTLIN = X’999999D’ compared with X’1C’ * Result is : 1st operand less than 2nd operand CP 0(5,9),=P'0' Compares contents of 5-byte field at address * (base register 9 + X’0’) with zero CP TOTAL,2(7,9) Compares contents of TOTAL with 7-byte field address (base register 9 + displacement X’2’)
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Machine Instructions - CR CR (Compare Register)
Machine Instruction Code 19 (RR Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CR Possible Interruptions No interruptions occur The CR instruction compares 2 binary numbers within 2 registers (1st and 2nd operands). Both remain unchanged. Examples: CR 4,5 31-bit binary number in register 4 compared with 31-bit binary number in register 5 13 CR 8,13 31-bit binary number in register 8 compared with 31-bit binary number in register
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Machine Instructions - CS CS (Compare and Swap)
Machine Instruction Code BA (RS Instruction) Condition code Possible Interruptions 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 10 after CS 11 Condition code is not set as 11 after CS 1st and 3rd operands are registers.
2nd operand is a storage field (full-word).
The contents of the register 1st operand is compared with the 2nd operand full-word.
If they are equal, the contents of register 3rd operand is stored in the 2nd operand full-word.
If they are unequal the contents of the 2nd operand full-word is loaded into register 1st operand.
Examples: CS 5,8,FW Before: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 00.BF.C4.20
After: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 7D.48.C0.00
CS 5,8,FW Before: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 00.FF.EE.DD
After: R5 00.FF.EE.DD R8 7D.48.C0.00 FW 00.FF.EE.DD
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Machine Instructions - CVB CVB (ConVert to Binary)
Machine Instruction Code Condition code 4F (RX Instruction) Remains unchanged Possible Interruptions 0005, 0007, 0009 The decimal packed number within the 8-byte field 2nd operand (normally a double-word – it remains unchanged), is converted to binary and loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVB 8,DOUBLE 12.BC.4F.CA
* 00.00.00.00.00.01.02.4D
FF.FF.FC.00 00.00.00.00.00.01.02.4D
2nd operand = DOUBLE CVB 8,0(5,9) FF.FF.FF.FF 00.00.00.00.00.01.02.5C
00.00.04.01 00.00.00.00.00.01.02.5C
* 2nd operand address = index register 5 + base register 9 + X’0’ CVB 8,0(,9) FF.FF.FF.FF 00.00.00.00.00.01.02.3F
00.00.03.FF 00.00.00.00.00.01.02.3F
* 2nd operand address = index register 0 + base register 9 + X’0’ CVB 8,0(5) FF.FF.FF.FF 00.00.00.00.00.01.02.3C
00.00.03.FF 00.00.00.00.00.01.02.3C
* 2nd operand address = index register 5 + base register 0 + X’0’
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Machine Instructions - CVD CVD (ConVert to Decimal [packed])
Machine Instruction Code Condition code 4E (RX Instruction) Remains unchanged Possible Interruptions 0004,0005 The binary number within the register 1st operand is converted to decimal packed format and stored into the 8-byte field 2nd operand (normally a double-word).
For positive numbers or zero, sign is ‘C’. For negative numbers sign is ‘D’.
Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVD 8,DOUBLE 00.00.10.00
* 00.00.00.00.00.00.00.70
00.00.10.00 00.00.00.00.00.04.09.6C
2nd operand = DOUBLE CVD 8,0(5,9) FF.FF.FF.FF 00.00.FB.EC.44.CC.F0.F1
FF.FF.FF.FF 00.00.00.00.00.00.00.1D
* 2nd operand address = index register 5 + base register 9 + X’0’ CVD 8,0(,9) 00.00.99.99 98.BA.76.FE.54.DC.32.B9
00.00.99.99 00.00.00.00.00.39.32.1C
* 2nd operand address = index register 0 + base register 9 + X’0’ CVD 8,0(5) 00.00.AA.AA 00.00.00.00.00.00.00.0C
00.00.AA.AA 00.00.00.00.00.43.69.0C
* 2nd operand address = index register 5 + base register 0 + X’0’
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Machine Instructions - D D (Divide)
Machine Instruction Code Condition code 5D (RX Instruction) Remains unchanged Possible Interruptions 0005,0006,0008 This instruction executes a division between 2 binary numbers.
1st operand indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits.
The number within this couple of registers is the dividend.
The divisor is the number within the 2nd operand storage field (full-word).
After division: -The remainder is stored into the even register from the even-odd couple.
- The quotient is stored in the odd register from the even-odd couple.
Examples: L 6,=F'0' L D 7,=F'257' 6,=F'4' * L 10,=F'0' L D 11,=F'17' 10,=F'3' * Dividend: Registers 6-7 together; They have the number 257 Divisor: (literal) with number 4; Quotient: Register 7 = 64; Remainder: Register 6 = 1 Dividend: Registers 10-11 together; They have the number 17 Divisor: (literal) with number 3; Quotient: Register 11 = 5; Remainder: Register 10 = 2
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Machine Instructions - DP DP (Divide Packed)
Machine Instruction Code Condition code FD (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0004,0005,0006,0007,000B The DP instruction executes a division between 2 storage fields, both in packed decimal format. 1st operand is the dividend, and 2nd operand is the divisor.
After division the quotient and the remainder are stored in the 1st operand storage field.
2nd operand remains unchanged.
About the 2nd operand divisor (a) it remains unchanged after division (b) it cannot exceed 8 bytes (c) its length cannot be greater than or equal to the 1st operand length (d) if condition b or c occurs, program will interrupt with code 0006.
The remainder is stored in the rightmost bytes of the 1st operand, with divisor’s length.
Code 000B interruption occurs when: Quotient’s length is greater than the length available to it in the 1st operand Dividend has not at least 1 leftmost zero algarism.
Divisor is zero.
See the following examples:
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Machine Instructions - DP DP (Divide Packed)
Machine Instruction Code Condition code FD (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0004,0005,0006,0007,000B Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after DP FLDA,FLDB 00.00.45.67.8C 00.2C
22.83.9C.00.0C 00.2C DP FLDA,FLDB 00.00.00.11.1C 00.2C
00.05.5C.00.1C 00.2C DP VALUE,=P'5' 00.00.00.00.00.12.7C 5C 00.00.00.00.02.5C.2C 5C
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Machine Instructions - DR DR (Divide Register)
Machine Instruction Code 1D (RR Instruction) Remains unchanged Possible Interruptions 0006,0009 This instruction executes a division between 2 binary numbers, both in registers.
1st operand must indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits.
The number within this couple of registers is the dividend. 2nd operand is the divisor.
After division: - The quotient is stored into the odd register - The remainder is stored into the even register - If the remainder and/or quotient are = 0, their sign will be 0; remainder’s sign is the same as dividend’s sign Examples: L 12,=F'2' L 4,=F'0' L 5,=F'257' DR 4,12 * L L 9,=F'12' 6,=F'0' L 7,=F'148' DR 6,9 Divisor: Register 12 with number 2 Dividend: Registers 4-5 together; They have the number 257 Quotient: Register 5 = 128; Remainder: Register 4 = 1 Divisor: Register 9 with number 12 Dividend: Registers 6-7 together; They have the number 148 Quotient: Register 7 = 12; Remainder: Register 6 = 4
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Machine Instructions - ED ED (Edit)
Machine Instruction Code Condition code DE (SS Instruction – L) Possible Interruptions 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED 0004,0005,0007 Syntax: [symbol] ED receiving_field,sending_field The 1st operand must have been prepared, prior to the edition, with the edition mask (e.g. move the edition mask to the 1st operand of edit instruction).
The sending field (2nd operand) is converted from packed decimal to zoned decimal, and stored into the receiving field (1st operand), ovelaying therefore the mask in the 1st operand.
Edition means the control and inclusion, if needed, of sign, visual characters (e.g. decimal point, 3 digit separators), and supression of non-significant zeros.
One may edit many packed fields in just one execution of ED instruction.
The (only) length specified is applied just to the 1st operand.
The 2nd operand must be in the decimal packed format. If any byte of the 2nd operand have in his left half the configurations A, B, C, D , E or F, it will occur a program interruption (code 0007).
Edit is done left to right.
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Machine Instructions - ED ED (Edit)
Machine Instruction Code Condition code DE (SS Instruction – L) 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED 0004,0005,0007 Possible Interruptions The bytes of mask may have: X'20‘ = digit selector; X’21’ = significance trigger, X’22’ ) = field separator , or any other contents (in this last case, it’s just a character to be inserted for visual pirposes) During edition, each character of the receiving field (mask – 1st operand) may have go into one of the 3 ways: Remain unchanged Substituted by an algarism of the sending field (converted to zoned format) Substituted by the leftmost character of the 1st operand mask (FILLING character).
To make the opetion from the 3 alternatives, CPU must analyse the mask, and consider the algarism being edited (is it zero or not?).
The process is as follows:
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Machine Instructions - ED ED (Edit)
Machine Instruction Code Condition code DE (SS Instruction – L) 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED 0004,0005,0007 Possible Interruptions The mask’s leftmost byte is analysed; if it is X’20’ or X’21’ it’s assigned as padding character and the edition starts with it.
Each one of the following bytes can have one of the following configurations:
Digit selector (X'20') or S-Trigger (X'21') or Field separator (X'22') or Any other
In the edition, when is detected a X’20’ or X’21’ in the 1st operand, instruction v erifies: The S-Trigger : significance indicator; it is a CPU flag; it can be ON or OFF.
The digit carresponding at the 2nd operand.
As a result of the verification, the configuration in the mask in the 1st operand will be substituted by the corresponding digit in the 2nd operand converted to zoned (if digit in the 1st operand is X’20’ or X’21’), or by the padding character (if not X’20’ nor X’21’).
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Machine Instructions - ED ED (Edit)
Machine Instruction Code Condition code DE (SS Instruction – L) 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED 0004,0005,0007 Possible Interruptions About the S-trigger: It is turned OFF (a) at the beginning of the ED execution or (b) after a X’22’ is found in the mask or (c) when a X’A’ or X’C’ or ‘E’ or ‘F’ is found in the right phalf of any byte of the 2nd operand (the packed field being edited) It is turned ON (a) after a X’21’ is detected in the mask or (b) when a ‘X20’ is detected in the mask WITH its corresponding digit in the sending field being NOT zero. For these 2 cases the right half of the byte in the sending field doesn’t have X’A’ or X’C’ or ‘E’ or ‘F’.
About Field separator (X'22') : it identifies fields in a multi-field edition. It is always substituted by the padding character Examples:
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Machine Instructions - ED ED (Edit)
Machine Instruction Code Condition code DE (SS Instruction – L) 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED 0004,0005,0007 Possible Interruptions Note that lowercase b means a (blank) space.
MVC WPAREA+5(10),MASK ED WPAREA+5(10),TOTAL ...
MASK DC X'4020204B2021206B2020' Before: After: TOTAL WPAREA+5(10) TOTAL WPAREA+5(10) 00.12.34.5C
40.20.20.4B.20.21.20.6B.20.20
b b b b 1 2 3 , 4 5 00.12.34.5C
40.40.40.40.F1.F2.F3.6B.F4.F5
b b b b 1 2 3 , 4 5 Other examples: ED ED ED 0(5,7),CPO ARIMP+17(8),ISDRT 4(12,9),2(10)
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Machine Instructions - EDMK EDMK (Edit and Mark)
Machine Instruction Code DF (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after EDMK Possible Interruptions 0004,0005,0007 This instruction is analog to the ED instruction.
It loads into register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the byte in the 1st operand who received the 1st non-zero digit.
Note that the address is not loaded when significance is forced (using X'21').
Example: EDMK ARIMP+5(10),TOTAL
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Machine Instructions - EX EX (Execute)
Machine Instruction Code Possible Interruptions 44 (RX Instruction) The setting (or not) depends on the executed instruction 0003,0005,0006 The 2nd operand specifies an instruction address.
The instruction it refers to is temporarily (internally in theCPU) modified according to the value of the register specified as 1st operand. With this tomporary change, it is executed.
The temporary changing is made applying a boolean OR (mask = rightmost byte of 1st operand register; object = 2nd byte of instruction addressed by 2nd operand).
Note that both EX operands remain unchanged.
If 1st operand is register 0, OR won’t be done, the instruction will be executed as it is in storage, with no change in the 2nd byte.
Example: L 5,=F'22' EX 5,MVC . . MVC MVC 0,(0,12),=CL256' ' Move will be executed with length 23
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Machine Instructions - IC IC (Insert Character)
Machine Instruction Code Condition code Possible Interruptions 43 (RX Instruction) Remains unchanged 0005 The contents of the byte specified in the 2nd operand is inserted into the rightmost byte of the register 1st operand; leftmost 3 bytes remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after IC 4,BYTE 00.00.45.67.8C 6B 00.00.45.67.6B 6B IC 8,=C'K' 00.00.00.11.1C D2 00.00.00.11.D2 D2 IC 11,=HL1'125' 00.00.00.00.00.12.7C 7D 00.00.00.00.02.5C.2C 7D
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Machine Instructions - ICM ICM (Insert Character under Mask)
Machine Instruction Code Condition code Possible BF (RS Instruction) 00 All inserted bits are 0, or mask is zero.
01 1st bit of inserted field is 1.
10 1st bit of inserted field is 0, and not all inserted bits are zero. 11 Condition code is not set as 11 after ICM.
Interruptions The format of this instruction is: 1st byte: X’BF’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register.
The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The storage bytes are inserted left to right into the bytes of 1st operand byteswhose bits in the mask are ON.
The remaining bytes of the register remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after ICM 5,B'1010',TWOBYTES 00.00.45.67 9A.BC
9A.00.BC.67 9A.BC 1st byte from TWOBYTES is inserted into 1st byte of register 5 and 2nd byte from TWOBYTES is inserted into the 3rd byte of register 5.
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Machine Instructions - IPM IPM (Insert Program Mask)
Machine Instruction Code Condition code Possible Interruptions B222 (RR InstructionE) Remains unchanged No interruptions occur Bits 16-23 (3rd byte) and 28-31 (4th byte right) of the instruction are ignored.
Condition code and program mask (from PSW) are copied into bits 2-3 (condition code) and bits 4-7 (program mask) into the corresponding bits of 1st operand register.
Bits 0-1 of the register are zeroed, and bits 8-31 remain unchanged.
Example: Suppose PSW with condition code ’01’ and program mask ‘1100’ register 8 before register 8 after IPM 8 C4.56.78.9A
1C.56.78.9A
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Machine Instructions - L L (Load)
Machine Instruction Code Condition code Possible Interruptions 58 (RX Instruction) Remains unchanged 0005 The contents of the field specified as 2nd operand (remains unchanged and) is loaded into the register 1st operand. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after L 7,FULL FE.DC.BA.98 00.01.00.00
00.01.00.00 00.01.00.00
L 14,SALVA 00.00.00.11 FF.FF.FF.FD
FF.FF.FF.FD FF.FF.FF.FD L 11,=F'125' 00.00.00.00 00.00.00.7D
00.00.00.7D 00.00.00.7D Other examples: L 8,0(10) L 8,0(,11) L 8,0(10,11) L 5,=F'200'
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Machine Instructions - LA LA (Load Address)
Machine Instruction Code Condition code 41 (RX Instruction) Remains unchanged Possible Interruptions No interruptions occur The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example: Suppose the registers with the values shown bellow (for symbol references register 3 is supposed to be the base register for the referenced fileds, and the displacements are just for example purposes; ) register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5,TABLE 01.12.34.56 41.50.3A.C2 00.0B.88.40 not used 00.0B.93.02 00.0B.88.40 not used LA 5,FLD+17 01.12.34.56 41.50.3F.03 00.A0.00.00 not used 00.A0.0F.03 00.A0.00.00 not used LA 5,FLD+17(9) 01.12.34.56 41.59.3F.03 00.A0.00.00 00.00.00.14 00.A0.0F.17 00.A0.00.00 00.00.00.14 LA 5,2(9,3) 01.12.34.56 41.59.30.02 00.A0.00.00 00.00.00.14
00.A0.00.16 00.A0.00.00 00.00.00.14 LA 5,200 01.23.45.67 41.50.00.C8 not used not used 00.00.00.C8 not used not used
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Machine Instructions - LA LA (Load Address)
Machine Instruction Code Condition code Possible Interruptions 41 (RX Instruction) Remains unchanged No interruptions occur The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example: Suppose the registers with the values shown bellow register 1st operand before register1st operand after machine instruction register 3 before register 9 before register 3 after register 9 after LA 5,4095 01.23.45.67 41.50.0F.FF not used not used 00.00.0F.FF not used not used LA 5,4095(3) 01.23.45.67 41.53.0F.FF 00.0A.80.00 not used 00.0A.8F.FF 00.0A.80.00 not used LA 5,4095(3,9) 01.23.45.67 41.53.9F.FF 00.0A.00.00 00.00.00.01
00.0A.10.00 00.0A.80.00 00.00.00.01
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Machine Instructions - LCR LCR (Load Complement Register)
Machine Instruction Code Condition code 13 (RR Instruction) 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0008 The binary number in the register 2nd operand is complemented and stored into the register 1st operand.
If the number is positive, it becomes negative; if it is negative it becomes positive.
Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LCR 4,5 00.00.00.00 FF.FF.FF.FC
00.00.00.04 FF.FF.FF.FC
LCR 4,4 00.00.00.02 00.00.00.02
FF.FF.FF.FE 00.00.00.02
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Machine Instructions - LH LH (Load Halfword)
Machine Instruction Code 48 (RX Instruction) Remains unchanged Possible Interruptions 0005 The 2-byte field specified as 2nd operand (remains unchanged and) is loaded into the rightmost 2 bytes of the register 1st operand. The leftmost bit of the storage field is used to fill the leftmost 2 bytes of the register 1st operand: it is expanded / copied to all bits of the first 2 bytes of the register.
Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after LH 5,FLD 00.00.00.00 8A.B4
FF.FF.8A.B4 8A.B4
LH 8,HWORD FF.FF.FF.FF
00.00.7A.B4
7A.B4
7A.B4
More examples: LH 7,HALF LH 8,0(10) LH 8,0(,11) LH 8,0(10,11) LH 8,=H'200'
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Machine Instructions - LM LM (Load Multiple)
Machine Instruction Code Possible Interruptions 98 (RX Instruction) Remains unchanged 0005 This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field.
It loads the contents of the storage field 2nd perand into the registers specified as a range by the 1st and 3rd operands.
The length of the field depends on how many registers must be loaded. To load 2 registers, the area must have 8 bytes; to load 3 registers, the area must have 12 bytes, and so on.
Example: LM 14,1,SAVEAREA Reg. 14 Reg.15 Reg.0 Reg.1
<----------><---------><----------><----------> |------- SAVEAREA ----------------------------| SAVEAREA = 16 bytes (bytes 0-3 = contents loaded into register 14; bytes 4-7 = contents loaded into register 15; bytes 8-11 = contents loaded into register 0; bytes 12-15 = contents loaded into register 1) Another example: LM 1,7,2(10)
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Machine Instructions - LNR LNR (Load Negative Register)
Machine Instruction Code 11 (RR Instruction) Condition code 00 Result = 0 01 Result < 0 10 Condition code is not set as 10 after LNR 11 Condition code is not set as 11 after LNR Possible Interruptions No interruptions occur The binary number of the 2nd operand is converted to negative and loaded into the register 1st operand.
Negative numbers and zero remain unchanged.
Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LNR 4,5 00.00.00.00 FF.FF.FF.FC
FF.FF.FF.FE FF.FF.FF.FC
LNR 4,5 00.00.00.02 00.00.00.02
FF.FF.FF.FE 00.00.00.02 LNR 4,8 00.00.00.02 00.00.00.00
00.00.00.00 00.00.00.00
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Machine Instructions - LPR LPR (Load Positive Register)
Machine Instruction Code 10 (RR Instruction) Condition code 00 Result = 0 01 Condition code is not set as 1 after LPR.
10 Result > 0 11 Overflow Possible Interruptions 0008 The binary number of the 2nd operand converted to positive and loaded into the register 1st operand. Positive numbers and zero remain unchanged.
The overflow occurs when the maximum negative value is converted to positive; in this case, the number remains unchanged. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LPR 4,5 00.00.00.00 FF.FF.FF.FC
00.00.00.04 FF.FF.FF.FC
LPR 4,5 00.00.00.02 00.00.00.02
00.00.00.02 00.00.00.02 LPR 4,8 00.00.00.FF 00.00.00.00
00.00.00.00 00.00.00.00
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Machine Instructions - LR LR (Load Register)
Machine Instruction Code Condition code 18 (RR Instruction) Remains unchanged Possible Interruptions No interruptions occur The contents of the register 2nd operand is loaded into the register 1st operand. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LR 4,5 00.00.00.00 FF.FF.FF.FC
FF.FF.FF.FC FF.FF.FF.FC
LR 4,5 00.00.12.34 00.00.00.02
00.00.00.02 00.00.00.02 LR 4,8 00.00.00.02 00.00.00.00
00.00.00.00 00.00.00.00
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Machine Instructions - LTR LTR (Load and Test Register)
Machine Instruction Code Condition code 12 (RR Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after LTR No interruptions occur The contents of register 2nd operand is loaded into the register 1st operand; the condition code is set according to the number loaded. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LTR 4,5 00.00.00.00 FF.FF.FF.FC
FF.FF.FF.FC FF.FF.FF.FC
LTR 4,5 00.00.12.34 00.00.00.02
00.00.00.02 00.00.00.02 LTR 4,8 00.00.00.02 00.00.00.00
00.00.00.00 00.00.00.00
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Machine Instructions - M M (Multiply)
Machine Instruction Code 5C (RX Instruction) Remains unchanged Possible Interruptions 0005,0006 This instruction multiplies two binary numbers.
Register 1st operand must be an even register. The odd register following it must contain the multiplicand.
The 2nd operand storage field must contain the multiplier.
The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Examples: Register 6 before Register 7 before Register 6 after Register 7 after 2nd operand before 2nd operand after M 6,FLDA [ Multiplicand: Register 7; Multiplier: FLDA; Result: Registers 6 and 7 together ] 00.00.00.00 00.00.00.0A 00.00.00.02
00.00.00.00 00.00.00.14 00.00.00.02
M 6,=F'256' Multiplicand: Register 7; Multiplier: 256; Result: Registers 6 and 7 together 00.00.00.00 00.00.04.00 00.00.00.FF
00.00.00.00 00.03.FC.00 00.00.00.FF
M 6,4(2,8) Multiplicand: Register 7; Multiplier address: Index reg 2 + Base reg 8 + X’4’; Result: Registers 6 and 7 together 00.00.00.00 00.00.04.00 00.00.01.0A
00.00.00.00 00.04.28.00 00.00.01.0A
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Machine Instructions - M M (Multiply)
Machine Instruction Code Possible Interruptions More examples: 5C (RX Instruction) Remains unchanged 0005,0006 M 6,4(2) Register 6 before Register 7 before Register 6 after Register 7 after 2nd operand before 2nd operand after Multiplicand: Register 7; Multiplier address: Reg index 2 [ + Reg base 0 ] + X’4’; Result: Registers 6 and 7 together 00.00.00.00 00.00.00.0C 00.00.00.02
00.00.00.00 00.00.00.18 00.00.00.02
M 6,FLD+4(1) Multiplicand: Reg 7; Multiplier address: Reg index 1 + Base register of FLD+4 + Displacement of FLD+4 + X’4’; Result: Registers 6 and 7 together 00.00.00.00 00.00.AA.AA 00.11.22.33
00.00.00.0B 6C.16.93.DE 00.11.22.33
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Machine Instructions - MC MC (Monitor Call)
Machine Instruction Code Condition code AF (SI Instruction) Remains unchanged Possible Interruptions 0006,0040 This instruction causes a program interruption if the bit that controls this event is ON in the control register.
The control register mask bits are the bits 16-31, end they correspond to the classes 0-15 respectively.
The leftmost 4 bits of 2nd operand (immediate) must be zero.
The rightmost 4 bits of 2nd operand specify abinary number indicating the desired interruption class.
If the corresponding bit in the control register 8is ON, interruption will occur.
The 2nd operand address is not a storage address; it is a code to be stored at the storage address X'000156'.
If the mask referred to the desired interruption is OFF in the control register 8, instruction processes as a NOP (no operation).
Example:
MC MONITCOD,7
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Machine Instructions - MH MH (Multiply Halfword)
Machine Instruction Code Possible Interruptions 4C (RX Instruction) Remains unchanged 0005 This instruction multiplies two binary numbers.
Register 1st operand must have the multiplicand. The 2nd operand 2-byte storage field must contain the multiplier.
The result is a 32-bit fixed-point binary number stored into the register 1st operand. Example: Note that if an overflow occurs (this event is NOT indicated in the condition code) the result sign may not be correct. If result = zero, sign is same as positive number.
Examples: MH 5,=H'4' Register 1st operand before 2nd operand before Register 1st operand after 2nd operand after [ Multiplicand: Register 5; Multiplier: literal 4; Result: Register 5 ] 00.00.00.0A 00.04
00.00.00.28 00.04
MH 5,=F'2' Multiplicand: Register 5; Multiplier: 0 [ left half of the fullword is taken as the halfword 2nd operand] ; Result: Register 5 00.00.04.00 00.00 [TAKE CARE! right half with 00.02 not taken! ] 00.00.00.00 00.00
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Machine Instructions - MP MP (Multiply Packed)
Machine Instruction Code FC (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0001,0004,0005,0006,0007 This instruction multiplies two decimal packed numbers, both in storage fields.
The result is stored in the 1st operand.
2nd operand can be up to 8 bytes.
2nd operand length must be less than the length of the 1st operand.
If 2nd operand length is greater than or equal to the length of the 1st operand, an interruption will occur (code 0006).
1st operand must have as many zero leftmost digits as many digits the 2nd operand has. If it doesn’t happen, interruption 0007 will occur. Example: MP FLDA,FLDB 1st operand before 2nd operand before 1st operand after 2nd operand after 00.09.99.9C 99.9C 99.89.00.1C 99.9C
00.19.99.9C 99.9C 00.19.99.9C 99.9C (Error! FLDA must have at least 3 leftmost digits with zero)
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Machine Instructions - MR MR (Multiply Register)
Machine Instruction Code Condition code 1C (RR Instruction) Remains unchanged Possible Interruptions 0006 This instruction multiplies two binary numbers, both in registers.
Register 1st operand must be an even register (its contents is not considered in the operation, unless it is [also] the multiplier). The odd register following it must contain the multiplicand.
The 2nd operand register must contain the multiplier.
The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Example: Register 6 before Register 7 before Register 6 after Register 7 after Register 9 before Register 9 after MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] 00.00.00.00 00.00.00.0A 00.00.00.02
00.00.00.00 00.00.00.14 00.00.00.02
MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] 00.00.00.00 99.AA.BB.CC 00.FF.FF.FF
00.99.AA.BB 32.55.44.34 00.FF.FF.FF
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Machine Instructions - MVC MVC (MoVe Character)
Machine Instruction Code Condition code D2 (SS Instruction - L) Remains unchanged Possible Interruptions 0004,0005 This instruction moves (copies) the contents of stotage field to another storage field.
The move is done left to right, each byte at a time. Example: before after FLDB C1.C2.C3 C1.C2.C3
MVC FLDA,FLDB FLDA C4.C5.C6 C1.C2.C3
The sending field is the 2nd operand and remains unchanged (unless part of it is at the same time the receiving field = overlapping). The receiving field is the 1st operand. The quantity of bytes moved is determined by the 1st operand length, and both operands are treated with this same length. Examples: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVC WA+5(3),WR+2 40.40.40 E5.C1.D3
E5.C1.D3 E5.C1.D3
MVC WOUT,WIN 00.00.00.00.00 00.00.00.00.1C
00.00.00.00.1C 00.00.00.00.1C
MVC NICKNAM,=C'SMAIL' C3.D9.E8.40.40 E2.D4.C1.C9.D3
E2.D4.C1.C9.D3 E2.D4.C1.C9.D3
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Machine Instructions - MVC MVC (MoVe Character)
Machine Instruction Code Condition code D2 (SS Instruction - L) Remains unchanged Possible Interruptions 0004,0005 More examples:
Move spaces using an auxiliary 5-byte field (a 5-byte literal) :
Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVC WA(5),=CL5' ' 5C.5C.5C.5C.5C 40.40.40.40.40
40.40.40.40.40 40.40.40.40.40
Alternatively, one may propagate spaces using na auxiliary 1-byte area (the literal) !
- The first MVC moves space to the leftmost byte of WA.
- The second one moves 4 bytes; remember that MVC operates one byte at a time.
- Follow the 4-byte move, one at a time: The 1st byte is moved to the 2nd; The 2nd to the 3rd; The 3rd byte to the 4th; The 4th byte to the 5th.
Initial MVC for the leftmost byte: MVC WA(1),=C' ' 5C.??.??.??.?? 40 before 40.??.??.??.?? 40 after
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Machine Instructions - MVC MVC (MoVe Character)
Machine Instruction Code Condition code D2 (SS Instruction - L) Remains unchanged Possible Interruptions Follow MVC one byte at a time : 0004,0005 Propagation from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th and from 4th to 5th MVC WA+1(4),WA
Or, better yet:
1st byte move: 40.??.??.??.?? 40.??.??.??.??
40.40.??.??.?? 40.40.??.??.??
1st move: 40.??.??.??.?? Before 40.40.??.??.?? After 2nd byte move : 40.40.??.??.?? 40.40.??.??.??
40.40.40.??.?? 40.40.40.??.??
2nd move: 40.40.??.??.?? Before 40.40.40.??.?? After 3rd byte move : 40.40.40.??.?? 40.40.40.??.??
40.40.40.40.?? 40.40.40.40.??
3rd move: 40.40.40.??.?? Before 40.40.40.40.?? After 4th byte move : 40.40.40.40.??
40.40.40.40.??
40.40.40.40.40 40.40.40.40.40
4th move: 40.40.40.40.?? Before 40.40.40.40.40 After
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Machine Instructions - MVCIN MVCIN (MoVe Character Inverted)
Machine Instruction Code Condition code E8 (SS Instruction – L) Remains unchanged Possible Interruptions 0001,0004,0005 This instruction moves (copies) the contents of the 2nd operand to the 1st operand (both are storage fields) in an inverted sequence.
Note that the 1st operand address is its leftmost byte, and the 2nd operand address is its rightmost byte.
Move is done each byte at a time.
From the sending field’s view its from right to left.
From the receiving field’s view its from left to right.
If occurs any overlay (superposition), results are unpredictable.
Example: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVCIN A(3),B+2 C4.C5.C6 C1.C2.C3
C3.C2.C1 C1.C2.C3
MVCIN A(5),BETA C4.C5.C6.C7.C8 C1.C2.C3.C4.C5
C5.C4.C3.C2.C1 C1.C2.C3.C4.C5
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Machine Instructions - MVCL MVCL (MoVe Character Long)
Machine Instruction Code 0E (RR Instruction) Condition code Possible Interruptions 00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Both 1st and 2nd operands must be even registers. They indicate a couple of (even-odd) registers, herein dubbed R1st, R1st+1, R2nd and R2nd+1 This instruction move a storage field (sending field) to another storage field (receiving field), each byte at a time, left to right.
Receiving field address must be in the 3 rightmost bytes of R1st.
Sending field address must be in the 3 rightmost bytes of R2nd.
Receiving field length must be in the 3 rightmost bytes of R1st+1.
Sending field length must be in the 3 rightmost bytes of R2nd+1.
The leftmost byte of R2nd+1 must contain the padding character.
The leftmost byte of R1st is ignored. Same happens with leftmost byte of R1st+1 and leftmost byte of R2nd.
Example: MVCL 2,8 See details on following slide.
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Machine Instructions - MVCL MVCL (MoVe Character Long)
Machine Instruction Code 0E (RR Instruction) Condition code Possible Interruptions 00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed L 2,=A(RECEIVE) L 3,=A(L’RECEIVE) L 8,=A(SENDING) L 9,=A(L’SENDING) ICM 9,B'1000',=C'*' MVCL 2,8 If sending field wraps from byte 16.777.215 to byte 0 (or not), move is executed this way: · The move is executed while the receiving field’s leftmost byte is the same or it’s at the left of the leftmost byte of the sending field OR the move is executed while the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field.
· The move is executed while the receiving field’s leftmost byte is the same or is at the left of the leftmost byte of the sending field AND the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field.
The (address of the) rightmost byte of the sending field is computed using the length of the receiving or sending field (the smaller).
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Machine Instructions - MVCL MVCL (MoVe Character Long)
Machine Instruction Code 0E (RR Instruction) Condition code Possible Interruptions 00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed After move: - The 3 rightmost bytes of R1st+1 (previously with the receiving field length) are set to zero (in fact, at each byte moved, it’s decremented by 1; , it is the amount of remaining bytes to move; at the end of operation remaining bytes to move = zero).
To the 3 rightmost bytes of R1st (previously with the receiving field address) is added the length originally specified in R1st+1 (in fact, at each byte moved, it’s incremented by 1 = next receiving byte address).
From the 3 rightmost bytes of R2nd+1 (originally with the sending field length) is subtracted the amount of moved bytes (in fact at each byte move it is decremented by 1, it is the amount of remaining bytes to move; at the end remaining bytes to move = zero) - To the 3 rightmost bytes of R2nd (previously with sending field address) it is added the number of bytes moved from sending to receiving field (in fact, at each byte moved, it’s incremented by 1 = next sending byte address) Leftmost R1st byte and leftmost R2nd byte are set to zero, even if move is not done.
- Leftmost R1st+1 byte and leftmost R2nd+1 byte remain unchanged.
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Machine Instructions - MVI MVI (MoVe Immediate)
Machine Instruction Code Condition code 92 (SI Instruction) Remains unchanged Possible Interruptions 0004,0005 This instruction moves (copies) a constant 1-byte storage field (2nd operand – immediate operand) to another storage 1-byte field.
2nd operand (mmediate operand) is the sending field and 1st operand is the receiving field.
Examples: MVI FLDA,C'*' or MVI FLDA,X'5C' or MVI FLDA,B'01011100' or MVI FLDA,92 FLDA before Immediate operand before FLDA after Immediate operand after 12 5C 5C 5C Other examples:
MVI WAREA+72,C'/' MVI 0(4),X'80'
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Machine Instructions - MVN MVN (MoVe Numerics)
Machine Instruction Code Condition code D1 (SS Instruction - L) Remains unchanged Possible Interruptions 0004,0005 This instruction is similar to MVC, but it moves onle the right half of the bytes.
Example: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVN FLDA,FLB 12.34.56 78.9A.BC
18.3A.5C 78.9A.BC
MVN TOT+4(1),=X'0C' 00.12.30.00.2F 0C 00.12.30.00.2C 0C
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Machine Instructions - MVO MVO (MoVe with Offset)
Machine Instruction Code Condition code F1 (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0004,0005 The MVO instruction moves the contents of the 2nd operand storage field to the 1st operand storage field, from righ to left, with displacement of half byte: the right half of the receveing field rightmost byte remains unchanged. The right half of the rightmost byte of sending field is sent to the left half of the rightmost byte of receiving field. And so on.
If 1st operand isn’t large enough to receive all digits sent from the 1st operand, the leftmost half-bytes are truncated.
If 1st operand is larger than enough to receive all digits sent from the 1st operand, the leftmost half-bytes are filled with X’0’.
Examples: MVO RECFLD,SENFLD SENFLD Before
00.00.12.00
RECFLD Before
00.00.00.0C
SENFLD After RECFLD After
00.00.12.00
00.01.20.0C
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Machine Instructions - MVO MVO (MoVe with Offset)
Machine Instruction Code Condition code F1 (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0004,0005 MVO CPOA,CPOB Before After 1º Case CPOB 12.34.56 12.34.56
CPOA 78.9A 45.6A
2º Case CPOB AB.72 AB.72
CPOA 4A.5C.B9.FC 00.0A.B7.2C
Other examples: MVO ARCALC(5),ARCALC(4) MVO 0(4,7),ARCALC MVO AREA,2(5,8) MVO 2(7,13),19(5,15)
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Machine Instructions - MVZ MVZ (MoVe Zones)
Machine Instruction Code Condition code D3 (SS Instruction – L) Remains unchanged Possible Interruptions 0004,0005 The MVZ instruction is similar to the MVC, but it moves onle the left half of the bytes. Examples: Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVZ FLDA,FLB 12.34.56 78.9A.BC
72.94.B6 78.9A.BC
MVZ TOT,=4C'0' 01.02.03.04.C5 F0.F0.F0.F0.F0
F1.F2.F3.F4.F5 F0.F0.F0.F0.F0
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Machine Instructions - N N ([boolean] aNd)
Machine Instruction Code Condition code Possible Interruptions 54 (RX Instruction) 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after N 11 Condition code is not set as 11 after N 0005 This instruction executes a boolean AND between a register (1st operand) and a 4-byte storage field (2nd operand).
Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: N 13,FIELDX Before After Register 13 B4.EF.2F.A8 00.00.00.A8
FIELDX 00.00.00.FF 00.00.00.FF
Other examples: N 11,=F'15' N 3,0(4) N 3,0(,4) N 3,0(8,4)
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Machine Instructions - NC NC ([boolean] aNd Character)
Machine Instruction Code Condition code D4 (SS Instruction – L) Possible Interruptions 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NC 11 Condition code is not set as 11 after NC 0004, 0005 This instruction executes a boolean AND between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NC FLDA,FLDB Before After FLDA EF.2F.A8 00.00.A8
FLDB 00.00.FF 00.00.FF
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Machine Instructions - NI NI ([boolean] aNd [with] Immediate [operand])
Machine Instruction Code 94 (SI Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NI 11 Condition code is not set as 11 after NI Possible Interruptions 0004, 0005 This instruction executes a boolean AND between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NI BYTE,X'0F' Before After BYTE B4 04 Immediate Op. 0F 0F
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Machine Instructions - NR NR ([boolean] aNd Register)
Machine Instruction Code Condition code 14 (RR Instruction) Possible Interruptions 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NR 11 Condition code is not set as 11 after NR No interruptions occur This instruction executes a boolean AND between 2 registers.
Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NR 5,8 Before After Register 5 B4.EF.2F.A8 00.00.00.A8
Register 8 00.00.00.FF 00.00.00.FF
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Machine Instructions - O O ([boolean] Or)
Machine Instruction Code Condition code Possible Interruptions 56 (RX Instruction) 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after O 11 Condition code is not set as 11 after O 0005 This instruction executes a boolean OR between a register (1st operand) and a 4-byte storage field (2nd operand).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: O 13,FIELDF Before After Register 13 B4.EF.2F.A8 B4.EF.2F.FF
FIELDF 00.00.00.FF 00.00.00.FF
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Machine Instructions - OC OC ([boolean] Or Character)
Machine Instruction Code Condition code D6 (SS Instruction – L) Possible Interruptions 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OC 11 Condition code is not set as 11 after OC 0004, 0005 This instruction executes a boolean OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.FF
FLDB 00.00.FF 00.00.FF
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Machine Instructions - OI OI ([boolean] Or [with] Immediate [operand])
Machine Instruction Code Condition code 96 (SI Instruction) Possible Interruptions 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OI 11 Condition code is not set as 11 after OI 0004, 0005 This instruction executes a boolean OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OI BYTE,X'0F' Before After BYTE B4 BF Immediate Operand 0F 0F
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Machine Instructions - OR OR ([boolean] Or Register)
Machine Instruction Code Condition code 16 (RR Instruction) 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OR 11 Condition code is not set as 11 after OR Possible Interruptions No interruptions occur This instruction executes a boolean OR between 2 registers.
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OR 5,8 Before After Reg. 5 B4.EF.2F.A8 B4.EF.2F.FF
Reg. 8 00.00.00.FF 00.00.00.FF
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Machine Instructions - PACK PACK
Machine Instruction Code Condition code F2 (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0004,0005 The PACK instruction moves a storage zoned field to a storage packed field. The intended function is to convert a numeric field from zoned format to packed format. NO validation is done in the sending field; if its contents is not a valid decimal zoned number, the operation flows normally.
1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left.
The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field.
After that, each right half byte of the sending field is sent to a half of the receiving field. 2nd operand remains unchanged.
If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated.
If the receiving field is greater than needed to fit all digits from sending field, the remaining left digits are filled with X’0’.
Example: PACK FLDA,FLDB Before After FLDB FLDA F1.F2.F3.F4
00.B7.2A
F1.F2.F3.F4
01.23.4F
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Machine Instructions - PACK PACK
Machine Instruction Code Condition code F2 (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions PACK 2ºcase FLDB FLDA 3ºcase FLDB FLDA 0004,0005 FLDA,FLDB F1.F2.F3.F4
C9.4A
9A.48.F9.DB
19.B7.DF
F1.F2.F3.F4
23.4F
9A.48.F9.DB
0A.89.BD
Note the 3rd case. The sending field is not validated about being zoned. The receiving field may not become a valid decimal packed field.
More examples: PACK VALUE,READAREA+5(9) PACK PACK HOWMUCH+2(7),2(8,5) 0(10,2),AREA PACK PACK PACK 2(5,7),2(3,8) DOUBLE,DOUBLE BYTE,BYTE
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Machine Instructions - S S (Subtract)
Machine Instruction Code Condition code 5B (RX Instruction) 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0005,0008 Possible Interruptions Instruction S subtracts algebraically the binary number in the 4-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register.
Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after S 5,=F'259' 00.00.BF.D2 00.00.01.03 00.00.BE.CF 00.00.01.03
S 7,FULL 00.00.00.0D 00.00.01.03
FF.FF.FF.0A 00.00.01.03
S 7,4(2,8) 07.FF.FF.FE 00.00.00.01
07.FF.FF.FD 00.00.00.01
S 7,4(2) 07.FF.FF.FF 00.00.00.02
07.FF.FF.FD 00.00.00.02
S 7,4(,8) 00.00.00.00 FF.FF.FF.FF
00.00.00.01 FF.FF.FF.FF
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Machine Instructions - SH SH (Subtract Halfword)
Machine Instruction Code 4B (RX Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0005,0008 Instruction SH subtracts algebraically the binary number in the 2-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SH 5,=H'259' 00.00.2B.C4
01.03
00.00.2A.C1 01.03
SH 5,HALF 00.00.00.0D 01.0D
FF.FF.FF.00 01.0D SH 5,4(2,8) 11.11.11.11 (decimal 286331153) 11.11.88.89 (decimal 286361737) SH 5,4(2) 11.11.11.11 (decimal 286331153) 11.10.98.89 (decimal 286300297) 88.88 (decimal –30584) 88.88
78.88 78.88
(decimal +30856)
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Machine Instructions - SL SL (Subtract Logical)
Machine Instruction Code Condition code 5F (RX Instruction) 00 Condition code is not set as 00 after SL 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions 0005 Instruction S subtracts logically the binary number in the 4-byte storage field 2nd operand from the binary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SL 5,=F'259' 00.00.BF.D2 00.00.01.03 00.00.BE.CF 00.00.01.03
SL 7,FULL 00.00.00.0D 00.00.00.03
00.00.00.0A 00.00.00.03
SL 7,4(2,8) 07.FF.FF.FE 00.00.00.01
07.FF.FF.FD 00.00.00.01
SL 7,4(2) 07.FF.FF.FF 00.00.00.02
07.FF.FF.FD 00.00.00.02
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Machine Instructions - SLA SLA (Shift Left Algebraic)
Machine Instruction Code Condition code 8B (RS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow No interruptions occur This instruction shifts algebraically, to the left, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted.
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SLA 5,3 Register 5 before Shift FF.80.9A.00
Register 5 after Shift FC.04.D0.00
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Machine Instructions SLDA SLDA (Shift Left Double Algebraic)
Machine Instruction Code Condition code 8F (RS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0004, 0008 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number).
This instruction shifts algebraically, to the left, the bits of the number inside the 2 registers (both treated as only onr number).
The sign bit remains unchanged, and the other 63 bits are shifted.
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDA Registers 8 and 9 before Shift 00.00.00.00 FF.80.9A.00
8,3 Registers 8 and 9 after Shift 00.00.00.07 FC.04.D0.00
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Machine Instructions - SLDL SLDL (Shift Left Double Logical)
Machine Instruction Code 8D (RS Instruction) Remains unchanged Possible Interruptions 0006 The register specified as 1st operand indicates a pair of registers (R1st and R1st+1), taken as a number with 64-bit.
This instruction shifts logically, to the left, the bits of the number inside the 2 registers (both treated as only onr number).
All 64 bits are shifted (including sign bit).
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDL 8,4 Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A.78.90 8 9 Registers 8 and 9 after Shift 2F.E3.D4.C5 B6.A7.89.00 8 9
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Machine Instructions - SLL SLL (Shift Left Logical)
Machine Instruction Code 89 (RS Instruction) Remains unchanged Possible Interruptions No interruptions occur The register specified as 1st operand indicates a register, taken as a 32-bit number.
This instruction shifts logically, to the left, the bits of the number inside the register.
All 32 bits are shifted (including sign bit).
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SLL 5,2 Register 5 before Shift B9.4F.FF.FF Register 5 after Shift E5.3F.FF.FC
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Machine Instructions - SLR SLR (Subtract Logical Register)
Machine Instruction Code 1F (RR Instruction) Condition code 00 Condition code is not set as 00 after SLR 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions No interruptions occur Instruction SLR subtracts logically the binary number in the register 2nd operand from the binary number in the register 1st operand.
Result is stored into 1st operand register. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SLR SLR 7,12 10,11 00.B0.C4.E2
00.B0.C4.E1
80.00.00.00
00.00.00.01
00.00.00.01
00.00.00.01
7F.FF.FF.FF
00.00.00.01
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Machine Instructions - SP SP (Subtract Packed)
Machine Instruction Code Condition code FB (SS Instruction – L1 e L2) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0001,0004,0005,0007,000A This instruction subtracts the contents of the 2nd operand from the contents of the 1st operand.
Both must be storage fields in the decimal packed format.
Result is stored into 1st operand field.
Examples: SP FLDA,FLDB Before After FLDB 98.7C 98.7C
FLDA 12.34.5C 11.35.8C
More examples: SP VALUE,VALUE SP TOTAL,=P'1' SP AE+5(8),AE+15(3) SP 0(2,7),4(1,8)
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Machine Instructions - SPM SPM (Set Program Mask)
Machine Instruction Code Condition code Possible Interruptions 04 (RR Instruction) Is set with the contents of bits 2 and 3 of register 1st operand No interruptions occur This is RR instruction. Its bits 12-15 are not considered.
The contents of 1st operand register is used to take the values of condition code and program mask to store them into PSW.
The value of bits 2-3 are set to the condition code.
The value of bits 4,5,6 and 7 are set to the PSW program mask.
The bits 0-1 and 8-31 are ignored.
Example: SPM 8
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Machine Instructions - SR SR (Subtract Register)
Machine Instruction Code Condition code 1B (RR Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0008 This instruction subtracts the contents of the register 2nd operand from the contents of the register 1st operand. Result is stored into register 1st operand.
Then: Minuend : 1st operand ; Subtrahend : 2nd operand ; Result : 1st operand Examples: Suppose the operands with the length and values shown in the “before” line Register 1st operand before Register 2nd operand before Register 1st operand after Register 2nd operand after SR 7,8 00.00.FF.FF
00.00.00.01
00.00.FF.FE
00.00.00.01
SR 2,2 00.00.FF.FF 00.00.FF.FF
00.00.00.00 00.00.00.00
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Machine Instructions - SRA SRA (Shift Right Algebraic)
Machine Instruction Code Condition code 8A (RS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after SRA No interruptions occur This instruction shifts algebraically, to the right, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted.
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SRA 5,3 Register 5 before Shift FF.80.0A.00
Register 5 after Shift 8F.F0.01.40
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Machine Instructions - SRDA SRDA (Shift Right Double Algebraic)
Machine Instruction Code Condition code 8E (RS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after SRDA 0006 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number).
This instruction shifts algebraically, to the right, the bits of the number inside the 2 registers (both treated as only one number).
The sign bit remains unchanged, and the other 63 bits are shifted.
The “new” bits to the left are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDA 8,4 Registers 8 and 9 before Shift 04.20.08.91 C4.00.02.FF
Registers 8 and 9 after Shift 00.42.00.89 1C.40.00.2F
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Machine Instructions - SRDL SRDL (Shift Right Double Logical)
Machine Instruction Code 8C (RS Instruction) Remains unchanged Possible Interruptions 0006 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit.
This instruction shifts logically, to the right, the bits of the number inside the 2 registers (both treated as only onr number).
All 64 bits are shifted (including sign bit).
The “new” bits to the left are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDL 8,4 Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A.78.90 8 9 Registers 8 and 9 after Shift 01.2F.E3.D4 C5.B6.A7.89 8 9
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Machine Instructions - SRL SRL (Shift Right Logical)
Machine Instruction Code Condition code 88 (RS Instruction) Remains unchanged Possible Interruptions No interruptions occur The register specified as 1st operand indicates a register, taken as a 32-bit number.
This instruction shifts logically, to the right, the bits of the number inside the register.
All 32 bits are shifted (including sign bit).
The “new” bits to the left are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SRL 5,2 Register 5 before Shift B9.4F.FF.FF Register 5 after Shift 2E.53.FF.FF
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Machine Instructions - SRP SRP (Shift and Round Packed)
Machine Instruction Code Condition code F0 (SS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0001,0004,0005,0007,000A This is a SS instruction, and its format is the following: 1 byte = operation code 1/2 byte = L1 = 1st operand length - 1 1/2 byte = I3 = 3rd operand (immediate operand) 2 bytes = 1st operand base+displacement address 2 bytes = 2nd operand base+displacement address The 1st operand is a decimal packed storage field; it is shifted based upon the information provided by the 2nd operand: the sense of shift and the amount of digits to be shifted.
If shift is to be done rightwards the number is rounded accordingly 3rd operand.
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Machine Instructions - SRP SRP (Shift and Round Packed)
Machine Instruction Code Condition code F0 (SS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0001,0004,0005,0007,000A The 6 rightmost bits of the number computed as the “address” of 2nd operand are analysed this way: Leftmost bit indicates the sense of the shift: OFF means shift leftwards; ON means rightwards.
The number composed by the remaining 5 bits indicates the amount of digits to be shifted (if shift rightwards, this number is negative).
The round is done by adding the number specified in the 3rd operand to the last shifted digit and, if it is 1, it is added to the number-result after shift. See the following examples:
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Machine Instructions - SRP SRP (Shift and Round Packed)
Machine Instruction Code Condition code F0 (SS Instruction) Possible Interruptions 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow 0001,0004,0005,0007,000A SRP SRP TOTAL,61,5 TOTAL Before 12.34.56.78.9C
TOTAL After (shifts 3 digits to the right) 00.01.23.45.7C
TOTAL,3,0 TOTAL Before TOTAL After (shifts 3 digits to the left) 12.34.56.78.9C
45.67.89.00.0C
These rules make it easier to specify shift sense and amount of digits: Shift leftwards = specify directly the amount of digits SRP TOTAL,3,5 Specify amount in the 2nd operand = shifts “amount” digits to the left (in the example = 3) Shift rightwards = specify (64 – amount of digits) SRP TOTAL,64-3,5 Specify [64-amount] in the 2nd operand = shifts “amount” digits to the right (In the example = 3)
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Machine Instructions - ST ST (Store [from register to storage])
Machine Instruction Code Condition code 50 (RX Instruction) Remains unchanged Possible Interruptions 0004,0005 The register 1st operand (remain unchanged and) is stored into the 2nd operand 4-byte storage field.
Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after ST 7,FULL FE.DC.BA.98 00.01.00.00
FE.DC.BA.98 FE.DC.BA.98
ST 14,SAVE 00.00.00.11 FF.FF.FF.FD
00.00.00.11 00.00.00.11 Other examples: ST 14,FULL+4 ST 14,0(2) ST 14,0(,8)
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Machine Instructions - STC STC (STore Character)
Machine Instruction Code Condition code 42 (RX Instruction) Remains unchanged Possible Interruptions 0004,0005 The rightmost byte of register 1st operand (remain unchanged and) is stored into the 2nd operand 1-byte storage field. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STC 7,BYTE FE.DC.BA.98 00 FE.DC.BA.98 98 STC 14,0(5) 00.00.00.11 FF 00.00.00.11 11
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Machine Instructions - STCK STCK (STore ClocK)
Machine Instruction Code Condition code B205 (Instrução S) Possible Interruptions 00 Clock status allows set 01 Clock status does not allow set 10 Clock status is error 11 Condition code is not set as 11 after STCK 0004 TOD clock contents is stored into the 8-byte storage field specified in the 2nd operand.
Clock must be is set, stop or no-set state.
The rightmost bytes are set to zero.
If TOD clock is in error state, contents stored is unpredictable.
If TOD clock is not operational, all bytes are set to zero.
Example: STCK DW
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Machine Instructions - STCM STCM (STore Character under Mask)
Machine Instruction Code Condition code BE (RS Instruction) Remains unchanged Possible Interruptions 0004,0005 The format of this instruction is: 1st byte: X’BE’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register.
The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The register 1st operand bytes corresponding to the ON bits of the mask are stored into the 2nd operand storage bytes (taken as a contiguous field).
1st operand remains unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STCM 5,B’1010’,TWOBYTES 00.00.45.67 9A.BC
00.00.45.67 00.45 1st byte of register 5 is stored into byte TWOBYTES and 3rd byte of register 5 is stored into byte TWOBYTES+1
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Machine Instructions - STH STH (STore Halfword)
Machine Instruction Code Condition code 40 (RX Instruction) Remains unchanged Possible Interruptions 0004,0005 The rightmost 2 bytes of register 1st operand (remain unchanged and) are stored into the 2nd operand 2-byte storage field. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STH 5,FLD 00.00.00.0A 8A.B4
STH 8,HWORD 00.00.00.0A 00.0A
FF.FF.FF.FF
FF.FF
FF.FF.FF.FF
FF.FF
Other examples: STH 14,SAVE+18 STH 14,0(2) STH 14,0(,8) STH 14,0(2,8) STH 0,FLD
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Machine Instructions - STM STM (STore Multiple)
Machine Instruction Code Possible Interruptions 90 (RX Instruction) Remains unchanged 0004,0005 This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field.
It stores the contents of the registers specified as a range by the 1st and 3rd operands into the storage field 2nd perand.
The length of the field depends on how many registers must be stored. To store 2 registers, the area must have 8 bytes; to store 3 registers, the area must have 12 bytes, and so on.
Example: STM 14,1,SAVE SAVE = 16 bytes (bytes 0-3 = contents of register 14; bytes 4-7 = contents of register ; bytes 8-11 = contents of register 0; bytes 12-15 = contents of register 1) |------- SAVE --------------------------------| <----------><---------><----------><----------> Reg. 14 Reg.15 Reg.0 Reg.1
Another example: STM 1,7,2(10)
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Machine Instructions - SVC SVC (SuperVisor Call)
Machine Instruction Code 0A (RR Instruction) Condition code (Remains unchanged in the old PSW) Possible Interruptions No interruptions occur The format of this instruction is: 1st byte = operation code; 2nd byte = SVC number This instruction causes a program interruption; this interruption demands CPU to execute a call to the operating system (supervisor) to execute some function.
The code (2nd byte – from 0 to 255 – X’00’ up to X’FF’) determines the function to be executed by supervisor .
Examples: SVC SVC 0 7 Some MVS-z/OS SVCs: X'00' (000) = EXCP/XDAP X'13' (019) = OPEN X'01' (001) = WAIT/WAITR/PRTOV X'14' (020) = CLOSE X'02' (002) = POST X'23' (035) = WTO/WTOR X'04' (004) = GETMAIN X'24' (036) = WTL X'05' (005) = FREEMAIN X'5D' (093) = TGET/TPUT X'0B' (011) = TIME X'63' (099) = DYNALLOC X'0D' (013) = ABEND X'6B' (107) = MODESET
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Machine Instructions - TM TM (Test under Mask)
Machine Instruction Code Condition code 91 (SI Instruction) Possible Interruptions 00 All bits tested are OFF, or mask is zero 01 Some bits tested are ON and others are OFF 10 Condition code is not set as 10 after TM 11 All bits tested are ON 0005 This instruction tests the bits of the 1-byte storage field specified by the 1st operand, using the mask specified in the 2nd operand (self-defining term).
The mask indicates whose bits must be tested. The ON bits in the mask indicate the bits of the stoprage byte to be tested.
Test means: is the bit(s) ON or OFF?
To reflect the result, condition code is set.
Example: TM BYTE,X'9C' Bits 0, 3, 4 and 5 of BYTE are tested More examples: TM KEYAB,B'10000001' Bits 0, and 7 of KEYAB are tested TM 0(4),240 Bits 4,5,6 and 7 of [base register 4 + displacement X’0’] are tested TM 2(8),X'80' Bit 0 [base register 8 + displacement X’2’] is tested
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Machine Instructions - TR TR (TRanslate)
Machine Instruction Code Possible Interruptions DC (SS Instruction – L) Remains unchanged 0004,0005 TR instruction moves the contents of 2nd operand to the 1st operand, according to the 1st operand contents.
The move is done left to right, each byte at a time, this way: The contents of each byte of the 1st operand is added (internally) to the 2nd operand address; The byte at the resulting address is moved (copied) to the byte of the 1st operand.
2nd operand remains unchanged Example: TR ACSD,TABLE Before ACSD 02.00.08.FF.05
TABLE C1.48.B9.D7.A1.C3.D9.5C.4B ........1A 256 bytes After ACSD B9.C1.4B.1A.C3
TABLE Remains unchanged More examples : TR 0(5,7),0(10) TR WAREA+7(10),TABASTER TR 2(5,124),FIELD
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Machine Instructions - TR TR (TRanslate)
Machine Instruction Code Possible Interruptions DC (SS Instruction – L) Remains unchanged 0004,0005 More examples : To translate uppercase EBCDIC letters into lowercase EBCDIC letters; invalid letters are converted to EBCDIC spaces CONVTB1 DC 256C ' ' 256 EBCDIC spaces ORG CONVTB1+C'A' “Return” to Uppercase A DC C'abcdefghi' Substitute original spaces by lowwercase ORG CONVTB1+C'J' “Return” to Uppercase J DC C'jklmnopqr' Substitute original spaces by lowwercase ORG CONVTB1+C'S' “Return” to Uppercase S DC C'stuvwxyz' Substitute original spaces by lowwercase ORG , Return to byte folowing CONVTB1 To translate uppercase EBCDIC letters into uppercase ASCII letters; invalid letters are converted to ASCII spaces CONVTB2 DC 256X'20' 256 ASCII spaces ORG CONVTB2+C'A' “Return” to Uppercase A DC X'414243444546474849' Substitute EBCDIC value by ASCII value ORG CONVTB1+C'J' “Return” to Uppercase J DC X'4A4B4C4D4E4F505152' Substitute EBCDIC value by ASCII value ORG CONVTB1+C'S' “Return” to Uppercase S DC X'535455565758595A' Substitute EBCDIC value by ASCII value ORG , Return to byte folowing CONVTB2
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Machine Instructions - TR TR (TRanslate)
Machine Instruction Code Possible Interruptions DC (SS Instruction – L) Remains unchanged 0004,0005 More examples : To translate uppercase ASCII letters into uppercase EBCDIC letters; invalid “letters” are converted to EBCDIC spaces CONVTB3 DC 256X ' 40 ' 256 EBCDIC spaces ORG CONVTB2+X ' 41 ' Volta para A maiusculo ASCII DC C ' ABCDEFGHIJKLMNOPQRSTUVWXYZ ' Substitui ASCII value by EBCDIC ORG , Return to byte CONVTB3+256
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Machine Instructions - TRT TRT (TRanslate and Test)
Machine Instruction Code Condition code DD (SS Instruction – L) Possible Interruptions 00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested.
10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT This instruction tests bytes of the 2nd operand, verifying their status (X’00’ or not).
The 1st tested byte NOT in X’00’ ends the instruction execution.
1st operand indicates the 2nd operand bytes to be tested: TRT adds the contents of each byte of the 1st operand to the 2nd operand address (same as TR instruction); the byte at the resulting address is tested with X’00’.
When a non-X’00’ byte is detected instruction stores in the register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the 1st operand byte that lead to the 2nd operand non-X’00’ byte; it also stores in register 2 (bits 24-31; bits 0-23 remain unchanged) the contents of the 2nd operand byte not in X’00’.
This instruction is generally used to:
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Machine Instructions - TRT TRT (TRanslate and Test)
Machine Instruction Code Condition code DD (SS Instruction – L) 00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested.
10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions a) Validate a decimal zoned field (1st operand – only valid digits): TRT CART+9(6),TABNUM BZ NUMÉRIC .
.
.
TABNUM DC 240X'FF',10X'00',6X'FF' b) Validate an alphanumeric field (1st operand – only uppercase letters and spaces) TRT CART+9(6),TABALFAB BZ FABETIC .
.
TABALFA DC CL256X'FF' ORG TABALFAB+C' ' DC X'00' ORG TABALFAB+C'A' DC 9X'00' ORG TABALFAB+C'J' DC 9X'00' ORG TABALFAB+C'S' DC 8X'00' ORG
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Machine Instructions - TRT TRT (TRanslate and Test)
Machine Instruction Code Condition code DD (SS Instruction – L) Possible Interruptions 00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested.
10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT c) Find a character (* in the example) in a string of characters (e.g. for parsing).
TABASTER TRT BZ register 1 has the byte with * .
.
.
0(80,7),TABASTER NOTASTER DC ORG DC ORG 256X'00' TABASTER+C'*' X'FF'
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Machine Instructions - TS TS (Test ans Set)
Machine Instruction Code Condition code 93 (Instrução S) Possible Interruptions 00 Leftmost bit OFF 01 Leftmost bit ON 10 Condition code is not set as 10 after TS 11 Condition code is not set as 11 after TS 0004,0005 Second byte of instruction is ignored.
The leftmost bit of the (only) operand is tested (ON or OFF).
After the test all bits of the byte are set to 1 (ON).
Condition code is set according to the result of the test.
Example: TS BYTE
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Machine Instructions - UNPK UNPK (UNPacK)
Machine Instruction Code F3 (SS Instruction – L1 e L2) Remains unchanged Possible Interruptions 0004,0005 The UNPK instruction moves a storage packed field to a storage zoned field. The intended function is to convert a numeric field from packed format to zoned format. NO validation is done in the sending field; if its contents is not a valid decimal packed number, the operation flows normally.
1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left.
The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field.
After that, each half byte of the sending field is sent to a right half of a receiving field byte, and the left half is set to X’F’. 2nd operand remains unchanged.
If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated.
If the receiving field is greater than needed to fit all digits from sending field, the remaining left bytes are filled with X’F0’.
Example: UNPK FLDA,FLDB Before After FLDB 12.34.5C 12.34.5C
FLDA 92.B8.4C.D0 F2.F3.F4.C5
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Machine Instructions - UNPK UNPK (UNPacK)
Machine Instruction Code Possible Interruptions More examples: UNPK FLDB FLDA F3 (SS Instruction – L1 e L2) Remains unchanged 0004,0005 FLDA,FLDB Before 12.3C
92.B8.4C.D0
After 12.3C
F0.F1.F2.C3
UNPK UNPK UNPK UNPK WRITAREA+5(12),TOTLIQ AX2,2(3,7) 17(10,8),T4B2F+3(5) 2(13,10),0(5,3)
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Machine Instructions - X X ([boolean] eXclusive or Character)
Machine Instruction Code Condition code 57 (RX Instruction) 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after X 11 Condition code is not set as 11 after X Possible Interruptions 0005 This instruction executes a boolean Exclusive OR between a register (1st operand) and a 4-byte storage field (2nd operand).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: X 13,FIELDF Before After Register 13 B4.EF.2F.A8 B4.EF.2F.57
FIELDF 00.00.00.FF 00.00.00.FF
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Machine Instructions - XC XC ([boolean] eXclusive or Character)
Machine Instruction Code D7 (SS Instruction – L) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after XC 11 Condition code is not set as 11 after XC Possible Interruptions 0004, 0005 This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: XC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.57
FLDB 00.00.00 00.00.FF
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Machine Instructions - XI XI ([boolean] eXclusive or [with] Immediate [operand])
Machine Instruction Code Condition code 97 (SI Instruction) 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OI 11 Condition code is not set as 11 after OI Possible Interruptions 0004, 0005 This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: NI BYE,X’0F’ before After BYTE B4 BB Immediate operand 0F 0F
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Machine Instructions - XR XR ([boolean] eXclusive or Register)
Machine Instruction Code Condition code 17 (RR Instruction) 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after XR 11 Condition code is not set as 11 after XR Possible Interruptions No interruptions occur This instruction executes a boolean EXCLUSIVE OR between 2 registers.
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: XR 5,8 Before After Register 5 B4.EF.2F.A8 B4.EF.2F.57
Register 8 00.00.00.FF 00.00.00.FF
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Machine Instructions - ZAP ZAP (Zero and Add Packed)
Machine Instruction Code Condition code F8 (SS Instruction – L1 e L2) Possible Interruptions 00 Sender field = 0 01 Sender field < 0 10 Sender field > 0 11 Overflow 0001,0004,0005,0007,000A 2nd operand must be a packeddecimal storage field.
This instruction zeroes (decimal packed zero) the 1st operand and add the value of the 2st operand to the 1st. 2nd operand remains unchanged.
Note that this process is done internally (in the CPU).
That’s the reason one can specify the same storage field as 1st and also as 2nd operand; this is often used to test the number (positive, negative or zero) because ZAP sets the condition code When we do ZAP FLD,FLD before zeroing FLD, its contents are internally saved. After being zeroed, when add is done the original contents is available; then it returns to the original value.
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Machine Instructions - ZAP ZAP (Zero and Add Packed)
Machine Instruction Code Condition code F8 (SS Instruction – L1 e L2) Possible Interruptions 00 Se o campo movido = 0 01 Se o campo movido < 0 10 Se o campo movido > 0 11 Overflow 0001,0004,0005,0007,000A ZAP CPOA,CPOB Before After 1st Case CPOB 12.34.5C 12.34.5C
CPOA B4.F8 34.5C
2nd Case CPOB 12.3C 12.3C
CPOA 07.B8.92 00.12.3C
More examples: ZAP TOTAL,=P'0' ZAP CONTLIN,=P'2'
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Macro Instructions MACRO INSTRUCTIONS
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Macro Instructions MACRO INSTRUCTIONS
Sorry... It’s not in the scope of this course...
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Appendix - Links LINKS z/Architecture http://publibz.boulder.ibm.com/epubs/pdf/dz9zr006.pdf
ESA Enterprise Systems Architecture / XC Extended Configuration (para z/VM) http://publib.boulder.ibm.com/infocenter/zvm/v5r3/index.jsp?topic=/com.ibm.zvm.v53.hcpb6/abstract.htm
High Level Assembler http://publib.boulder.ibm.com/infocenter/ratdevz/v7r5/topic/com.ibm.ent.asm.zos.doc/topics/fn1lrmst02.htm#wq2
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Appendix – Instructions by operation code Some instructions (ordered by operation code)
Mnemonic Code Type BALR 05 RR BCTR 06 RR BCR 07 RR SVC 0A RR BSM 0B RR BASSM 0C RR BASR 0D RR MVCL 0E RR CLCL 0F RR LPR 10 RR LNR 11 RR LTR 12 RR LCR 13 RR NR 14 RR CLR 15 RR OR 16 RR XR 17 RR LR 18 RR CR 19 RR AR 1A RR
Mnemonic Code Type SR 1B RR MR 1C RR DR 1D RR ALR 1E RR SLR 1F RR STH 40 RX LA 41 RX STC 42 RX IC 43 RX EX 44 RX BAL 45 RX BCT 46 RX BC 47 RX LH 48 RX CH 49 RX AH 4A RX SH 4B RX MH 4C RX BAS 4D RX CVD 4E RX Mnemonic Code Type CVB 4F RX ST 50 RX LAE 51 RX N 54 RX CL 55 RX O 56 RX X 57 RX L 58 RX C 59 RX A 5A RX S 5B RX M 5C RX D 5D RX AL 5E RX SL 5F RX STD 60 RX MXD 67 RX LD 68 RX CD 69 RX AD 6A RX Continues...
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Appendix – Instructions by operation code Some instructions (ordered by operation code)
Mnemonic Code Type SD 6B RX MD 6C RX DD 6D RX AW 6E RX SW 6F RX STE 70 RX LE 78 RX CE 79 RX BXH 86 RS BXLE 87 RS SRL 88 RS SLL 89 RS SRA 8A RS SLA 8B RS SRDL 8C RS SLDL 8D RS SRDA 8E RS SLDA 8F RS STM 90 RS TM 91 SI Mnemonic Code Type MVI 92 SI TS 93 S NI 94 SI CLI 95 SI OI 96 SI XI 97 SI LM 98 RS MC AF SI LRA B1 RX STCK B205 S CS BA RS CDS BB RS CLM BD RS STCM BE RS ICM BF RS MVN D1 SS/L MVC D2 SS/L MVZ D3 SS/L NC D4 SS/L CLC D5 SS/L Mnemonic Code Type OC D6 SS/L XC D7 SS/L TR DC SS/L TRT DD SS/L ED DE SS/L EDMK DF SS/L MVCIN E8 SS/L SRP F0 SS/L1I3 MVO F1 SS/L1L2 PACK F2 SS/L1L2 UNPK F3 SS/L1L2 ZAP F8 SS/L1L2 CP F9 SS/L1L2 AP FA SS/L1L2 SP FB SS/L1L2 MP FC SS/L1L2 DP FD SS/L1L2
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Appendix – Instructions by mnemonic Some instructions (ordered by mnemonic)
Mnemonic Code Type A 5A RX AD 6A RX AH 4A RX AL 5E RX ALR 1E RR AP FA SS/L1L2 AR 1A RR AW 6E RX BAL 45 RX BALR 05 RR BAS 4D RX BASR 0D RR BASSM 0C RR BC 47 RX BCR 07 RR BCT 46 RX BCTR 06 RR BSM 0B RR BXH 86 RS BXLE 87 RS Mnemonic Code Type C 59 RX CD 69 RX CDS BB RS CE 79 RX CH 49 RX CL 55 RX CLC D5 SS/L CLCL 0F RR CLI 95 SI CLM BD RS CLR 15 RR CP F9 SS/L1L2 CR 19 RR CS BA RS CVB 4F RX CVD 4E RX D 5D RX DD 6D RX DP FD SS/L1L2 DR 1D RR Mnemonic Code Type ED DE SS/L EDMK DF SS/L EX 44 RX IC 43 RX ICM BF RS L 58 RX LA 41 RX LAE 51 RX LCR 13 RR LD 68 RX LE 78 RX LH 48 RX LM 98 RS LNR 11 RR LPR 10 RR LR 18 RR LRA B1 RX LTR 12 RR M 5C RX MC AF SI
Continues...
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Appendix – Instructions by mnemonic Some instructions (ordered by mnemonic)
Mnemonic Code Type MD 6C RX MH 4C RX MP FC SS/L1L2 MR 1C RR MVC D2 SS/L MVCIN E8 SS/L MVCL 0E RR MVI 92 SI MVN D1 SS/L MVO F1 SS/L1L2 MVZ D3 SS/L MXD 67 RX N 54 RX NC D4 SS/L NI 94 SI NR 14 RR O 56 RX OC D6 SS/L OI 96 SI OR 16 RR Mnemonic Code Type PACK F2 SS/L1L2 S 5B RX SD 6B RX SH 4B RX SL 5F RX SLA 8B RS SLDA 8F RS SLDL 8D RS SLL 89 RS SLR 1F RR SP FB SS/L1L2 SR 1B RR SRA 8A RS SRDA 8E RS SRDL 8C RS SRL 88 RS SRP F0 SS/L1I3 ST 50 RX STC 42 RX STCK B205 S Mnemonic Code Type STCM BE RS STD 60 RX STE 70 RX STH 40 RX STM 90 RS SVC 0A RR SW 6F RX TM 91 SI TR DC SS/L TRT DD SS/L TS 93 S UNPK F3 SS/L1L2 X 57 RX XC D7 SS/L XI 97 SI XR 17 RR ZAP F8 SS/L1L2
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Appendix – EBCDIC - Some characters Some EBCDIC configurations HEX
40 4B 4C 4D 4E 4F 50 5A 5B 5C 5D 5E 5F C
ARATER
Space . point < less than ( Left parenheses + Plus sign | Vertical bar & Ampersand ! Exclamation mark $ Dollar sign * Asterisk ) Right parentheses ; Semicolon Not 7C 7D 7E 7F 60 61 6B 6C 6D 6E 6F 7A 7B hiphen / slash , comma % percent _ underscore > Greater than ? Question mark : colon # number sign @ at ' apostrophe = equals " quotes 81 82 83 84 85 86 87 88 91 92 93 94 95 96 97 98 99 9A a b d e f l m n o h i j q r A2 A3 A5 A6 A7 A9 C0 C1 C3 C4 C5 C6 C8 C9 A B C D E F G H I s t u v w x y z { Left brace D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 E0 E2 E3 E4 E5 E6 E7 E8 E9 U V W X Y Z N O P Q } Right brace J K L M R \ Backslash S T
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 0 1 2 3 4 5 6 7 8 9
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Appendix – ASCII - Some characters Some ASCII configurations HEX
20 21 26 27 28 29 22 23 24 25 2A 2B 2C 2D 2E 2F
CARATER
Space ! exclamation mark “ quotes # number $ dollar sign % percent sign & ampersand ‘ apostrophe ( Left parentheses ) Right parentheses * asterisk + plus sign , comma - hyphen . point / slash
30 31 36 37 38 39 32 33 34 35 3A 3B 3C 3D 3E 3F 0 zero 1 one 2 two 3 three 4 four 5 five 6 six 7 seven 8 eight 9 nine : colon ; semicolon < less than = equals > greater ? question mark
40 41 @ at 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 P Q R S T U V W X Y Z [ Left bracket \ back slash ] Right bracket ^ circumflex _ (underscore) 60 61 ` grave accent a 62 63 64 65 66 67 68 69 f g h i b c d e 6A j 6B k 6C l 6D m 6E 6F n o 70 p 71 q 72 73 74 75 76 77 78 79 r s t u v w x y 7A z 7B 7C { Left brace | Vertical Slash 7D 7E } Right brace ~ tilde
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Questions
Questions
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(Q) Exercises 1-12 (Convert decimal to binary)
Exercise 1 : (987654) 10 Exercise 2 : (4095) 10 = (?) = (?) 2 2 Exercise 3 : (7) 10 = (?) 2 Exercise 4 : (1023) 10 = (?) 2 Exercise 5 : (4096) 10 Exercise 6 : (255) 10 = (?) = (?) 2 2 Exercise 7 : (1024) 10 = (?) 2 Exercise 8 : (10010001) 10 = (?) 2 Exercise 9 : (256) 10 = (?) 2 Exercise 10 : (1025) 10 = (?) 2 Exercise 11 : (999888) 10 Exercise 12 : (65432) 10 = (?) = (?) 2 2
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(Q) Exercises 13-24 (Convert decimal to hexadecimal)
Exercise 13 : (987654) 10 Exercise 14 : (4095) 10 = (?) = (?) 16 16 Exercise 15 : (7) 10 = (?) 16 Exercise 16 : (1023) 10 = (?) 16 Exercise 17 : (4096) 10 Exercise 18 : (255) 10 = (?) = (?) 16 16 Exercise 19 : (1024) 10 = (?) 16 Exercise 20 : (10010001) 10 = (?) 16 Exercise 21 : (256) 10 Exercise 22 : (1025) 10 = (?) 16 = (?) 16 Exercise 23 : (999888) 10 = (?) 16 Exercise 24 : (65432) 10 = (?) 16
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(Q) Exercises 25-36 (Convert binary to hexadecimal)
Exercise 25 : (11111000111010100100001 ) 2 = (?) 16 Exercise 26 : (1000000111000111111110000011111110) 2 Exercise 27 : (1100) 2 = (?) 16 Exercise 28 : (11111110001) 2 = (?) 16 Exercise 29 : (1010101010101000110011000111) 2 = (?) 16 = (?) 16 Exercise 30 : (110011001100110011001) 2 Exercise 31 : (1000000000000001) 2 = (?) 16 = (?) 16 Exercise 32 : (1000000001) 2 = (?) 16 Exercise 33 : (111111100000001111111) 2 = (?) 16 Exercise 34 : (1) 2 = (?) 16 Exercise 35 : (1100101011111110) 2 = (?) 16 Exercise 36 : (101011010111000111000000001111110001111) 2 = (?) 16
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(Q) Exercises 37-48 (Convert hexadecimal to binary)
Exercise 37 : (CAFE) 16 = (?) 2 Exercise 38 : (CDF) 16 = (?) 2 Exercise 39 : (1AB4D) 16 Exercise 40 : (15) 16 = (?) 2 = (?) 2 Exercise 41 : (F) 16 = (?) 2 Exercise 42 : (87B54) 16 = (?) 2 Exercise 43 : (1001) 16 Exercise 44 : (234) 16 = (?) = (?) 2 2 Exercise 45 : (CAD) 16 Exercise 46 : (7F7) 16 = (?) = (?) 2 2 Exercise 47 : (1990) 16 Exercise 48 : (33) 16 = (?) = (?) 2 2
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(Q) Exercises 49-60 (Convert binary to decimal)
Exercise 49 : (11) 2 = (?) 10 Exercise 50 : (100001111111) 2 Exercise 51 : (101010010101) 2 = (?) 10 = (?) 10 Exercise 52 : (110000001111111) 2 Exercise 53 : (11111110000011) 2 = (?) = (?) 10 10 Exercise 54 : (11110000111000) Exercise 55 : (11) 2 = (?) 10 2 = (?) 10 Exercise 56 : (111111110) 2 = (?) 10 Exercise 57 : (1111100001111000111001101) 2 Exercise 58 : (1000000000000) Exercise 59 : (11111001) 2 = (?) 2 10 = (?) 10 Exercise 60 : (1000000000000001) 2 = (?) 10 = (?) 10
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(Q) Exercises 61-72 (Convert hexadecimal to decimal)
Exercise 61 : (11) 16 = (?) 10 Exercise 62 : (AAF45) 16 = (?) 10 Exercise 63 : (1B567) 16 Exercise 64 : (100) 16 = (?) = (?) 10 10 Exercise 65 : (1000) 16 Exercise 66 : (FF) 16 = (?) = (?) 10 10 Exercise 67 : (FFF) 16 Exercise 68 : (CDF) 16 = (?) 10 = (?) 10 Exercise 69 : (CAFE) 16 = (?) 10 Exercise 70 : (FACA) 16 Exercise 71 : (DAD0) 16 = (?) 10 = (?) 10 Exercise 72 : (F1E2D3C4) 16 = (?) 10
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400
(Q) Exercises 73-84 (Add numbers in binary)
Exercise 73 : (11001100) 2 + (10101010) 2 Exercise 74 : (1111001111) 2 = (?) + (1001111001) 2 2 = (?) 2 Exercise 75 : (1111) 2 Exercise 76 : (1111) 2 + (1) 2 + (111) = (?) 2 2 = (?) 2 Exercise 77 : (100001) 2 + (11110) 2 Exercise 78 : (1011110011) 2 = (?) 2 + (111101111) Exercise 79 : (110011001100) 2 + (101011110000) Exercise 80 : (1111100001111000) 2 2 = (?) 2 + (101111) 2 2 = (?) 2 = (?) 2 Exercise 81 : (111) 2 Exercise 82 : (11) 2 + (1111) + (111) 2 2 + (100) + (1111) 2 2 Exercise 83 : (1111) 2 + (1001) 2 + (11111) + (111) 2 = (?) 2 2 + (101) 2 = (?) 2 + (11) 2 Exercise 84 : (111) 2 + (1000) 2 + (1) 2 + (1100) 2 = (?) 2 + (1) 2 = (?) 2
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(Q) Exercises 85-96 (Subtract numbers in binary)
Exercise 85 : (11001100) 2 - (1010101) 2 Exercise 86 : (1111001111) 2 - (1111001) 2 = (?) 2 = (?) 2 Exercise 87 : (1111) 2 Exercise 88 : (1111) 2 - (1) 2 - (111) = (?) 2 2 = (?) 2 Exercise 89 : (100001) 2 Exercise 90 : (1011110011) Exercise 91 : (11001100) - (11110) 2 2 2 = (?) 2 - (111101111) 2 = (?) 2 - (111011110000) 2 = (?) 2 Exercise 92 : (1111000) Exercise 93 : (111) 2 2 - (101010111) - (1111) 2 = (?) 2 2 = (?) 2 Exercise 94 : (10001) Exercise 95 : (0) 2 Exercise 96 : (0) 2 - (1) 2 2 - (111111) 2 - (10) 2 = (?) 2 = (?) 2 = (?) 2
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(Q) Exercises 97-108 (Add numbers in hexadecimal)
Exercise 97 : (F12B) 16 Exercise 98 : (1100) 16 + (321) + (111) 2 16 = (?) = (?) 16 16 Exercise 99 : (1000F) 16 + (F0001) 16 Exercise 100 : (A9B8C7) 16 = (?) + (D6E5F4) 16 16 = (?) 16 Exercise 101 : (CAFE) 16 Exercise 102 : (B001) 16 + (CDF) + (FD) 16 16 = (?) = (?) 16 16 Exercise 103 : (999) 16 + (111) 16 Exercise 104 : (123456) 16 = (?) 16 + (789ABC) 16 = (?) 16 Exercise 105 : (FFF) 16 Exercise 106 : (DDD) 16 + (EEE) Exercise 107 : (987AED) 16 16 + (333) 16 = (?) 16 = (?) + (CF01) 16 16 = (?) 16 Exercise 108 : (FACA) 16 + (CAFE) 16 = (?) 16
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(Q) Exercises 109-120 (Subtract numbers in hexadecimal)
Exercise 109 : (F1C5) 16 - (101) 16 Exercise 110 : (1AD87C) 16 = (?) - (FDE9) 2 16 = (?) 16 Exercise 111 : (112233) 16 - (44556) 16 Exercise 112 : (AABBCC) 16 = (?) - (DDEEF) 16 16 = (?) 16 Exercise 113 : (F1E2D3) 16 Exercise 114 : (FF00001) 16 - (C4B5A6) 16 - (10000F) 16 = (?) 16 = (?) 16 Exercise 115 : (CAFE) 16 Exercise 116 : (CDF) 16 - (FACA) - (FDC) 16 16 = (?) = (?) 16 16 Exercise 117 : (10001) 16 Exercise 118 : (10000) 16 - (20001) 16 - (FFFE) 16 = (?) 16 = (?) 16 Exercise 119 : (0) 16 Exercise 120 : (0) 16 - (9) 16 - (1A) = (?) 16 16 = (?) 16
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(Q) Exercises 121-126 (Representing binary numbers in bytes)
Exercise 121 : (1) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 122 : (-1) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 123 : (10) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 124 : (-10) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 125 : (17) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 126 : (-17) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16
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405
(Q) Exercises 127-132 (Representing binary numbers in bytes)
Exercise 127 : (254) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 128 : (-254) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 129 : (100000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 130 : (-100000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 131 : (32000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 132 : (-32000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16
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406
(Q) Exercises 133-138 (Representing binary numbers in bytes)
Exercise 133 : (63000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 134 : (-63000) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 135 : (1010) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 136 : (-1010) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 137 : (4095) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 138 : (-4095) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16 = (xxxxxxxx) 16
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(Q) Exercises 139-140 (Representing binary numbers in bytes)
Exercise 139 : (4097) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 Exercise 140 : (-4097) 10 = (bbbb bbbb bbbb bbbb) 2 = (xxxx) 16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb) 2 = (xxxxxxxx) 16 = (xxxxxxxx) 16
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(Q) Exercises 141-152 (Representing packed numbers in bytes)
Exercise 141 : (1) 10 Exercise 142 : (-1) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 143 : (10) 10 Exercise 144 : (-10) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 145 : (17) 10 Exercise 146 : (-17) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 147 : (254) 10 Exercise 148 : (-254) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 149 : (100000) 10 Exercise 150 : (-100000) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 151 : (32000) 10 Exercise 152 : (-32000) 10 = (in decimal-packed format) = (in decimal-packed format)
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(Q) Exercises 153-160 (Representing packed numbers in bytes)
Exercise 153 : (63000) 10 Exercise 154 : (-63000) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 155 : (1010) 10 Exercise 156 : (-1010) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 157 : (4095) 10 Exercise 158 : (-4095) 10 = (in decimal-packed format) = (in decimal-packed format) Exercise 159 : (4097) 10 Exercise 160 : (-4097) 10 = (in decimal-packed format) = (in decimal-packed format)
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(Q) Exercises 161-172 (Representing zoned numbers in bytes)
Exercise 161 : (1) 10 Exercise 162 : (-1) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 163 : (10) 10 Exercise 164 : (-10) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 165 : (17) 10 Exercise 166 : (-17) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 167 : (254) 10 Exercise 168 : (-254) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 169 : (100000) 10 Exercise 170 : (-100000) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 171 : (32000) 10 Exercise 172 : (-32000) 10 = (in decimal-zoned format) = (in decimal-zoned format)
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(Q) Exercises 173-180 (Representing zoned numbers in bytes)
Exercise 173 : (63000) 10 Exercise 174 : (-63000) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 175 : (1010) 10 Exercise 176 : (-1010) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 177 : (4095) 10 Exercise 178 : (-4095) 10 = (in decimal-zoned format) = (in decimal-zoned format) Exercise 179 : (4097) 10 Exercise 180 : (-4097) 10 = (in decimal-zoned format) = (in decimal-zoned format)
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(Q) Exercises 181-194 (Representing character strings in bytes)
Exercise 181 : “17“ = (in alphanumeric EBCDIC) Exercise 182 : “-17“ = (in alphanumeric EBCDIC) Exercise 183 : “AF$BD“ = (in alphanumeric EBCDIC) Exercise 184 : “-AF4BD“ = (in alphanumeric EBCDIC) Exercise 185 : “ALBERTO“ = (in alphanumeric EBCDIC) Exercise 186 : “15-9“ = (in alphanumeric EBCDIC) Exercise 187 : “-4095“ = (in alphanumeric EBCDIC) Exercise 188 : “4095“ = (in alphanumeric EBCDIC) Exercise 189 : “*&$//“ = (in alphanumeric EBCDIC) Exercise 190 : “12+3“ = (in alphanumeric EBCDIC) Exercise 191 : “I LOVE HER“ = (in alphanumeric EBCDIC) Exercise 192 : “US$ 2,584.73“ = (in alphanumeric EBCDIC) Exercise 193 : “US$ 1 MILLION“ = (in alphanumeric EBCDIC) Exercise 194 : “PANCHO’S BAR“ = (in alphanumeric EBCDIC)
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(Q) Exercises 195-209 (Representing fields in bytes)
Exercises 195-300 must be considered as a program starting at address X’00000000’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9.
Exercise 195: DC C'123' Exercise 196: Exercise 197: Exercise 198: Exercise 199: Exercise 200: Exercise 201: Exercise 202: Exercise 203: Exercise 204: Exercise 205: Exercise 206: Exercise 207: Exercise 208: Exercise 209: DC DC DC DC DC DC DC DC DC DC DC DC DC DC C'+123' C'-123' C'12.3' C'1AB8' C'01101' C'A+B=C' CL4'A' CL4'ABCDEF' 3CL2'A' 2CL3'A,B' C'ME&&YOU' C'''S MUSIC' C'@@OI' CL3'*'
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(Q) Exercises 210-225 (Representing fields in bytes)
Exercise 210: Exercise 211: Exercise 212: Exercise 213: Exercise 214: Exercise 215: Exercise 216: Exercise 217: Exercise 218: Exercise 219: Exercise 220: Exercise 221: Exercise 222: Exercise 223: Exercise 224: Exercise 225: DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC 3C'*' X'123' X'-123' X'1AB2C3' X'1AB2F4G3' XL3'12D' XL3'AABBCCDDEE' X'1,22,333,4444' XL2'1,22,333' 2X'1,22,333' 2XL2'1,22' B'01010101' B'1' BL2'1111' B'1,1111111111' BL2'1,1111111111'
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(Q) Exercises 226-239 (Representing fields in bytes)
Exercise 226: Exercise 227: Exercise 228: Exercise 229: Exercise 230: Exercise 230: Exercise 231: Exercise 232: Exercise 233: Exercise 234: Exercise 235: Exercise 236: Exercise 237: Exercise 238: Exercise 239: DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC 2B'1000' 2BL2'1000' F'10' F'+10' F'-10' F'-15,+16' 2F'22' 2F'33,44' FL3'258' 2FL1'255' F'128000' H'10' H'+10' H'-10' H'-15,+16'
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(Q) Exercises 240-254 (Representing fields in bytes)
Exercise 240: Exercise 241: Exercise 242: Exercise 243: Exercise 244: Exercise 245: Exercise 246: Exercise 247: Exercise 248: Exercise 249: Exercise 250: Exercise 251: Exercise 252: Exercise 253: Exercise 254: DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC 2H'22' 2H'33,44' HL3'258' 2HL1'255' H'128000' P'123' P'+123' P'-123' PL4'456' PL1'789' P'1,-22,333,-4444' PL2'1,-22,333,-4444' 3P'0' PL3'0' 2P'1,22,333'
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(Q) Exercises 255-266 (Representing fields in bytes)
Exercise 255: Exercise 256: Exercise 257: Exercise 258: Exercise 259: Exercise 260: Exercise 261: Exercise 262: Exercise 263: Exercise 264: Exercise 265: Exercise 266: DC DC DC DC DC DC DC DC DC DC DC DC 2PL2'1,22,333' Z'123' Z'+123' Z'-123' ZL4'456' ZL1'789' Z'1,-22,333,-4444' ZL3'1,-22,333,-4444' 3Z'0' ZL3'0' 2Z'1,22,333' 2ZL3'1,22,333'
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(Q) Exercises 267-279 (Representing fields in bytes)
Exercise 267: SIMBZZ DC Exercise 268: SIMBAA DC Exercise 269: SIMBBB DC Exercise 270: SIMBCC DC Exercise 271: SIMBDD DC Exercise 272: SIMBEE DC Exercise 273: SIMBFF DS Exercise 274: SIMBGG DC Exercise 275: SIMBHH DC Exercise 276: SIMBII DC Exercise 277: SIMBJJ DC Exercise 278: SIMBKK DC Exercise 279: SIMBLL DC A(0) A(127) A(X'8000') A(B'1111') A(C'*') A(*) CL17 A(*) A(SIMBGG) A(SIMBAA+12) A(SIMBII-SIMBBB) AL1(*-SIMBKK) 5AL1(*-SIMBLL)
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(Q) Exercises 280-290 (Representing fields in bytes)
Exercise 280: SIMBMM Exercise 281: SIMBNN Exercise 282: SIMBOO Exercise 283: SIMBPP Exercise 284: SIMBQQ Exercise 285: SIMBRR Exercise 286: SIMBSS Exercise 287: SIMBTT Exercise 288: SIMBUU Exercise 289: SIMBVV Exercise 290: SIMBWW DC DC DC DC DC DC DC DC DC DC DC AL2(3,5,7) A(SIMBII+5*2) A(SIMBNN+X'80000000') 4AL2(*-SIMBPP) A(SIMBVV) A(SIMBKK,SIMBJJ) A(SIMBTT+40) A(SIMBUU,*,80) 2A(*-SIMBUU) A(C'AMO') A(X'7FFFFFFF')
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(Q) Exercises 291-300 (Representing fields in bytes)
Exercise 291: YY1 Exercise 292: YY2 Exercise 293: YY3 Exercise 294: SS1 Exercise 295: SS2 Exercise 296: SS3 Exercise 297: SS4 Exercise 298: SS5 DC DC DC DC DC DC DC DC Y(SIMBWW) Y(10) Y(L'YY2) S(SIMBAA) S(SS1) S(10) S(*) A(125),F'33',C'*',2H'6,18' Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' Exercise 300: LAST DC 256AL1(255+LAST-*)
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(Q) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions; for each one, specify: - Operation code (machine code) - Menmonic Assembler code - Instruction address (suppose 1st instruction at address X’00000000’) - Operands (register, base register, index register, displacement; if operand is in storage, compute the operand address; to compute the operand’s addresses suppose the general registers with the following contents: R00=00112233 R04=00000400 R08=00000800 R12=00000C00 R01=00000100 R05=00000500 R09=00000900 R13=00000D00 R02=00000200 R06=00000600 R10=00000A00 R14=00000E00 R03=00000300 R07=00000700 R11=00000B00 R15=00000F00 Instructions to decode: 1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
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Answers
Answers
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423
(A) Exercises 1-12 (Convert decimal to binary)
Exercise 1 : (987654) 10 Exercise 2 : (4095) 10 = (1111 0001 0010 0000 0110) = (1111 1111 1111) 2 2 Exercise 3 : (7) 10 = (111) 2 Exercise 4 : (1023) 10 = (11 1111 1111) 2 Exercise 5 : (4096) 10 Exercise 6 : (255) 10 = (1 0000 0000 0000) = (1111 1111) 2 2 Exercise 7 : (1024) 10 = (100 0000 0000) 2 Exercise 8 : (10010001) 10 = (1001 1000 1011 1101 1001 0001) 2 Exercise 9 : (256) 10 = (1 0000 0000) 2 Exercise 10 : (1025) 10 = (100 0000 0001) 2 Exercise 11 : (999888) 10 Exercise 12 : (65432) 10 = (1111 0100 0001 1101 0000) = (1111 1111 1001 1000) 2 2
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(A) Exercises 13-24 (Convert decimal to hexadecimal)
Exercise 13 : (987654) 10 Exercise 14 : (4095) 10 = (F1206) = (FFF) 16 16 Exercise 15 : (7) 10 = (7) 16 Exercise 16 : (1023) 10 = (3FF) 16 Exercise 17 : (4096) 10 Exercise 18 : (255) 10 = (1000) = (FF) 16 16 Exercise 19 : (1024) 10 = (400) 16 Exercise 20 : (10010001) 10 = (98BD91) 16 Exercise 21 : (256) 10 Exercise 22 : (1025) 10 = (100) 16 = (401) 16 Exercise 23 : (999888) 10 Exercise 24 : (65432) 10 = (F41D0) = (FF98) 16 16
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425
(A) Exercises 25-36 (Convert binary to hexadecimal)
Exercise 25 : (11111000111010100100001 ) 2 = (7C7521) 16 Exercise 26 : (1000000111000111111110000011111110) 2 = (2071FE0FE) 16 Exercise 27 : (1100) 2 = (C) 16 Exercise 28 : (11111110001) 2 = (7F1) 16 Exercise 29 : (1010101010101000110011000111) Exercise 30 : (110011001100110011001) 2 2 = (AAA8CC7) 16 = (199999) 16 Exercise 31 : (1000000000000001) 2 Exercise 32 : (1000000001) 2 = (201) = (8001) 16 16 Exercise 33 : (111111100000001111111) Exercise 34 : (1) 2 = (1) 16 2 = (1FC07F) 16 Exercise 35 : (1100101011111110) 2 = (CAFE) 16 Exercise 36 : (101011010111000111000000001111110001111) 2 = (56B8E01F8F) 16
Alberto Romano Schiesari – www.profars.com
426
(A) Exercises 37-48 (Convert hexadecimal to binary)
Exercise 37 : (CAFE) 16 = (1100101011111110) 2 Exercise 38 : (CDF) 16 = (110011011111) 2 Exercise 39 : (1AB4D) 16 Exercise 40 : (15) 16 = (11010101101001101) = (10101) 2 2 Exercise 41 : (F) 16 = (1111) 2 Exercise 42 : (87B54) 16 = (10000111101101010100) 2 Exercise 43 : (1001) 16 Exercise 44 : (234) 16 = (1000000000001) = (1000110100) 2 2 Exercise 45 : (CAD) 16 Exercise 46 : (7F7) 16 = (110010101101) = (11111110111) 2 2 Exercise 47 : (1990) 16 Exercise 48 : (33) 16 = (1100110010000) = (110011) 2 2
Alberto Romano Schiesari – www.profars.com
427
(A) Exercises 49-60 (Convert binary to decimal)
Exercise 49 : (11) 2 = (3) 10 Exercise 50 : (100001111111) 2 Exercise 51 : (101010010101) 2 = (2175) 10 = (2709) 10 Exercise 52 : (110000001111111) 2 Exercise 53 : (11111110000011) 2 = (24703) = (16259) 10 10 Exercise 54 : (11110000111000) Exercise 55 : (11) 2 = (3) 10 2 = (15416) 10 Exercise 56 : (111111110) 2 = (510) 10 Exercise 57 : (1111100001111000111001101) 2 Exercise 58 : (1000000000000) 2 Exercise 59 : (11111001) 2 = (249) = (4096) 10 10 Exercise 60 : (1000000000000001) 2 = (32567757) = (32769) 10 10
Alberto Romano Schiesari – www.profars.com
428
(A) Exercises 61-72 (Convert hexadecimal to decimal)
Exercise 61 : (11) 16 = (17) 10 Exercise 62 : (AAF45) 16 = (700229) 10 Exercise 63 : (1B567) 16 Exercise 64 : (100) 16 = (111975) = (256) 10 10 Exercise 65 : (1000) 16 Exercise 66 : (FF) 16 = (4096) = (255) 10 10 Exercise 67 : (FFF) 16 Exercise 68 : (CDF) 16 = (4095) 10 = (3295) 10 Exercise 69 : (CAFE) 16 = (51966) 10 Exercise 70 : (FACA) 16 Exercise 71 : (DAD0) 16 = (64202) 10 = (56016) 10 Exercise 72 : (F1E2D3C4) 16 = (4058174404) 10
Alberto Romano Schiesari – www.profars.com
429
(A) Exercises 73-84 (Add numbers in binary)
Exercise 73 : (11001100) 2 + (10101010) 2 Exercise 74 : (1111001111) 2 = (1 0111 0110) + (1001111001) 2 2 = (110 0100 1000) 2 Exercise 75 : (1111) 2 Exercise 76 : (1111) 2 + (1) 2 + (111) = (10000) 2 2 = (10110) 2 Exercise 77 : (100001) 2 + (11110) 2 Exercise 78 : (1011110011) 2 = (111111) + (111101111) 2 2 = (100 1110 0010) 2 Exercise 79 : (110011001100) 2 + (101011110000) 2 Exercise 80 : (1111100001111000) 2 + (101111) 2 = (1 0111 1011 1100) = (1111 1000 1010 0111) 2 2 Exercise 81 : (111) 2 Exercise 82 : (11) 2 + (1111) + (111) 2 2 + (100) + (1111) 2 2 = (11010) + (11111) 2 2 = (111000) 2 Exercise 83 : (1111) 2 Exercise 84 : (111) 2 + (1001) + (1000) 2 2 + (111) + (1) 2 2 + (101) + (1100) 2 2 + (11) 2 = (11100) 2 + (1) 2 = (101000) 2
Alberto Romano Schiesari – www.profars.com
430
(A) Exercises 85-96 (Subtract numbers in binary)
Exercise 85 : (11001100) 2 - (1010101) 2 Exercise 86 : (1111001111) 2 - (1111001) 2 = (111 0111) 2 = (11 0101 0110) 2 Exercise 87 : (1111) 2 Exercise 88 : (1111) 2 - (1) 2 - (111) = (1110) 2 2 = (1000) 2 Exercise 89 : (100001) 2 Exercise 90 : (1011110011) Exercise 91 : (11001100) - (11110) 2 2 2 = (11) 2 - (111101111) 2 = (1 0000 0100) 2 - (111011110000) 2 = (...1111 1111 1100 1101) 2 Exercise 92 : (1111000) 2 Exercise 93 : (111) 2 - (101010111) - (1111) 2 2 = (... 1111 1111 0010 0001) = (... 1111 1111 1111 1000) 2 2 Exercise 94 : (10001) 2 Exercise 95 : (0) 2 - (1) 2 - (111111) 2 = (... 1111 1111 1101 0010) = (... 1111 1111 1111 1111) 2 2 Exercise 96 : (0) 2 - (10) 2 = (... 1111 1111 1111 1110) 2
Alberto Romano Schiesari – www.profars.com
431
(A) Exercises 97-108 (Add numbers in hexadecimal)
Exercise 97 : (F12B) 16 Exercise 98 : (1100) 16 + (321) + (111) 2 16 = (F44C) = (1211) 16 16 Exercise 99 : (1000F) 16 + (F0001) 16 Exercise 100 : (A9B8C7) 16 = (100010) + (D6E5F4) 16 16 = (1809EBB) 16 Exercise 101 : (CAFE) 16 Exercise 102 : (B001) 16 + (CDF) + (FD) 16 16 = (D7DD) = (B0FE) 16 16 Exercise 103 : (999) 16 + (111) 16 Exercise 104 : (123456) 16 = (AAA) + (789ABC) 16 16 = (19BBF12) 16 Exercise 105 : (FFF) 16 Exercise 106 : (DDD) 16 + (EEE) Exercise 107 : (987AED) 16 16 + (333) 16 = (1EED) 16 = (1110) + (CF01) 16 16 = (9949EE) 16 Exercise 108 : (FACA) 16 + (CAFE) 16 = (1C5C8) 16
Alberto Romano Schiesari – www.profars.com
432
(A) Exercises 109-120 (Subtract numbers in hexadecimal)
Exercise 109 : (F1C5) 16 - (101) 16 Exercise 110 : (1AD87C) 16 = (F0C4) - (FDE9) 2 16 = (19DA93) 16 Exercise 111 : (112233) 16 - (44556) 16 Exercise 112 : (AABBCC) 16 = (CDCDD) - (DDEEF) 16 16 = (9CDCDD) 16 Exercise 113 : (F1E2D3) 16 Exercise 114 : (FF00001) 16 - (C4B5A6) 16 - (10000F) 16 = (2D2D2D) 16 = (FDFFFF2) 16 Exercise 115 : (CAFE) 16 Exercise 116 : (CDF) 16 - (FACA) - (FDC) 16 16 = (...FFFFD034) = (...FFFFFD03) 16 16 Exercise 117 : (10001) 16 Exercise 118 : (10000) 16 - (20001) 16 - (FFFE) 16 = (...FFFF0000) = (2) 16 16 Exercise 119 : (0) 16 Exercise 120 : (0) 16 - (9) 16 - (1A) = (...FFFFFFF7) 16 16 = (...FFFFFFE6) 16
Alberto Romano Schiesari – www.profars.com
433
(A) Exercises 121-126 (Representing binary numbers in bytes)
Exercise 121 : (1) 10 = (0000 0000 0000 0001) 2 = (0001) 16 = (0000 0000 0000 0000 0000 0000 0000 0001) 2 Exercise 122 : (-1) 10 = (1111 1111 1111 1111) 2 = (FFFF) 16 = (1111 1111 1111 1111 1111 1111 1111 1111) 2 = (00000001) = (FFFFFFFF) 16 16 Exercise 123 : (10) 10 = (0000 0000 0000 1010) 2 = (000A) 16 = (0000 0000 0000 0000 0000 0000 0000 1010) 2 Exercise 124 : (-10) 10 = (1111 1111 1111 0110) 2 = (FFF6) 16 = (1111 1111 1111 1111 1111 1111 1111 0110) 2 = (0000000A) = (FFFFFFF6) 16 16 Exercise 125 : (17) 10 = (0000 0000 0001 0001) 2 = (0011) 16 = (0000 0000 0000 0000 0000 0000 0001 0001) 2 Exercise 126 : (-17) 10 = (1111 1111 1110 1111) 2 = (FFEF) 16 = (1111 1111 1111 1111 1111 1111 1110 1111) 2 = (00000011) = (FFFFFFEF) 16 16
Alberto Romano Schiesari – www.profars.com
434
(A) Exercises 127-132 (Representing binary numbers in bytes)
Exercise 127 : (254) 10 = (0000 0000 1111 1110) 2 = (00FE) 16 = (0000 0000 0000 0000 0000 0000 1111 1110) 2 Exercise 128 : (-254) 10 = (1111 1111 0000 0010) 2 = (FF02) 16 = (1111 1111 1111 1111 1111 1111 0000 0010) 2 = (000000FE) = (FFFFFF02) 16 16 Exercise 129 : (100000) 10 = (impossible to represent in 2 bytes) = (0000 0000 0000 0001 1000 0110 1010 0000) 2 Exercise 130 : (-100000) 10 = (impossible to represent in 2 bytes) = (1111 1111 1111 1110 0111 1001 0110 0000) 2 = (000186A0) = (FFFE7960) 16 16 Exercise 131 : (32000) 10 = (0111 1101 0000 0000) 2 = (7D00) 16 = (0000 0000 0000 0000 0111 1101 0000 0000) 2 Exercise 132 : (-32000) 10 = (1000 0011 0000 0000) 2 = (8300) 16 = (1111 1111 1111 1111 1000 0011 0000 0000) 2 = (00007D00) = (FFFF8300) 16 16
Alberto Romano Schiesari – www.profars.com
435
(A) Exercises 133-138 (Representing binary numbers in bytes)
Exercise 133 : (63000) 10 = (impossible to represent in 2 bytes) = (1111 1111 1111 1111 1111 0110 0001 1000 ) 2 Exercise 134 : (-63000) 10 = (impossible to represent in 2 bytes) = (1111 1111 1111 1111 0000 1001 1110 1000) 2 = (FFFFF618) 16 = (FFFF09E8) 16 Exercise 135 : (1010) 10 = (0000 0011 1111 0010) 2 = (03F2) 16 = (0000 0000 0000 0000 0000 0011 1111 0010) 2 Exercise 136 : (-1010) 10 = (1111 1100 0000 1110) 2 = (FC0E) 16 = (1111 1111 1111 1111 1111 1100 0000 1110) 2 = (000003F2) = (FFFFFC0E) 16 16 Exercise 137 : (4095) 10 = (0000 1111 1111 1111) 2 = (0FFF) 16 = (0000 0000 0000 0000 0000 1111 1111 1111) 2 Exercise 138 : (-4095) 10 = (1111 0000 0000 0001) 2 = (F001) 16 = (1111 1111 1111 1111 1111 0000 0000 0001) 2 = (00000FFF) = (FFFFF001) 16 16
Alberto Romano Schiesari – www.profars.com
436
(A) Exercises 139-140 (Representing binary numbers in bytes)
Exercise 139 : (4097) 10 = (0001 0000 0000 0001) 2 = (1001) 16 = (0000 0000 0000 0000 0001 0000 0000 0001) 2 Exercise 140 : (-4097) 10 = (1110 1111 1111 1111) 2 = (EFFF) 16 = (1111 1111 1111 1111 1110 1111 1111 1111) 2 = (00001001) = (FFFFEFFF) 16 16
Alberto Romano Schiesari – www.profars.com
437
(A) Exercises 141-152 (Representing packed numbers in bytes)
Exercise 141 : (1) 10 Exercise 142 : (-1) 10 = [ 0001 1100 ] = [ 1C ] = [ 0001 1101 } = [ 1D ] Exercise 143 : (10) 10 Exercise 144 : (-10) 10 = [ 0000 0001 0000 1100 ] = [ 010C ] = [ 0000 0001 0000 1101 ] = [ 10D ] Exercise 145 : (17) 10 Exercise 146 : (-17) 10 = [ 0000 0001 0111 1100 ] = [ 017C ] = [ 0000 0001 0111 1101 ] = [ 017D ] Exercise 147 : (254) 10 Exercise 148 : (-254) 10 = [ 0010 0101 0100 1100 ] = [ 254C ] = [0010 0101 0100 1101 ] = [ 254D ] Exercise 149 : (100000) 10 = [ 0000 0001 0000 0000 0000 0000 0000 1100 ] = [ 0100000C ] Exercise 150 : (100000) 10 = [ 0000 0001 0000 0000 0000 0000 0000 1101 ] = [ 0100000D ] Exercise 151 : (32000) 10 Exercise 152 : (-32000) 10 = [ 0011 0010 0000 0000 0000 1100 ] = [ 32000C ] = [ 0011 0010 0000 0000 0000 1101 ] = [ 32000D ]
Alberto Romano Schiesari – www.profars.com
438
(A) Exercises 153-160 (Representing packed numbers in bytes)
Exercise 153 : (63000) 10 Exercise 154 : (-63000) 10 = [ 0110 0011 0000 0000 0000 1100 ] = [ 63000C ] = [ 0110 0011 0000 0000 0000 1101 ] = [ 63000D ] Exercise 155 : (1010) 10 Exercise 156 : (-1010) 10 = [ 0000 0001 0000 0001 0000 1100 ] = [ 01010C ] = [ 0000 0001 0000 0001 0000 1100 ] = [ 01010D ] Exercise 157 : (4095) 10 Exercise 158 : (-4095) 10 = [ 0000 0100 0000 1001 0101 1100 ] = [ 04095C ] = [ 0000 0100 0000 1001 0101 1101 ] = [ 04095D ] Exercise 159 : (4097) 10 Exercise 160 : (-4097) 10 = [ 0000 0100 0000 1001 0111 1100 ] = [ 04097C ] = [ 0000 0100 0000 1001 0111 1101 ] = [ 04097D ]
Alberto Romano Schiesari – www.profars.com
439
(A) Exercises 161-172 (Representing zoned numbers in bytes)
Exercise 161 : (1) 10 Exercise 162 : (-1) 10 = [ 1111 0001 ] = [ F1 ] = [ 1101 0001 } = [ D1 ] Exercise 163 : (10) 10 Exercise 164 : (-10) 10 Exercise 165 : (17) 10 Exercise 166 : (-17) 10 = [ 1111 0001 1111 0000 ] = [ F1F0 ] Exercise 167 : (254) 10 Exercise 168 : (-254) 10 = [ 1111 0001 1101 0000 ] = [ F1D0 ] = [ 1111 0001 1111 0111 ] = [ F1F7 ] = [ 1111 0001 1101 0111 ] = [ F1D7 ] = [ 1111 0010 1111 0101 1111 0100 ] = [ F2F5F4 ] = [ 1111 0010 1111 0101 1101 0100 ] = [ F2F5D4 ] Exercise 169 : (100000) 10 = [ 1111 0001 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 ] = [ F1F0F0F0F0F0 ] Exercise 170 : (-100000) 10 = [ 1111 0001 1111 0000 1111 0000 1111 0000 1111 0000 1101 0000 ] = [ F1F0F0F0F0D0 ] Exercise 171 : (32000) 10 = [ 1111 0011 1111 0010 1111 0000 1111 0000 1111 0000 ] = [ F3F2F0F0F0 ] Exercise 172 : (-32000) 10 = [ 1111 0011 1111 0010 1111 0000 1111 0000 1111 0000 ] = [ F3F2F0F0D0 ]
Alberto Romano Schiesari – www.profars.com
440
(A) Exercises 173-180 (Representing zoned numbers in bytes)
Exercise 173 : (63000) 10 = [ 1111 0110 1111 0011 1111 0000 1111 0000 1111 0000 ] = [ F6F3F0F0F0 ] Exercise 174 : (-63000) 10 = [ 1111 0110 1111 0011 1111 0000 1111 0000 1101 0000 ] = [ F6F3F0F0D0 ] Exercise 175 : (1010) 10 Exercise 176 : (-1010) 10 = [ 1111 0001 1111 0000 1111 0001 1111 0000 ] = [ F1F0F1F0 ] = [ 1111 0001 1111 0000 1111 0001 1101 0000 ] = [ F1F0F1D0 ] Exercise 177 : (4095) 10 Exercise 178 : (-4095) 10 = [ 1111 0100 1111 0000 1111 1001 1111 0101 ] = [ F4F0F9F5 ] = [ 1111 0100 1111 0000 1111 1001 1101 0101 ] = [ F4F0F9D5 ] Exercise 179 : (4097) 10 Exercise 180 : (-4097) 10 = [ 1111 0100 1111 0000 1111 1001 1111 1111 ] = [ F4F0F9F7 ] = [ 1111 0100 1111 0000 1111 1001 1101 0111 ] = [ F4F0F9D7 ]
Alberto Romano Schiesari – www.profars.com
441
(A) Exercises 181-194 (Representing character strings in bytes)
Exercise 181 : “17“ = [ F1F7 ] Exercise 182 : “-17“ = [ 60F1F7 ] Exercise 183 : “AF$BD“ = [ C1C66BC2C4 ] Exercise 184 : “-AF4BD“ = [ 60C1C6F4C2C4 ] Exercise 185 : “ALBERTO“ = [ C1D3C2C5D9E3D6 ] Exercise 186 : “15-9“ = [ F1F560F9 ] Exercise 187 : “-4095“ = [ 60F4F0F9F5 ] Exercise 188 : “4095“ = [ F4F0F9F5 ] Exercise 189 : “*&$//“ = [ 5C505B6161 ] Exercise 190 : “12+3“ = [ F1F24EF3 ] Exercise 191 : “I LOVE HER“ = [ C940D3D6E5C540C8C5D9 ] Exercise 192 : “US$ 2,584.73“ = [ E4E25B40F26BF5F8F44BF7F3 ] Exercise 193 : “US$ 1 MILLION“ = [ E4E25B40F140D4C9D3D3C9D6D5 ] Exercise 194 : “PANCHO’S BAR“ = [ D7C1C5C3C8D67DE240C2C1D9 ]
Alberto Romano Schiesari – www.profars.com
442
(A) Exercises 195-209 (Representing fields in bytes)
Exercises 195-300 must be considered as a program starting at address X’00000000’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9.
* Address Contents Exercise 195: Exercise 196: Exercise 197: Exercise 198: Exercise 199: Exercise 200: Exercise 201: Exercise 202: Exercise 203: Exercise 204: Exercise 205: Exercise 206: Exercise 207: Exercise 208: Exercise 209:
DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC
C'123' C'+123' C'-123' C'12.3' C'1AB8' C'01101' C'A+B=C' CL4'A' CL4'ABCDEF' 3CL2'A' 2CL3'A,B' C'ME&&YOU' C'''S MUSIC' C'@@OI' CL3'*' 0000 F1.F2.F3
0003 4E.F1.F2.F3
0007 60.F1.F2.F3
000B F1.F2.4B.F3
000F F1.C1.C2.F8
0013 F0.F1.F1.F0.F1
0018 C1.4E.C2.7E.C3
001D C1.40.40.40
0021 C1.C2.C3.C4
0025 C1.40.C1.40.C1.40
002B C1.6B.C2.C1.6B.C2
0031 D4.C5.50.E8.D6.E4
0037 7D.E2.40.D4.E4.E2.C9.C3
003F 7C.7C.D6.C9
0043 5C.40.40
Alberto Romano Schiesari – www.profars.com
443
(A) Exercises 210-225 (Representing fields in bytes)
* Exercise 210: Exercise 211: Exercise 212: Exercise 213: Exercise 214: Exercise 215: Exercise 216: Exercise 217: Exercise 218: Exercise 219: Exercise 220: Exercise 221: Exercise 222: Exercise 223: Exercise 224: Exercise 225: DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Address Contents 3C'*' X'123' X'-123' X'1AB2C3' X'1AB2F4G3' XL3'12D' XL3'AABBCCDDEE' X'1,22,333,4444' XL2'1,22,333' 2X'1,22,333' 0046 5C.5C.5C
0049 01.23
*** error *** 004B 1A.B2.C3
*** error *** 004E 00.01.2D
0051 CC.DD.EE
0054 01.22.03.33.44.44
005A 00.01.00.22.03.33
0060 01.22.03.33.01.22.03.33
2XL2'1,22' B'01010101' B'1' 0068 00.01.00.22.00.01.00.22
0070 55 0071 01 BL2'1111' B'1,1111111111' 0072 00.0F
0074 01.03.FF
BL2'1,1111111111' 0077 00.01.03.FF
Alberto Romano Schiesari – www.profars.com
444
(A) Exercises 226-239 (Representing fields in bytes)
* Exercise 226: Exercise 227: Exercise 228: Exercise 229: Exercise 230: Exercise 230: Exercise 231: Exercise 232: Exercise 233: Exercise 234: Exercise 235: Exercise 236: Exercise 237: Exercise 238: Exercise 239: DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC 2B'1000' 2BL2'1000' F'10' F'+10' F'-10' F'-15,+16' 2F'22' 2F'33,44' FL3'258' 2FL1'255' F'128000' H'10' H'+10' H'-10' H'-15,+16' Address Contents 007B 08.08
007D 00.08.00.08
0081 00.00.00 (align) 0084 00.00.00.0A
0088 00.00.00.0A
008C FF.FF.FF.F6
0090 FF.FF.FF.F1.00.00.00.10
0098 00.00.00.16.00.00.00.16
00A0 00.00.00.21.00.00.00.2C
00.00.00.21.00.00.00.2C
00B0 00.01.02
00B3 FF.FF
00B5 00.00.00 (align) 00B8 00.01.F4.00
00BC 00.0A
00BE 00.0A
00C0 FF.F6
00C2 FF.F1.00.10
Alberto Romano Schiesari – www.profars.com
445
(A) Exercises 240-254 (Representing fields in bytes)
* Exercise 240: Exercise 241: Exercise 242: Exercise 243: Exercise 244: Exercise 245: Exercise 246: Exercise 247: Exercise 248: Exercise 249: Exercise 250: Exercise 251: Exercise 252: Exercise 253: Exercise 254: Address Contents DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC 2H'22' 2H'33,44' HL3'258' 2HL1'255' H'128000' P'123' P'+123' P'-123' PL4'456' 00C6 00.16.00.16
00CA 00.21.00.2C.00.21.00.2C
00D2 00.01.02
00D5 FF.FF
00D7 00 (align) 00D8 F4.00
00DA 12.3C
00DC 12.3C
00DE 12.3D
00E0 00.00.45.6C
PL1'789' P'1,-22,333,-4444' 00E4 9C 00E5 1C.02.2D.33.3C.04.44.4D
PL2'1,-22,333,-4444' 00ED 00.1C.02.2D.33.3C.44.4D
3P'0' PL3'0' 2P'1,22,333' 00F5 0C.0C.0C
00F8 00.00.0C
00FB 1C.02.2C.33.3C.1C.02.2C.33.3C
Alberto Romano Schiesari – www.profars.com
446
* Exercise 255: Exercise 256: Exercise 257: Exercise 258: Exercise 259: Exercise 260: Exercise 261: Exercise 262: Exercise 263: Exercise 264: Exercise 265: Exercise 266:
(A) Exercises 255-266 (Representing fields in bytes)
Address Contents DC DC DC DC DC DC DC DC DC DC DC DC 2PL2'1,22,333' Z'123' Z'+123' Z'-123' 0105 00.1C.02.2C.33.3C
00.1C.02.2C.33.3C
0111 F1.F2.C3
0114 F1.F2.C3
0117 F1.F2.D3
ZL4'456' ZL1'789' 011A F0.F4.F5.C6
011E C9 Z'1,-22,333,-4444' 011F ZL3'1,-22,333,-4444' 0129 F1.F2.D2.F3.F3.C3.F4.F4.F4.D4
F0.F0.C1.F0.F2.D2.F3.F3.C3
3Z'0' ZL3'0' 2Z'1,22,333' 2ZL3'1,22,333' F4.F4.F4.D4
0135 C0.C0.C0
0138 F0.F0.F0
013B C1.F2.C2.F3.F3.C3
C1.F2.C2.F3.F3.C3
0147 F0.F0.C1.F0.F2.C2.F3.F3.C3
F0.F0.C1.F0.F2.C2.F3.F3.C3
Alberto Romano Schiesari – www.profars.com
447
(A) Exercises 267-279 (Representing fields in bytes)
* Address Contents Exercise 267: SIMBZZ DC Exercise 268: SIMBAA DC Exercise 269: SIMBBB DC Exercise 270: SIMBCC DC Exercise 271: SIMBDD DC Exercise 272: SIMBEE DC Exercise 273: SIMBFF DS Exercise 274: SIMBGG DC Exercise 275: SIMBHH DC Exercise 276: SIMBII DC Exercise 277: SIMBJJ DC Exercise 278: SIMBKK DC Exercise 279: SIMBLL DC A(0) A(127) A(X'8000') A(B'1111') A(C'*') A(*) CL17 0159 00.00.00 (align) 015C 00.00.00.00
0160 00.00.00.7F
0164 00.00.80.00
0168 00.00.00.0F
016C 00.00.00.5C
0170 00.00.01.70
0174 ??.??.??.??.??.??.??.??.??
??.??.??.??.??.??.??.??
0185 00.00.00 (align) A(*) A(SIMBGG) 0188 00.00.01.88
018C 00.00.01.88
A(SIMBAA+12) 0190 00.00.01.6C
A(SIMBII-SIMBBB) 0194 00.00.00.2C
AL1(*-SIMBKK) 5AL1(*-SIMBLL) 0198 00 0199 00.01.02.03.04
Alberto Romano Schiesari – www.profars.com
448
(A) Exercises 280-290 (Representing fields in bytes)
* Exercise 280: SIMBMM Exercise 281: SIMBNN Exercise 282: SIMBOO Exercise 283: SIMBPP Exercise 284: SIMBQQ Exercise 285: SIMBRR Exercise 286: SIMBSS Exercise 287: SIMBTT DC DC DC DC DC DC DC DC Exercise 288: SIMBUU DC Exercise 289: SIMBVV Exercise 290: SIMBWW DC DC Endereço Conteúdo AL2(3,5,7) A(SIMBII+5*2) A(SIMBNN+X'80000000') 4AL2(*-SIMBPP) A(SIMBVV) A(SIMBKK,SIMBJJ) A(SIMBTT+40) A(SIMBUU,*,80) 2A(*-SIMBUU) A(C'AMO') A(X'7FFFFFFF') 019E 00.03.00.05.00.07
01A4 00.00.01.9A
01A8 80.00.01.A4
01AC 00.00.00.02.00.04
00.06
01B4 00.00.01.D8
01B8 00.00.01.98
00.00.01.94
01C0 00.00.01.EC
01C4 00.00.01.D0
00.00.01.C8
00.00.00.50
01D0 00.00.00.00
00.00.00.04
01D8 00.C1.D4.D6
01DC 7F.FF.FF.FF
Alberto Romano Schiesari – www.profars.com
449
(A) Exercises 291-299 (Representing fields in bytes)
* Address Contents Exercise 291: YY1 Exercise 292: YY2 Exercise 293: YY3 Exercise 294: SS1 Exercise 295: SS2 Exercise 296: SS3 Exercise 297: SS4 Exercise 299: SS6 DC DC DC DC DC DC DC Exercise 298: SS5 DC DC Y(SIMBWW) Y(10) Y(L'YY2) S(SIMBAA) S(SS1) S(10) S(*) X'1,1',B'1,1',C'1,1' 01E0 01.DC
01E2 00.0A
01E4 00.02
01E6 91.60
01E8 91.E6
01EA 00.0A
01EC 91.EC
01EE 00.00 (align) A(125),F'33',C'*',2H'6,18' 01F0 00.00.00.7D
00.00.00.21
5C 00 (align) 00.06.00.12
00.06.00.12
0202 01.01.01.01
F1.6B.F1
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450
(A) Exercise 300 (Representing fields in bytes)
* Endereço Conteúdo * * * * * * * * * * * Exercise 300: * * * * LAST DC 256AL1(255+LAST-*) 0209 FF.FE.FD.FC.FB.FA.F9.F8.F7.F6.F5.F4.F3.F2.F1.F0
0219 EF.EE.ED.EC.EB.EA.E9.E8.E7.E6.E5.E4.E3.E2.E1.E0
0229 DF.DE.DD.DC.DB.DA.D9.D8.D7.D6.D5.D4.D3.D2.D1.D0
0239 CF.CE.CD.CC.CB.CA.C9.C8.C7.C6.C5.C4.C3.C2.C1.C0
0249 BF.BE.BD.BC.BB.BA.B9.B8.B7.B6.B5.B4.B3.B2.B1.B0
0259 AF.AE.AD.AC.AB.AA.A9.A8.A7.A6.A5.A4.A3.A2.A1.A0
0269 9F.9E.9D.9C.9B.9A.99.98.97.96.95.94.93.92.91.90
0279 8F.8E.8D.8C.8B.8A.89.88.87.86.85.84.83.82.81.80
0289 7F.7E.7D.7C.7B.7A.79.78.77.76.75.74.73.72.71.70
0299 6F.6E.6D.6C.6B.6A.69.68.67.66.65.64.63.62.61.60
02A9 5F.5E.5D.5C.5B.5A.59.58.57.56.55.54.53.52.51.50
02B9 4F.4E.4D.4C.4B.4A.49.48.47.46.45.44.43.42.41.40
02C9 3F.3E.3D.3C.3B.3A.39.38.37.36.35.34.33.32.31.30
02D9 2F.2E.2D.2C.2B.2A.29.28.27.26.25.24.23.22.21.20
02E9 1F.1E.1D.1C.1B.1A.19.18.17.16.15.14.13.12.11.10
02F9 0F.0E.0D.0C.0B.0A.09.08.07.06.05.04.03.02.01.00
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451
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566 ----////////----////////--------////////------------//////////// Suppose the general registers with the following values: R00=00112233 R04=00000400 R08=00000800 R12=00000C00 R01=00000100 R05=00000500 R09=00000900 R13=00000D00 R02=00000200 R06=00000600 R10=00000A00 R14=00000E00 R03=00000300 R07=00000700 R11=00000B00 R15=00000F00
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452
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566 ----//////// ----////////--------////////------------////////////
1ABB - Operation code (machine code) = 1A - Mnemonic Assembler code = AR (add register) - Instruction address = X’00000000’ - Operands = 1st operand = register 11; 2nd operand = register 11 41278CF0 - Operation code (machine code) = 41 - Mnemonic Assembler code = LA (load address) - Instruction address = X’00000002’ -Operands = 1st operand = register 2; 2nd operand : index register = register 7 2nd operand : base register = register 8 2nd operand : displacement = X’CF0’ 2nd operand address = X’ 00000700’+X’00000800’+X’CF0’= X’00001BF0’ Continues...
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453
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566 ----//////// ----//////// --------////////------------////////////
0A13 - Operation code (machine code) = 0A - Mnemonic Assembler code = SVC (supervisor call) - Instruction address = X’00000006’ - Operands = supervisor call code = X’13’ = (19) 10 = open 980F3344 - Operation code (machine code) = 98 - Mnemonic Assembler code = LM (load multiple) - Instruction address = X’00000008’ -Operands = 1st operand = register 0; 3rd operand : register = register 15 (X’F’) 2nd operand : base register = register 3 2nd operand : displacement = X’344’ 2nd operand address = X’00000300’+X’344’= X’00000644’ Continues...
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454
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566 ----////////----//////// --------//////// ------------////////////
45E00CB4 - Operation code (machine code) = 45 - Mnemonic Assembler code = BAL (branch and link) - Instruction address = X’0000000C’ -Operands = 1st operand = register 14 (X’E’); 2nd operand : index register = register 0 2nd operand : base register = register 0; 2nd operand : displacement = X’CB4’ 2nd operand address = X’CB4’= X’00000CB4’ 90EC0D00 - Operation code (machine code) = 90 - Mnemonic Assembler code = STM (store multiple) - Instruction address = X’00000010’ -Operands = 1st operand = register 14 (X’E’); 3rd operand : register = register 12 (X’C’) 2nd operand : base register = register 0; 2nd operand : displacement = X’D00’ 2nd operand address = X’D00’= X’00000D00’ Continues...
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455
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566 ----////////----////////--------//////// ------------////////////
FA82305448CC - Operation code (machine code) = FA - Mnemonic Assembler code = AP (add packed) - Instruction address = X’00000014’ - 1st operand length = 9 bytes; 1st operand base register = register 3; 1st operand displacement= X’054’; 1st operand address= X’00000300’+X’054’ = X’00000354’ - 2nd operand length = 3 bytes; 2nd operand base register = register 4; 2nd operand displacement = X’8CC’; 2nd operand address= X’00000400’+X’8CC’ = X’00000CCC’ D28233445566 - Operation code (machine code) = D2 - Mnemonic Assembler code = MVC (move character) - Instruction address = X’0000001A’ - 1st operand length = 131 bytes; 1st operand base register = register 3; 1st operand displacement= X’344’; 1st operand address= X’00000300’+X’344’ = X’00000644’ - 2nd operand length = 131 bytes; 2nd operand base register = register 5; 2nd operand displacement = X566’; 2nd operand address= X’00000500’+X’566’ = X’00000A66’
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Programming Hints
Programming Hints
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457
Programming Hints
Interesting things, useful things, awful but used things, etc...
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458
Programming Hints Let’s figure out an 11K program, with only one base register PROG START 0 USING *,3 USING specified when Location Counter has zero (assembly time) LR 3,15 Load 1st and only base register (run time)
...
4K 4K 3K
Part of the program that is within the range of the base register R3; any symbol herein declared, which must be converted to Base+Displacement has R3 as base register.
This part of rhe program is outside from the range of the base register.
Any symbol herein declared, which must be converted to Base+Displacement : ERROR
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459
Programming Hints Let’s figure out an 11K program, with 2 base registers PROG START 0 USING *,3,7 USING specified when Loc. Counter has zero (assembly time) LR 3,15 Load 1st base register (run time) LA 7,2048(3) Begin loading 2nd base register (run time) LA 7,2048(3,7) Complete loading 2nd base register (run time)
...
4K 4K 3K
Part of the program that is within the range of the base register R3; any symbol herein declared, which must be converted to Base+Displacement has R3 as base register.
Part of the program that is within the range of the base register R7; any symbol herein declared, which must be converted to Base+Displacement has R7 as base register.
This part of the programt is outside the range of both base registers; any symbol herein declared, which must be converted to Base+Displacement: ERROR
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460
Programming Hints Let’s figure out an 11K program, with 3 base registers PROG START 0 USING *,3,7,6 USING specified when Loc. Counter has zero (assembly time) LR 3,15 Load 1st base register (run time) LA 7,2048(3) Begin loading 2nd base register (run time) LA 7,2048(3,7) Complete loading 2nd base register (run time) LA 6,1 Begin loading 2nd base register (run time) LA 6,4095(6,7) Complete loading 2nd base register (run time)
...
4K 4K 3K
Part of the program within the range of the base register R3
Part of the program within the range of the base register R7 Part of the program within the range of the base register R6
“Part in excess” for base reg R7
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461
Programming Hints Let’s figure out a 1000K program, with only one base register PROG START 0 USING *,3 USING specified when Location Counter has zero (assembly time) LR 3,15 Load 1st and only base register (run time)
...
4K 996K
Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR
Alberto Romano Schiesari – www.profars.com
462
Programming Hints Let’s figure out a 1000K program, with only one base register
4K Instructions Areas 996K
Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR
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463
Programming Hints Let’s figure out a 1000K program, with only one base register
Instrutions Areas (with base reg.) Areas (WITHOUT base register)
END (source program finish) Implicit (END) LTORG LITERALS declared by LTORG ( without base) Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR
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464
Programming Hints Let’s figure out a 1000K program, with only one base register
Instruction Areas (with base) Areas (WITHOUT base)
END (source program finish) Explicitly declared (by programmer) LTORG LITERALS declared by LTORG (with base) Areas still WITH base Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR
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465
Programming Hints Let’s figure out a 1000K program, with only one base register
Instruction Areas (with base) Areas (WITHOUT base)
END (source program finish) Explicitly declared (by programmer) LTORG LITERALS declared by LTORG (with base) Areas still WITH base Let’s take a good and detailed look
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466
Programming Hints Let’s figure out a 1000K program, with only one base register
Instructions Areas L T O R G Literals (with base) Início das áreas “grandes” (supor: 1os 100 bytes de uma área de 500000 bytes, por ex. TABXX)
TABXX DS 1000CL500
Restante da área (499900 bytes) + uma 2ª área grande TABYY + Uma pequena área de 4 bytes (XYZ)
- instructions, - areas before LTORG, - literals and
- the beginning of the “big” areas (specifically the first 100 bytes from TABXX)
Are within the range of the base register.
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467
Programming Hints Let’s figure out a 1000K program, with only one base register
Instruções Áreas L T O R G Literais (com base)
TABXX DS 1000CL500 100 1os bytes de TABXX Demias 499900 bytes de TABXX TABYY DS CL 1000CL52 XYZ DS CL4 - 1st 100 bytes of TABXX Are within the range of the base register - Next 499900 bytes of TABXX - All 520000 bytes of TABYY - 4 bytes of XYZ Are outside the range of the base register
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468
Programming Hints Let’s figure out a 1000K program, with only one base register
Instructions Areas L T O R G Literals (with base)
TABXX DS 1000CL500 1st 100 bytes of TABXX Demias 499900 bytes de TABXX TABYY DS CL 1000CL52 XYZ DS CL4 LA R9,TABXX the range of the base register L R9,=A(TABXX) OK! TABXX (TABXX address ís the address of the leftmost byte of TABXX) is within OK! The literal with TABXX address is within the range of the base register LA R9,TABXX+1 OK! TABXX+1 is na address within the range of the base register L R9,=A(TABXX+1) OK! The literal with TABXX+1 address is within the range of the base register LA R9,TABXX+99 OK! TABXX+99 is an address within the range of the base register L R9,=A(TABXX+99) OK! The literal with TABXX+99 address is within the range of the base register
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469
Programming Hints Let’s figure out a 1000K program, with only one base register
Instruções Áreas L T O R G Literais (com base)
TABXX DS 1000CL500 100 1os bytes de TABXX Demias 499900 bytes de TABXX TABYY DS CL 1000CL52 XYZ DS CL4 LA R9,TABXX+100 ERROR!!!
TABXX+100 é o 101º. Byte de TABXX, e, portanto, o primeiro a NÃO ser servido pelo registrador base.
L R9,=A(TABXX+100) OK! A literal que tem o endereço de TABXX+100 está dentro do alcance do registrador base LA R9,TABYY base L R9,=A(TABYY) base ERROR!!
TABYY é um endereço que NÃO está dentro do alcance do registrador OK! A literal que tem o endereço de TABYY está dentro do alcance do registrador LA R9,XYZ L R9,=A(XYZ) base ERROR!!!
XYZ é um endereço que NÃO está dentro do alcance do registrador base OK! A literal que tem o endereço de XYZ está dentro do alcance do registrador
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470
Programming Hints
Programs with 1 base register Assembler specification and runtime load
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471
Programming Hints Loading base register with entry point address with LR PROG START 0 USING *,3 LR 3,15 LOAD FIRST AND ONLY BASE REGISTER * REG 3 CONTAINS THE ENTRY POINT ADDRESS * THIS TYPE OF LOAD (WITH LR) IS OFTEN USED IN MVS Loading base register with entry point address with BALR+BCTR+BCTR PROG START 0 USING *,3 BALR 3,0 LOAD INTO R3 THE ADDRESS JUST AFTER BALR BCTR 3,0 SUBTRACTS 1 BCTR 3,0 SUBTRACTS 1 ONCE MORE * HERE REGISTER 3 IS OK; * IT HAS THE ENTRY POINT ADDRESS
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472
Programming Hints
Programs with 2 base registers Assembler specification and runtime load
Alberto Romano Schiesari – www.profars.com
473
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4096(4) LOAD INTO R4 THE VALUE OF R3 + 4096 NO! Why not? Because maximum displacement is 4095 (X ’ FFF ’ ) !!!
Assembly error !
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474
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA+LA+AR PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG 4 LA 4,4095(4) ADD 4095 * RESULT = 4096 AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X ’ 001000 ’ * OK ! R3 AND R4 PROPERLY LOADED !
Alberto Romano Schiesari – www.profars.com
475
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA+LA+AR PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4095 LOAD NUMBER 4095 INTO REG 4 LA 4,1(4) ADD 1 * RESULT = 4096 AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X ’ 001000 ’ * OK ! R3 AND R4 PROPERLY LOADED !
Alberto Romano Schiesari – www.profars.com
476
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA+LA PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG 4 LA 4,4095(3,4) ADD 4095 + ENTRY POINT * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X ’ 001000 ’ * OK ! R3 AND R4 PROPERLY LOADED !
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477
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA+LA PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,2048 LOAD NUMBER 1 INTO REG 4 LA 4,2048(3,4) ADD 2048 + ENTRY POINT * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X ’ 001000 ’ * OK ! R3 AND R4 PROPERLY LOADED !
Alberto Romano Schiesari – www.profars.com
478
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA+LA PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1000 LOAD R4 WITH # 1000 LA 4,3096(3,4) ADD 3096 + ENTRY POINT * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X ’ 001000 ’ * OK ! R3 AND R4 PROPERLY LOADED !
Alberto Romano Schiesari – www.profars.com
479
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with LA PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,PROG+4096 LOAD “ DIRECTLY ” ENTRY POINT + 4096 NO! Why not?
Because the address PROG+40096 isn ’ t in the range of first base register (R3), so far the only one correctly loaded. Assembly error.
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480
PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS L 4,=A(PROG+4096) LOAD “ DIRECTLY ” ENTRY POINT + 4096 IT DEPENDS ON ... ! The contents of the literal is being loaded into R4.
If the literal is outside the range of the FIRST BASE REGISTER (R3) (THE ONLY ONE CORRECTLY LOADED SO FAR), THEN this is INVALID to prepare the second base register. Assembly error. (case 1) ELSE, this way (using the literal) is VALID. (case 2)
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with L Alberto Romano Schiesari – www.profars.com
481
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with L CASE 1 : Literal is outside range of the 1st base register (R3), and it is the only one prepared so far. You can ’ t do this way ! Assembly error.
PROG START 0 USING *,3,4 LR 3,15 L 4,=A(PROG+4096) ... ( L needs the 2nd base register prepared, but... L prepares the 2nd base register! Execution time error!) END ( literals are declared after END) ... =A(PROG+4096)
This part is served by 1st base register Program = 8k This part is served by 2nd base register
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482
Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address + 4096 with L CASE 2 : Literal is in the range of the first base register (R3), and it is the only one prepared so far, so you can do this way.
PROG START 0 USING *,3,4 LR 3,15 L 4,=A(PROG+4096) B SKIP LTORG =A(PROG+4096) SKIP ...
This part is served by 1st base register Forces the literal to be defined here.
Program = 8k
END (other literals declared here) ... =...
=...
This part is served by 2nd base register
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483
THE END
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484