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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

ARM920T Processor

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Processor

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The ARM920T processor is a member of the ARM9TDMI family of general purpose microprocessors

– Includes the ARM9TDMI core plus cache and MMU.

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ARM9TDMI processor:

– Harvard architecture • Increases available memory bandwith • Simultaneous access to instruction and data memory can be achieved – 5-stage pipeline – 32-bit ARM instruction set and 16-bit THUMB instruction set.

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Processor

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ARM7TDMI Instruction Fetch

FETCH

Thumb

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ARM decompress ARM decode Reg Select Reg Read Shift ALU Reg Write

DECODE EXECUTE

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ARM9TDMI Instruction Fetch

FETCH

ARM or Thumb Inst Decode Reg Decode Reg Read

DECODE

Shift + ALU

EXECUTE

Memory Access

MEMORY

Reg Write

WRITE

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Processor

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Cached Processor for Platform OS Applications

– 16K Instruction & Data Caches – ARMv4 MMU for: PalmOS, EPOC, Linux & WindowsCE – Includes support for Coprocessor and ETM

16K I Cache MMU ARM9TDMI CORE Write Buffer 16K D Cache MMU Control Logic & BIU Coprocessor, ETM9 & AMBA ASB Interfaces

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T MMU

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What is an MMU ?

– Memory Management Unit • Controls memory access permissions • Translates virtual addresses into physical addresses – MMU consists of • Translation Look-aside Buffer (TLB) – Cache of recently used page translations • Hardware for page table walks – Updates TLB • Access control logic – If MMU is disabled • External address bus will output virtual addresses directly

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T MMU

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Virtual to Physical Address Mapping

Virtual Memory

Process D Process C Process B Process A Manager

Translation and checking mechanism.

MMU I TLB D TLB Protection & Aborts

Physical Memory

Translation Tables VRAM RAM ROM RAM RAM RAM 6

AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T MMU

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Translation Look-aside Buffer acts as a cache of recent VA to PA translations

– Provides translation and access permission information for most memory accesses – For TLB misses, the translation table walking hardware retrieves the information from the translation table in physical memory and the TLB is updated – If the TLB is full, a value will be overwritten using a cyclic scheme –

Translation Tables resides in physical memory

– Level 1 table is a list of 4096 translations, indexed by bits 31:20 of the virtual address – Entries contain a pointer to a 1MB section of physical memory along with attribute information, or … – A pointer to the base address of a another table, containing pointers to smaller pages of physical memory

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T MMU

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Translation Process

– Performed by hardware and is transparent to the user • Translation tables created by software

Virtual address Check if TLB contains virtual address yes Get physical address no Do translation table walk Get physical address Update TLB 8

AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T MMU

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Two Translation Lookaside Buffers (TLBs)

• 64-entry Instruction TLB • 64-entry Data TLB •

Two-level Hardware table walking :

• Address translation • Access control logic with permissions •

Highly flexible mapping scheme - supports:

• 1MB sections (with permissions) • 64kB large pages (permissions for each subpage of a page) • 4kB small pages (permissions for each subpage of a page) • 1kB tiny pages (with permissions)

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T MMU

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MMU usage in Linux

– Allows Memory mapping (physical to virtual address) – Allows memory allocation – Allows to safely run several processes, each one has a protected memory area.

– Provides protection against direct access to a peripheral’s physical address

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Caches

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What is a cache ?

– Small fast memory, local to the processor – Holds copies of recently accessed memory locations – Relies on memory re-use – Only improves performance for slow memory or narrow memory – Reduces bus bandwidth requirements – Reduces power consumption

CPU Cache Bus Interface

Address Data

External Memory 11

AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Caches

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16KB instruction and data caches 512 lines of 8 words arranged as a 64-way set-associative cache MMU must be enabled to enable Dcache

TAG = MVA [ 31 : 8 ] 8 words 8 words 8 words 8 words 8 words 8 words 8 words TAG 8 words 1 2 3 4 5 6 7 8 64 lines

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Caches

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Cache hit and miss

– Cache hit, if region is cachable, data are returned from the cache – Cache miss, an eight-word linefill is performed replacing another entry –

Replacement algorithm

– Random by default – Round-Robin : entries of each segment are replaced sequentially. More efficient.

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Caches operate at processor speed

– Max processor speed is 180 Mhz – Max AMBA ASB speed is 60 Mhz

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AT91 ARM 7 & ARM 9 MICROCONTROLLERS

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ARM920T Caches

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16-word (64Bytes) write buffer

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Lockdown features

– Lockdown instruction and data caches independently with a granularity of 1/64 th of cache – Must lockdown the associated TLB entry in the TLB to avoid page table walks during accesses to the locked data or instruction – Provide optimum and predictable execution time

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