Transcript Chapter 4: The Embedded Computing Platform

Chapter 4:
The Embedded Computing
Platform
Computer as Components
Embedded Systems Laboratory
Dept. of Computer Science & Engineering
National Sun Yat-Sen University
Presenter: Chung-Fu Kao
Chapter view


CPU bus, I/O devices, and interfacing
The CPU system as a framework for
understanding design methodology

Development environments and debugging

An alarm clock design
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Typical PC hardware platform
CPU
CPU bus
intr
ctrl
DMA
controller
bus
interface
memory
device
high-speed bus
timers
bus
interface
low-speed bus
device
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Introduction

Computer platform
 Microprocessors
 I/O devices
 Memory

How to interconnect microprocessors and devices using
the CPU bus
CPU
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?
device
keyboard
device
display
device
memory
The Embedded Computing System© C.-F. Kao
The CPU bus

Wire vs. bus
 Wire: a 1-bit line between two devices
wire
n
bus
 Bus: a collection of wires with a protocol
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Bus protocol

The simplest bus protocol is the four-cycle
handshake
enq
1
3
2
ack
data
Action
time
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Typical bus signals

Clock
 provides synchronization to the bus components

R/W’
 true when bus is reading

Address
 a n1-bit bundle

Data
 a n2-bit bundle

Data ready’
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A typical microprocessor bus

the CPU can read/write devices or memory, bus
devices of memory cannot initiate a transfer
Device 1
Device 1
clock
R/W’
data rdy’
address
data
CPU
memory
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Timing diagrams
one
A
B
rising
zero
falling
10 ns
changing
stable
Timing
constraint
C
time
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A simple transfer example
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Transfer with ‘wait’ states
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State diagrams for the bus read
transaction
Get
data
Done
Address
See ack
(start here)
Send
data
ack
Address
(start here)
Wait
Wait
CPU
Device
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Release
ack
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Bus read state diagram
Get
data
Done
one data send/receive
per transfer cycle
See ack
Address
(start here)
How to speedup
the transfer ?
Wait
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Burst transfer
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Bus architectures: Tri-state design

1-bit tri-state design
enable
data_out
tri_out
data_in

System tri-state bus
…
…
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…
Bus architectures: Multiplexing design
Master(s)
AGNTx1
AREQx1
AREQx2
AREQx3
BLOK
Data (W)
MUX
Data (R)
MUX
AGNTx2
ASB
Arbiter
BWAIT
BnRES/
BCLK
AGNTx3
select
Address bus
Data bus
DSEL 1
BA[31:0
DSEL 2
BWRITE
Address
MUX
Response
MUX
Control
MUX
BSIZE[1:0]
BPROT[1:0]
BnRES/
BCLK
ASB
Decoder
DSEL n
BWAIT
BERROR
BLAST
Select-1
Select-2
[31:28]
Decoder
Slave(s)
Control (write, transfer type, size)
Response (wait, last, error)
End of Chapter 4.2.1
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BTRAN[1:0]
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I/O techniques

Programmed I/O
 data are exchanged between CPU and I/O
 CPU must wait until the I/O operation is complete

Interrupt-driven I/O
 CPU can continues to execute other instructions
before I/O operation has completed

Direct Memory Access (DMA)
 CPU does not involve the I/O transfer
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DMA: Direct Memory Access

The DMA controller includes 3 registers
 a starting address register
 a length register
Data count
 a status register
Data register
Address register

Cycle stealing
DMA REQ
DMA ACK
INTR
Read
Write
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Control Logic
Possible DMA configuration
CPU
DMA
module
. . .
I/O
I/O
MEM
(a) Single-Bus, Detached DMA
CPU
DMA
DMA
module
MEM
module
I/O
I/O
I/O
(b) Single-Bus, Integrated DMA-I/O
System bus
CPU
DMA
module
MEM
I/O bus
I/O
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I/O
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Computing
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(c) I/O
bus
I/O
Bus example: ARM bus

ARM supports an on-chip bus: AMBA
 Advanced Microcontroller Bus Architecture
Arbiter
BIU: Bus Interface Unit
CPU
……
Master BIU
Master N
Other
APB slaves
Timer
Master BIU
Slave BIU
Slave BIU
APB
Bridge
AHB/ASB BUS
Decoder
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On-chip
RAM
Slave BIU
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APB BUS
Interrupt
Controller
LED
Slave BIU
AMBA features

Pipelining
 only AHB or ASB

Burst transfers
 1, 4, 8, 16-beat transfer

Split transactions
 release the current transfer

Multiple bus masters
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Bus components devices
Arbiter
BIU: Bus Interface Unit
CPU
……
Master BIU
Master N
Other
APB slaves
Timer
Master BIU
Slave BIU
Slave BIU
APB
Bridge
AHB/ASB BUS
Decoder
On-chip
RAM
Slave BIU
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APB BUS
Interrupt
Controller
LED
Slave BIU
Memory device organization


The most basic way to characterize a memory is
by its capacity
A 4-Mbit memory aspect ratio :
20
 as a 1M x 4-bit array, MAX of 2
different
addresses
22
 as a 4M x 1-bit array, MAX of 2 different
addresses
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Random-Access Memories (RAMs)

There are two major categories of RAM:
 static RAM (SRAM)
 dynamic RAM (DRAM)

The differences between SRAM and DRAM
 SRAM is faster than DRAM
 SRAM consumes more power than DRAM
 more DRAM can be put on a single chip
 DRAM values must be periodically refreshed
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SRAM


SRAM doesn’t need CLOCK signal
Block diagram
15
address
SRAM
chip select
8
output enable
write enable

Timing diagram
Data_in
8
32K x 8
CS’
R/W’
Adrs
Data
From SRAM
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From CPU
Data_out
DRAM

Single transistor and capacitor per bit
address
chip select
output enable
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DRAM
8
write enable
Data_in 8



CPU address bus is split into a row and a column
address
NO clock
Refreshed
 CAS-before-RAS refresh
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Data_out
Other DRAMs

FPM DRAM
 fast page mode switch (burst)

EDO DRAM
 extended data out

SDRAM
 synchronous DRAM
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Read-Only Memories (ROMs)



Read only, cannot write any data to ROMs
ROMs can store data without any power
ROM size
 height: n input line, consists 2 addressable
n
entries
 width: the number of bits in each addressable
entry

A ROM can encode a collection of logic functions
directly from the truth table
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ROMs


Mask ROM
Programmable ROM (PROM)
 write once

Erasable Programmable ROM (EPROM)
 can be erased using UV light and then
reprogrammed

Electrically Erasable Programmable ROM
 using high voltages for erasure and
reprogramming

Flash ROM
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I/O devices






Timers / counters
A/D and D/A converters
Keyboards
LEDs
Displays
Touchscreens
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Timers and counters

Very similar:
 a timer is incremented by a periodic signal
 a counter is incremented by an asynchronous,
occasional signal

Rollover causes interrupt
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Watchdog timer


Watchdog timer is periodically reset by system
timer
If watchdog is not reset, it generates an
interrupt to reset the host (CPU)
reset
CPU
time-out
Watchdog
Timer
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A/D and D/A converters



Analog/digital (A/D) or digital/analog (D/A)
converters (ADC/DAC)
To interface non-digital devices to embedded
systems
A typical A/D interface has two major digital
inputs
 a data port
 a clock input
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DAC
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ADC
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Keyboards

Switch de-bouncing

Encoded keyboard
 An array of switches is read by an encoder
row
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LEDs

Light-emitting diodes (LEDs)
+
+5 V
Anode (+)
Cathode (-)
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Displays

Common use: 7-segment LCD display

Other high-resolution displays
 cathode ray tube (CRT)
 liquid crystal display (LCD)
• passive matrix
• active matrix
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Touchscreens

Includes input and output device

Input device is a two-dimensional voltmeter
X
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Touchscreen position sensing
Push
↓
ADC
conductive sheets
voltage
spacer ball
end of chapter 4.5
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Design with microprocessors

System architecture

Hardware design

The PC as a platform

Debugging

Manufacturing testing
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System architecture – Hardware

Hardware elements
 CPU
 bus
 memory
 I/O devices: networking, sensors, etc.
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System architecture – Software

Functional description must be broken into
pieces:
 conceptual organization
 performance
 testability
 maintenance

Consider the H/W-S/W trade-off
 using DMA to move data rather than a
programmed loop
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Hardware design


Hardware: evaluation board
Software:
 cross compiler:
• compiles code on host for target system.
 cross debugger:
• displays target state, allows target system to be controlled.
target
system
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host system
serial line
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Evaluation board
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The PC as a platform

Advantages:
 cheap and easy to get
 rich and familiar software environment

Disadvantages:
 requires a lot of hardware resources
 not well-adapted to real-time
 high power consumption
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Typical PC hardware platform
CPU
CPU bus
intr
ctrl
DMA
controller
bus
interface
memory
device
high-speed bus
timers
bus
interface
low-speed bus
device
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Typical busses

ISA (Industry Standard Architecture)
 original IBM PC bus, low-speed by today’s
standard.

PCI (Peripheral Component Interconnect)
 standard for high-speed interfacing
 33 or 66 MHz.


USB (Universal Serial Bus),
IEEE 1394 (Firewire)
 relatively low-cost serial interface with high speed.
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Software elements

IBM PC uses BIOS (Basic I/O System) to
implement low-level functions:
 boot-up
 minimal device drivers

BIOS has become a generic term for the lowestlevel system software
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Debugging embedded systems

Challenges:
 target system may be hard to observe
 target may be hard to control
 may be hard to generate realistic inputs
 setup sequence may be complex
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Software debuggers



A monitor program residing on the target
provides basic debugger functions
Debugger should have a minimal footprint in
memory
User program must be careful not to destroy
debugger program, but , should be able to
recover from some damage caused by user code
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Breakpoints


A breakpoint allows the user to stop execution,
examine system state, and change state
Replace the breakpointed instruction with a
subroutine call to the monitor program
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ARM breakpoints
0x400
0x404
0x408
0x40c
MUL r4,r6,r6
ADD r2,r2,r4
ADD r0,r0,#1
B loop
uninstrumented code
0x400
0x404
0x408
0x40c
code with breakpoint
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MUL r4,r6,r6
ADD r2,r2,r4
ADD r0,r0,#1
BL bkpoint
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Breakpoint handler actions



Save registers
Allow user to examine machine
Before returning, restore system state
 safest way to execute the instruction is to replace
it and execute in place
 put another breakpoint after the replaced
breakpoint to allow restoring the original
breakpoint (pp. 222-223)
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In-circuit emulators


A microprocessor in-circuit emulator is a
specially-instrumented microprocessor
Allows you to stop execution, examine CPU state,
modify registers
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Logic analyzers

A logic analyzer is an array of low-grade
oscilloscopes:
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Manufacturing testing


Goal: ensure that manufacturing produces
defect-free copies of the design
Can test by comparing unit being tested to the
expected behavior
 but running tests is expensive

Maximize confidence while minimizing testing
cost
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Testing concepts

Yield: proportion of manufactured systems that
work
 proper manufacturing maximizes yield
 proper testing accurately estimates yield

Field return: defective unit that leaves the
factory.
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Faults



Manufacturing problems can be caused by many
thing
Fault model: model that predicts effects of a
particular type of fault
Fault coverage: proportion of possible faults
found by a set of test
 having a fault model allows us to determine fault
coverage
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Software vs. hardware testing

When testing code, we have no fault model
 we verify the implementation, not the
manufacturing
 simple tests work well to verify software
manufacturing

Hardware requires manufacturing tests in
addition to implementation verification
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Hardware fault models

Stuck-at 0/1 fault model:
 output of gate is always 0/1
01
0
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Combinational testing


Every gate can be stuck-at-0, stuck-at-1
Usually test for single stuck-at-faults
 one fault at a time
 multiple faults can mask each other

We can generate a test for a gate by:
 controlling the gate’s input
 observing the gate’s output through other gates
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Sequential testing


A state machine is combinational logic +
registers
Sequential testing is considerably harder
 a single stuck-at fault affects the machine on
every cycle
 fault behavior on one cycle can be masked by
same fault on other cycles
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Scan chains

A scannable register operates in two modes:
 normal
 scan
• forms an element in a shift register
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Scan chain cell
Scan
output
Input pin
EXTEST
INTEST
SEL
MUX
scan
SEL
BSR
MUX
Scan input
Shift
clock
PDR
Update
clock
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Input signal
to logic
Boundary scan

IEEE Std. 1149.1 JTAG boundary scan
Serial
data in
Serial
data out
Serial test interconnect
System interconnect
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Embedded ICE
Microprocessor Core
mode
external
debug
clock
address
data
Interface
ICE
breakpoint
Breakpoint
Scan Register
BDU
Bypass Register
Select Unit
TDI
TMS
TCK
Instruction
Register
Decode
Logic
TAP
Controller
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MUX
TDO