Transcript Diapositiva 1 - Istituto Nazionale di Fisica Nucleare

Robustness of SRAM Memories
Universitat Politecnica de Catalunya
(UPC)
Barcelona
Spain
Ioana Vatajelu
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Overview
Problem Statement
SB-SI Method of Statistical Failure Analysis
Failure Analysis of the 6T SRAM cell
Parametric Yield of the 6T SRAM memory array
Conclusions
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Overview
Problem Statement
SB-SI Method of Statistical Failure Analysis
Failure Analysis of the 6T SRAM cell
Parametric Yield of the 6T SRAM memory array
Conclusions
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Problem Statement
SRAM bit cell:
• Minimum size transistors
–> high sensitivity to process variability
– Inter-die
– Intra-die
Wafer to wafer
Die to die
• Systematic
• Random (RDF & LER)
asymmetric transistors strengths
Parametric Failures
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Problem Statement
Pull - up MOS
Pull - down MOS
access MOS
σ [%] Vdd W[nm] σ [V] 6σ [V] W[nm] σ [V] 6σ [V] W[nm] σ [V] 6σ [V]
45nm
32nm
4
6
15
8
22nm 15
30
10
16nm 20
1.1
94
1
67
0.95
46
0.087 0.523
0.051 0.306
0.096 0.573
33
0.191 1.147
0.069 0.412
0.137 0.823
0.9
40
18nm
13nm
33
58
39
58
0.023 0.141
0.035 0.209
196
140
40
0.7
29
0.067 0.400
0.117 0.703
0.079 0.473
0.117 0.703
0.026 0.157
96
0.065 0.392
0.038 0.229
0.071 0.429
70
0.143 0.857
0.047 0.281
0.094 0.562
0.274 1.646
0.7
0.017 0.104
113
80
60
0.046 0.276
0.081 0.485
0.055 0.329
0.081 0.489
0.035 0.208
55
0.086 0.519
0.050 0.302
0.094 0.566
40
0.189 1.133
0.062 0.372
0.124 0.743
0.187 1.124
84
0.023 0.136
0.248 1.487
48
35
0.061 0.365
0.107 0.642
0.072 0.430
0.107 0.640
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Problem Statement
+
V
GND
DD
+
Read Mode
Hold Mode
Write Mode
1
1
1
0.8
0.8
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0.2 0.4 0.6 0.8
1
0
0
0.2 0.4 0.6 0.8
1
0
0
0.2 0.4 0.6 0.8
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
1
Problem Statement
Hold Mode
FAIL
Read Mode
FAIL
Access
FAIL
Write Mode
FAIL
1.2
1.2
1.2
1.2
1
1
1
1
0.8
0.8
0.8
0.8
0.6
0.6
0.6
0.6
0.4
0.4
0.4
0.4
0.2
0.2
0.2
0.2
0
0
0
0
-0.2
0
2
4
6
8
-10
x 10
-0.2
0
0.5
1
1.5
x 10
-10
-0.2
0
0.5
1
1.5
x 10
-10
-0.2
0
0.5
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
1
1.5
-10
x 10
Overview
Problem Statement
SB-SI Method of Statistical Failure Analysis
Failure Analysis of the 6T SRAM cell
Parametric Yield of the 6T SRAM memory array
Conclusions
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
The SB-SI Method
E.I. Vatajelu, J. Figueras, IEEE DATE 2011
Acceptance Region
Failure Region
min
Statistical
Distribution
mean
p1
Acceptance Region
Failure Region
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
The SB-SI Method
E.I. Vatajelu, J. Figueras, IEEE DATE 2011
p2
Statistical
Distribution
p2
p1
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
p1
Overview
Problem Statement
SB-SI Method of Statistical Failure Analysis
Failure Analysis of the 6T SRAM cell
Parametric Yield of the 6T SRAM memory array
Conclusions
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Failure analysis of the 6T SRAM
Static analysis - SNM
1.20E+00
Failure Probability
1.00E+00
8.00E-01
6.00E-01
4.00E-01
2.00E-01
0.00E+00
Supply Voltage [V]
-2.00E-01
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.08
0.07
0.06
0.05
45nm - sigma 4%
0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 1.10E-06 1.00E-03 5.78E-02 7.16E-01 8.95E-01 9.57E-01 9.94E-01 1.00E+00
32nm - sigma 6%
0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 1.00E-07 3.20E-05 6.70E-03 1.55E-01 8.35E-01 9.53E-01 9.86E-01 9.99E-01 1.00E+00
22nm - sigma 15% 0.00E+00 0.00E+00 0.00E+00 0.00E+00 1.00E-09 1.70E-06 1.30E-03 3.57E-02 3.81E-01 9.70E-01 9.97E-01 1.00E+00 1.00E+00 1.00E+00
16nm - sigma 20% 0.00E+00 0.00E+00 0.00E+00 3.21E-07 6.67E-06 2.10E-05 3.41E-02 2.74E-01 8.24E-01 9.99E-01 1.00E+00 1.00E+00 1.00E+00 1.00E+00
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Failure analysis of the 6T SRAM
Static analysis - SNM
1
SNMmin = 10%V DD
0.8
Pno-acc, Pfail
SNMmin = 0
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
VDD [V]
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
1
Overview
Problem Statement
SB-SI Method of Statistical Failure Analysis
Failure Analysis of the 6T SRAM cell
Parametric Yield of the 6T SRAM memory array
Conclusions
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Parametric Yield
ΔVTHNR
WL
ΔVTHPL
BL
BLB
NaL
PL
PR
NaR
ΔVTHNR
NL
L
‘1’
NR
R
‘0’
ΔVTHNL
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Parametric Yield
∆VTHNR
HOLD
Taccess = 1000ps
ACCESS
Taccess = 500ps
∆VTHPL
VDDlow = 0.5V
VDDlow = 0.3V
WRITE
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Parametric Yield
PTM
45nm 4%
6%
32nm
15%
8%
22nm 15%
30%
10%
16nm 20%
40%
33%
58%
39%
13nm
58%
18nm
UoG
[%](PR) Yield
(%)
512k
Hold (PFH) Write (PFW) σRead
Access
(PFA
)
Cell
VDDlow = 0.5V Tacceess =
Tacceess =
Tacceess =
45nm
4%
99.85
(PCELL)
1ns
1ns
1ns
0
1.03e-9
0
2.41e-9
2.87e-9
6%
94.79
9.73e-8
2.91e-8
3.34e-8
7e-8
1.02e-7
15%
66.02
32nm
1.01e-7
4.76e-7
4.2e-8
9.32e-7
7.92e-7
8%
89.29
1.06e-7PTM 1.32e-7
9.47e-8
1.31e-7
2.16e-7
15% 2.66e-6
6.93
1.56e-6
3.03e-6
9.82e-7
5.09e-6
30% 2.17e-4
0
22nm
2.15e-4
1.49e-4
7.15e-4
8.23e-4
10% 3.33e-7
55.88 1.11e-6
5.14e-7
6e-7
2.91e-7
20% 1.25E-07
1.93e-5
2.06e-5
1.57e-5
1.8e-5
3.91e-5
40% 1.39e-3
0
16nm
1.15e-3
3.33e-3
9.23e-4
4.76e-3
9.81e-6
6.3e-3
2.62e-5UoG
4.66e-2
2.43e-5
1e-2
18nm
4.19e-5
7.1e-2
13nm
1.06e-5
33%
4.34e-3
58%
2.83e-5
39%
2.04e-2
58%
1.53e-5
1.11E-09
6.25e-3
0
3.33e-5
1.13E-17
5e-2
0
4.81e-5
1.42e-2
8.32e-5
1.21e-1
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Array
(PARRAY)
512k
1.5e-3
5.21e-2
0.34
0.107
0.937
1
0.441
1
1
Yield (%)
512k
1
1
1
1
1.11e-9
0
1.13e-17
0
99.85
94.79
66.02
89.29
6.93
0
55.88
1.25e-7
0
Parametric Yield
Parametric Yield [%]
120
100
99.85
94.79
89.29
80
55.88
60
40
20
0
45 nm (4%)
32nm (6%)
22nm (8%)
16nm (10%)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Overview
Problem Statement
SB-SI Method of Statistical Failure Analysis
Failure Analysis of the 6T SRAM cell
Parametric Yield of the 6T SRAM memory array
Conclusions
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Conclusions
• SB – SI Method:
– accurate and fast
• 6T SRAM DRV:
– 45nm: DRV = 47%VDDnom; 16nm: DRV = 75.5%VDDnom
• 6T SRAM Parametric Yield
– @T = 2ns, DRV = 500mV
– 45nm: Y = 99.85%, 16nm: Y = 55.88%
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th18th 2011
Thanks for your attention!
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011