Transcript MODERN presentation template

MODERN 2010 Review
ENIAC-120003 MODERN
Ref. Technical Annex MODERN_PartB Rev2 v3.3
WP1: Giuliana Gangemi
WP3: Wilmar Heuvelman
WP5: Loris Vendrame
Coordinator: Jan van Gerwen
WP2: André Juge
WP4: Davide Pandini
Date: March 1st, 2010 (09.00 - 15.00 hrs)
Review period: m13 : m22 (2010-12-31)
Agenda (1)
General information (Jan)
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Objectives
Consortium
Relationship between workpackages
Gantt Chart
Resources planned and used
Overview of deliverables and milestones status
Cooperation, dissemination and exploitation
Project management: progress, funding problems and amendments
Other issues, Q&A
For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide)
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Relationship between workpackages
Progress, highlights and lowlights
Matrices showing ‘Domain and Technology Overview per Task and Partner’
Link with other WPs and Tasks
Technical status and achievements of deliverables (incl. changes)
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 2
Agenda (2)
For WP5 (Loris)
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Relationship between workpackages
Progress, highlights and lowlights
Technical status and achievements of deliverables (incl. changes)
Structuring of demonstrators: goals and objectives
Link with other WPs and Tasks
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 3
Objectives
The objective of the MODERN project is to develop new paradigms in
integrated circuit design that will enable the manufacturing of reliable,
low cost, low EMI, high-yield complex products using unreliable and
variable devices.
Specifically, the main goals of the project are:
 Advanced, yet accurate, models of process variations for
nanometre devices, circuits and complex architectures.
 Effective methods for evaluating the impact of process
variations on manufacturability, design reliability and circuit
performance.
o Reliability, noise, EMC/EMI.
o Timing, power and yield.
 Design methods and tools to mitigate or tolerate the effects of
process variations on those quantities applicable at the device,
circuit and architectural levels.
 Validation of the modelling and design methods and tools on a
variety of silicon demonstrators.
1
2
3 4
Layout and strain induced variability (Synopsys)
MODERN 2010 Review
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CONFIDENTIAL 4
5
Consortium
The MODERN Consortium features strong competence and expertise
in the field of advanced technologies, with a well-balanced participation
between Large Industries, SMEs, Research Centres and Universities
from all over Europe.
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 5
Relationship between workpackages
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 6
Gantt Chart (1)
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 7
Gantt Chart (2)
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 8
WP1
WP2
WP3
WP4
WP5
WP6
Actual total
Target
Planned total
technologies,
Cum. Act. total
application
Cum.Plan total
dom ains,
Actual total
Process/device
Planned total
to com pact
Cum. Act. total
m odeling
Cum.Plan total
Actual total
Physical/circuit
to RT-level: PV- Planned total
aw are and PV- Cum. Act. total
Cum.Plan total
robust
Actual total
Architectural to
Planned total
system level:
Cum. Act. total
m odeling,
analysis, and Cum.Plan total
Actual total
Test structures
Planned total
and
dem onstrators Cum. Act. total
Cum.Plan total
Actual total
Managem ent,
Planned total
dissem ination
and exploitation Cum. Act. total
Cum.Plan total
Actual total
Plan total
TOTAL
Cum. Act. total
Cum. Plan total
29
34
29
58
325
388
325
639
421
451
421
686
385
360
385
579
169
151
169
274
57
65
57
110
1,385
1,449
1,385
2,346
1
3
1
5
12
13
12
19
33
33
33
54
12
22
12
66
24
22
24
36
10
9
10
14
1
2
1
5
24
26
24
43
46
48
46
84
44
37
44
60
4
4
4
6
28
26
28
42
12
12
12
12
12
12
12
12
65
48
65
78
30
39
30
63
2
3
2
5
51
66
51
109
0
0
0
2
33
33
33
56
46
48
46
84
3
4
3
6
68
51
68
84
2
4
2
6
46
40
46
66
17
15
17
24
12
12
12
13
31
31
31
36
8
8
8
19
2
2
2
2
69
67
69
95
24
24
24
24
30
30
30
30
2
2
2
2
56
56
56
56
4
5
4
6
26
25
26
42
11
11
11
18
15
16
15
30
6
3
6
6
2
3
2
6
63
63
63
108
3
3
3
6
30
29
30
48
125
125
125
204
12
11
12
18
46
40
46
66
22
22
22
36
33
33
33
54
19
18
19
30
210 80
208 73
210 80
342 120
17
18
17
30
22
29
22
48
38
62
38
102
50
44
50
72
41
15
41
24
7
7
7
12
174
176
174
288
31. Universitat Politecnica de Catalunya
30. Sapienza Universita de Roma
28. University of Calabria
27. Alma Mater Studiorum
26. Vienna University
25. Graz University
24. Eindhoven University
23. Delft University
22. TIEMPO SAS
21. Thales SA
2
2
2
6
6
10
6
23
7
20
7
32
61
66
61
108
7
6
7
10
0
2
0
3
14
18
14
36
36
37
36
60
0
0
0
18
2
4
2
6
40
42
40
90
45
35
45
58
4
6
4
12
1
1
1
2
50 61
43 66
50 61
72 108
11
11
11
18
16
16
16
23
16
16
16
23
12 59
12 106
12 59
12 174
15
5
15
7
15
5
15 12
25
27
25
27
3
3
3
3
30 64
30 114
30 64
30 186
2
2
2
3
27
29
27
30
24
23
24
38
11
11
11
18
24
23
24
38
'(*) NOT FUNDED IN ITALY
MODERN 2010 Review
March 1st, 2011
29. The University of Glasgow
20. Synopsys Switzerland LLC
19. STMicroelectronics S.r.l.
18. Politecnico di Torino
16. (Coordinator) NXP-NL
15. Numonyx Italy Srl
13. Montpellier Laboratory
2
3
2
5
17
22
17
36
12
22
12
66
12. CEA-LETI
11. Consorzio Nazionale
9. STMicroelectronics SAS
8. IMEP-LAHC Laboratory
6. Infineon Technologies
5. Teklatech
4. Elastix
Partner - Person-month per Workpackage
3. CSEM
Title
TOTALS
W
o
r
k
P
a
c
k
a
g
e
2. AustriaMicrosystems AG
TABLE 3. PERSON-MONTH STATUS TABLE
CONTRACT N°: 120003
ACRONYM: MODERN
PERIOD: m1 to m22
10. Integrated System Development SA
1. STMicroelectronics (Grenoble2) SAS
Resources planned and used
CONFIDENTIAL 9
7
20
7
32
1
1
1
4
33
33
33
50
16
12
16
20
27
26
27
42
6
10
6
16
4
4
4
6
53
51
53
84
Overview of deliverables and milestones status (1)
Deliverables
Del. no. Deliverable name
D1.3
D2.1.1
D2.2.3
D2.3.2
D2.5.1
D5.1.2
D6.1.6
D6.2.3
D6.2.4
D6.3.1
WP no.
Task
lead
Nature Dissemin
ation
level
Integration Specifications
1
ST-I
R
PP
Delivery
date
(proj.
month)
M 18
First version of process simulator including treatment of PV
for mainstream CM OS technologies, and Discrete Power
Device,SiC,GaN/AlGaN technologies, interfaced to
commercial TCAD tools
Device simulation analysis of dominant variability sources
in state-of-the-art Non-Volatile-M emory technologies
2
ST-I
R
CO
M 15
2
UNGL
R
CO
M 18
Characterization of major sources of PV in SiC
technologies/devices, and AlGaN/GaN HEM T devices.
Report on 1/f noise dispersion behavior in 45nm bulk
CM OS
PV-aware circuit-level models for standard CM OS
technologies (down to 45nm), and Non-Volatile-M emory
technologies. State-of-the-art based statistical models, based
on hardware and/or TCAD.
Design of test structures for analog design parameter
monitoring
Semi-annual project progress report
First report on dissemination activities
First update of public part of the project web-site
Dissemination and use plan (first version)
2
NXP
R
CO
M 18
2
UNET
R
CO
M 18
5
AM S
R
CO
M 18
6
6
6
6
NXP
UNET
UNET
NXP
R
R
D
R
CO
CO
PU
CO
M 18
M 18
M 18
M 18
MODERN 2010 Review
March 1st, 2011
Contributors
(lead)
Actual /
Forecast
delivery date
Delivered
ST-I, AM S,
IFXA, NM X,
NXP, THL
ST-I, AM S,
TUW
09/12/10
Yes
15/06/10
yes
UNET,
UNGL,
NM X, SNPS
ST-I, NXP
14/10/10
Yes
23/11/10
Yes
UNGL,
UNET, NXP,
POLI, ST-I,
STF2, NM X
TUGI, AM S
20/10/10
Yes
28/09/10
Yes
NXP, all
ST-I, all
ST-I
UNET, NXP,
all
02/11/10
10/01/11
11/10/10
11/10/10
Yes
Yes
Yes
Yes
CONFIDENTIAL 10
Overview of deliverables and milestones status (2)
Milestones
Milestone Milestone name
number
M 2.1
M 2.2
M 6.2
Work
Expected
package(s) date (proj.
involved
month)
PV aware compact models available for bulk planar CM OS technologies
2
M 18
down to 45nm, TCAD/hardware based
Identification and description of major PV sources in non-foundry
2
M 21
mainstream logic technologies, cross-technology- fertilization
Second project review by ENIAC
all
M 14
MODERN 2010 Review
March 1st, 2011
Actual /
Forecast
delivery date
20/10/10
Achieved Means of verification
Yes
23/11/10
Yes
29/06/10
Yes
D2.1.1, D2.2.2, D2.3.1,
D2.5.1
D2.2.3
D2.3.1/ D2.3.2
D2.5.1
Reviewer’s feedback
CONFIDENTIAL 11
Website
Public
section
Restricted
section
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 12
Cooperation, dissemination and exploitation
A Workshop at DATE 2010 with the theme ‘The Fruits of Variability
Research in Europe’ was organized. This workshop was a co-operation
of the UK EPSRC project, FP7 STREP project REALITY and MODERN
VARI Workshop, 2010 May 26-27, Montpellier, France
Contribution to the Workshop on Simulation and Characterisation of
Statistical CMOS Variability and Reliabilitywas presented, Sept. 9th
2010, Bologna, Italy
MODERN participated in the Poster & Demo Session at European
Nanoelectronics Forum 2010 in Madrid, Spain
Large number of publications
Main meetings:
– General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons
present and 10+ called in
Due to the travel restrictions that many companies/institutes still face
most of the interaction between partners is by phone and email
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 13
Project management: progress, funding problems
and amendments
Progress: All planned deliverables ready
Most uncertainties in countries causing funding and (national)
administrative issues e.g. Italy, Swiss, Spain and Austria, are resolved
Amendments:
1. The change of project coordinator from ST to NXP and ST-Crolles being
replaced by ST-Grenoble
2. The removal of some inconsistencies between some deliverables
3. The subcontracting of work by Glasgow to GSS Ltd.
4. CSEM withdraws due to lack of national funding as of 29-06-2010
5. To account for the leaving of some NXP employees and a related change
in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are
(slightly) changed
6. To account for some technical difficulties encountered in the research
activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 14
Other issues Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 15
Example (Davide)
WP4 Domain Overview per Task and Partner
T4.1
Digital IPs/macros
UPC, LETI
Analog/AMS IPs/macros
UPC, LETI
Asynchronous
IPs/macros/cells
T4.2
T4.3
ISD
TMPO, LETI
TMPO
ST I, UPC
LETI
ISD, THL, ST F, NMX
Interconnect schemes and
on-chip communication
LETI
ISD, THL, ST F
CAD algorithms
POLI
CAD flows and integration
ELX, TMPO, TEKL, POLI
ST I
Design methodologies
ELX, TMPO
ST I, UNBO
ELX, TMPO, LETI
TMPO
Variability
EMC/EMI
Reliability/Fault tolerance
LETI
LETI, UPC
ST I, UNBO
LIRM
LIRM (?)
ELX, TMPO, TEKL, POLI, ST I
ISD, THL, ST F, NMX
Manufacturability and yield
Reconfigurability
T4.5
ST I, UNBO
Regular/configurable
IPs/fabrics
Architectures/Microarchitectures
T4.4
THL
ST I,UPC, UNBO, TMPO
ST F, THL, ISD
Software and programming
methods
MODERN 2010 Review
March 1st, 2011
UNBO
LIRM, THL
ST I, UNBO
LIRM, THL
CONFIDENTIAL 16
Examples (Andre, Davide)
Technology Overview per Task and Partner
Technologi
es
Process
simulation
Device
simulation
Electrical
Charact.
Reliability
Compact
Modeling
Task
2.1
2.2
2.3
2.4
2.5
HVMOS
AMS TUW
AMS TUW
AMS TUW
Planar CMOS
Technology
T4.1 NVM
90nm w/- eNVM
65nm
45nm
FDSOI
UPC
LETI (?)
40nm
32nm
NVM
LETI
65nm
UNCA
45nm
UNGL POLI
SNPS (STF2)
IMEP STF2
32nm
UNGL POLI
(STF2)
IMEP STF2
T4.2
41nm
T4.3
POLI, ST I,
TEKL, ELX
Finfets, MUG,
GAA
TMPO
UNET NMX
SNPS
IMEP (STF2)
LETI IMEP
STF2
NXP
ST F, ISD
SiC Power
MOS
STI
AlGaN-GaN
HEMT
STI
ELX, TMPO
ISD
LETI
THL
T4.4
UNET NMX
UPC, ST I,
UNBO, TMPO
STI
UNGL
UNGL
T4.5
UNET (N)MX)
UNET NMX
LETI
IMEP
LIRM (?)
STI
STI
STI
ST I, UPC,
TMPO
THL
NMX
MODERN 2010 Review
March 1st, 2011
UNGL POLI
STF2 NXP
CONFIDENTIAL 17
Example (Davide)
WP4: Link with other WPs and Tasks
WP3
UPC, LETI
T3.3
UPC, LETI
T5.2
T4.1
ST I
T3.4
WP5
WP4
LETI, TMPO
T5.3
T4.2
THL
T4.3
T4.4
UPC, TMPO, ST I
ST I
THL, LIRM
T4.5
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 18
WP1 agenda
Progress, highlights and lowlights
Matrices showing ‘Domain and Technology Overview per Task and
Partner’
Link with other WPs and Tasks
Technical status and achievements of deliverable D1.3
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 19
Outline
Introduction
Progress, highlights and lowlights
Matrices showing‘Domain and Technology Overview per Task and
Partner’ D1.3
Link with other WPs and Tasks
Cooperation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 20
Introduction: Progress, highlights and lowlights
PERIOD UNDER REVIEW
M1.1Problem definition and Tests
M1.4 user guides
M1.2 Integraton specs
1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project
(e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc).
2. Set the target technologies for which the above listed problems will be faced.
3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously
listed problems.
4. Define the requirements of the integration work needed to embed the new tools into the existing design
frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP.
5. Define up front all activities of all WPs of MODERN exception made of the management.
HIGHLIGHT : Activities recovered past delay D1.3 released OCT 2010
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 21
Matrices showing‘Domain and Technology
Overview per Task and Partner’ D1.3
WP2
Analog
(mixed)
WP3
Digital
NXP
X
X
AMS
X
ST
X
IFX
NMX
THL
X
WP4
System
X
X
X
X
X
X
X
MODERN 2010 Review
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CONFIDENTIAL 22
Matrices showing‘Domain and Technology
Overview per Task and Partner’ D1.3
WP2
WP3
Matching and 1/f-noise results will be integrated in process
blocks and PDK’s. The data we collect, analyze, and
model are used by the FT/DKD group in NXP-Nijmegen to
construct the appropriate process blocks for circuit
simulations.
Equally important is the fact that we use the results
measured on advanced technologies to assess where,
when and how future models and process blocks should
be modified, refined or expanded. For this we also use the
data from other partners
NXP


AMS

WP4
 Substrate noise: implementation
through guidelines (documentation)
and design reviews
Model Order Reduction:
implementation through guidelines,
training and supplying a toolbox
(plug & play)
EM simulation methodology:
implementation through guidelines
(documentation)
After survey of results T1.2 in WP5 , tools and environment
must be optimized for the final implementation in the AMS
characterization and modelling flow.
The main outcome of the T2.2 task, aging modelling of HV
transistors including PV will be implemented in the AMS
simulation environment. At the end of the day the AMS
HitKIT will extended with PV lifetime simulators for low
voltage and high voltage transistors. As within the Modern
project only a few and HV transistors are used as
demonstrators for this approach. All other devices in the
AMS HV CMOS technologies will be carried out with PV
aging models in the next future.
Matching parameters and also additional analog parameters
will be directly implemented in the AMS HiTKIT based on the
developments performed in MODERN.
MODERN 2010 Review
March 1st, 2011
Not involved
Not involved
Not involved
CONFIDENTIAL 23
Matrices showing‘Domain and Technology
Overview per Task and Partner’ D1.3
WP2
WP3
WP4

ST
PV aware spice Spice Models will be
implemented in the ST-I simulation
environment. The models are “plug
and play” they do not need any
integration work
T3.1 and T3.2 At the end of the
project we shall update ST digital
design flow, introducing additional
degrees of freedom to maximizing
delay sensitivity to FBB keeping the
overhead leakage power and area
cost as lower as possible while the
models created for the Analog IC
flow are "plug and play" i.e. do not
require integrationwork
All the methodologies developed in T4.2 as part of this task
were designed keeping as a strict constraint the easy
interoperability with standard RTL-to-GDSII design tools.
The proposed methodologies were conceived, designed and verified
with the specific aim of being "pluggable" in the existing
design flow as an additional, stand-alone extra step that
could enhance final performance results without altering
the flow in itself.

In T4.4
o
Regarding the metal programmable flow the RTL
generated by the flow must be compliant with
synthesis tools utilized in ST (e.g. Synopsys design
compiler).
o
Regarding the metal programmable flow the RTL
generated by the flow must be compliant with synthesis
tools utilized in ST (e.g. Synopsys design compiler)
o
The “skeleton” layout and schematic containing the notprogrammed datapath tiles will be realized utilizing a
standard design flow. The customization of the skeleton
layout and schematic will be automatically performed
utilizing a skill (Cadence) script which generates a VIA4
OPUS layer of the specific accelerator implemented
starting from the bitstream output of the Griffy front end
flow. The skeleton layout and schematic will be further
imported in Cadence OPUS and all libraries and views
will be exported.
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 24
Matrices showing‘Domain and Technology
Overview per Task and Partner’ D1.3
WP2
WP3


IFX
Not involved

WP4
Aging model parameters for analog reliability simulator
Virtuoso® RelXpert have been extracted and will be
made available as add-on to standard PDKs in
design/verification flow.
Results from basic assessment of aging/reliability
issues and aging induced PV in key AMS&RF building
blocks will be compiled into a comprehensive
documentation & catalogue (“impact matrix”) that gives
circuit designers guidelines in terms of expected aging
impact and strategies how to avoid, minimize or
compensate effects accordingly. This documentation
will be part of standard verification plans.
In a similar way the developed monitor & control circuit
IP portfolio (to enable aging/reliability insensitive
analog, mixed-signal and & RF circuits) will be included
in the documentation. In addition prototype designs will
be made available to the circuit designers
Not involved
software tools both internal and commercial
NMX
have been and/or are going to be improved
with respect to PV in terms of models,
efficiency, usability (allowing to avoid
workarounds in handling discrete dopants/traps
whitin ‘concentration’ based tools).This does
not require any integration work just
upgrade the version of the tool
The simplified and time saving methodology available in the
company will be cross-checked against more complete and
computationally heavy approaches available in academia to
verify (or, if necessary, improve) the coverage of the industrial
flow.
MODERN 2010 Review
March 1st, 2011
This work is done internally
without partners, therefore does
not require an integration plan.
CONFIDENTIAL 25
Matrices showing‘Domain and Technology
Overview per Task and Partner’ D1.3
THL
WP2
WP3
WP4
Not involved
modify the toolchain, validate
the architecture principles with
a SystemC simulator and
develop a usecase
modify the toolchain, validate the architecture principles with a
SystemC simulator and develop a usecase
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 26
Link with other WPs and Tasks
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 27
Collaborations
WP leader: ST-I
Strong dependence on partners: NMX, NXP,THL,IFX,AMS,ST-I, ST-F
Collaboration with partners: NMX, NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F ,
Telephone conferences with: NMX,NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F
according requirements of deliverables ALL SEPT – OCT 2010.
With WP Leaders weekly since the month of December.
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 28
WP2 agenda
Progress, highlights and lowlights
Matrices showing‘Domain and Technology Overview per Task and
Partner’
Link with other WPs and Tasks
Technical status and achievements of deliverables (incl. changes):
D2.1.1, D2.2.3, D2.3.2 and D2.5.1
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 29
WP3 agenda
Progress, highlights and lowlights
Matrices showing‘Domain and Technology Overview per Task and
Partner’
Link with other WPs and Tasks
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 30
WP3
Progress, highlights and lowlights
All deliverables for 2010 delivered as planned (M12)
Number
D3.1.1
D3.2.1
Contributors
NXP, ST-I1, TUD, TUE, UNRM
ST-I1, UNBO, UNCA, UNRM
D3.3.1
CSEM, IFXA, LETI, POLI, UPC
D3.4.1
D3.4.2
LIRM, ST-I2
NXP
Deliverable
Set of alternative symbolic models for lib cells
Process development kit (PDK), circuit techniques, and speed-up algorithms for PVaware circuit simulation
PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital
and AMS&RF
Impact of supply noise, and clock distribution on EMI and circuit timing
RF-interaction models for combined PCB-package-IC
Deliverables M24 are on schedule
Number
D3.1.2
D3.2.2
Contributors
LIRM , NXP, ST-I, TUD, TUE, UNRM
NMX, NXP, UNBO, UNCA, UNGL, UNRM
Deliverable
Statistical methodology for characterisation of digital and AMS&RF circuits
Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays
D3.3.2
D3.4.3
IFXA, LETI, NXP, POLI, UPC
NXP, ST-I
D3.4.4
ST-I
PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF
Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and analysis flow for
combined IC-package-PCB
Implementation and evaluation of clock tree synthesis techniques for low EMI
Highlights:
– Very successful meeting with WP3 partners on Nov. 2010 in Catania
– VARI 2010 conference organized by LIRMM
Lowlights
– Withdrawal of partner CSEM due to Swiss funding issues
– Funding of Italian partners delayed
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 31
Matrix
Application overview per task and partner
Tasks
Circuit Models
Methods
Tools&Flows
3.1
PV aware
Circuits
3.2
EMI/EMC
3.3
3.4
Application
Digital
NXP,STI,TUD,TUE,
UNRM,LIRM
UNBO,NXP,STI,
UNCA,
UNGL,UNRM
POLI,LETI,UPC
STI,LIRM
AMS
STI,UNRM
NMX,STI,UNRM
IFX,UPC
NXP,STI
RF
NXP,STI
IFX
NXP
NVM
NMX
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 32
WP3 Domain Overview per Task and Partner (tbd)
T3.1
Digital circuit models
TUD, LIRM, NXP,
UNRM
Statistical methods for digital
LIRM, TUE
Analog circuit models
STI,UNRM
Timing analysis
TUD, TUE, NXP,
LIRMM
T3.2
T3.4
NXP
Algorithms
UNRM,STI
Monte Carlo
UNCA
Body Bias
UNBO, STI
Spice like simulation
UNGL, NMX
Design methodologies
UNBO,NMX,NXP, STI,
UNCA, UNGL,UNRM
Variability
T3.3
TUD,TUE,NXP,
UNRM, STI,LIRM
IFX
EMC/EMI
NXP,STI
Monitor & control for digital
POLI,UPC,LETI,ST
Monitor & control for analog
IFX,UPC
Regular cells
UPC
Substrate Noise
NXP
Chip-Package-PCB
co-design
NXP, ST
Software and programming methods
NXP
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 33
WP3 symbolic synergy
T3.1
T3.2
T3.3
MODERN 2010 Review
March 1st, 2011
T3.4
CONFIDENTIAL 34
WP3: Link with other WPs and Tasks
WP2
WP3
T2.3
T3.1
WP4
NXP
ST I, UNRM
NMX
T2.5
IFX
T3.2
NMX
T3.3
UPC, LETI
T4.1
T3.4
ST I
T4.2
WP5
T5.1
T5.2
MODERN 2010 Review
March 1st, 2011
T5.3
CONFIDENTIAL 35
T3.1: surrogate behavioral models
• The optimization procedures considered in
T3.2 requires the availability of a circuit
simulator (e.g. SPICE). Each simulation run
may require a large computing time;
• GOAL in T3.2: development of surrogate
models for the circuit behaviour based on
learning machines (e.g. Neural Networks,
Support Vector Machines);
• So as to employ the surrogate model instead of
the circuit simulator.
• A larger experimentation of surrogate models is in
order;
• New input-output data sets for different circuits
are expected from ST-I;
• Results of main interest for task T3.2;
• Cooperation between UNRM and ST-I essential.
Red: Surrogate model outputs
Blue: Original outputs
Output START_PH1: Comparison on the test set
MODERN 2010 Review
March 1st, 2011
Good performance of surrogate
models on the test set
CONFIDENTIAL 36
T3.2: Analysis of Analogue Sensing Memory Circuit
with RandomSpice
Sense Amplifier circuit of NMX analyzed with
RandomSpice (UNGL)
SPICE frontend for advanced statistical circuit simulation.
Allows use of UNGL-developed PCA and non-linear
power method compact model parameter generation
methods.
Statistical enhancement of circuit simulation to access
very rare circuit instances.
Database and post-processing backend for
power/performance/yield predictions.
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 37
T3.3: M&C Strategies for AMS & RF
Switches
– Monitor concepts: ring oscillator, current sensing
– Control: “frequency locked loop”, analog control loop
Aging induced offsets
– Avoid offset generation: e.g. chopping (comparator)
– Correction of static & dynamic effects: e.g. error correction by redundancy
– Burn-in: dedicated stress to increase robustness and compensate PV
stress pattern
control voltage
ADC search algorithm incl. redundancy
...
Inv 1
...
Inv 2
Inv n
switch replicas
enable
ref.
switch on-voltage
Phase
Frequency
Detector
MODERN 2010 Review
March 1st, 2011
Charge
Pump
Loop
Filter
Ringo
Monitor
CONFIDENTIAL 38
Frequency
Divider
T3.4: Neptune 5 test chip specs
isolation
Aggressor
(IO or digital)
isolation
propagation
Victim
(FM LNA)
Current floor plan proposal
Neptune 5
PCB
Spectrum analyzer
Victim 1
analog pads
Spectrum of the output of FM buffer
with and without digital noise present in the system
Links to WP5, demonstrator
test-chip on substrate noise
Victim 5
Victim 6
Victim 7
Victim
settings
Victim 2
Shift
register 1
Shift
register 3
Shift
register 2
Shift
register 4
Victim 3
Victim 4
Aggressor
settings
Digital pads
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 39
Digital pads
Control equipment
Digital pattern generator
analog pads
WP3
Cooperation
tbd
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 40
WP3
Dissemination
tbd
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 41
WP4: Outline
Progress, highlights and lowlights
Matrices showing‘Domain and Technology Overview per Task and
Partner’
Link with other WPs and Tasks, Cooperations
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 42
WP4 Task Structure
T4.1: Variability-aware design (LETI, UPC)
T4.2: Variation-tolerant, robust, low-noise and low-EMI
architectures/micro-architectures (ELX, TMPO, LETI, POLI, ST I, TEKL)
T4.3: Design of reliable systems (ISD, THL, NMX, ST F)
T4.4: Design of regular architectures and circuits for high
manufacturability and yield (ST I, TMPO, UPC, UNBO)
T4.5: Distributed reconfigurable PV-robust architectures (THL, LIRM)
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 43
WP4 M24 Deliverables
D4.1.1
D4.2.2
D4.2.3
D4.3.2
Reports on PV-aware (self-) adaptive compensation and optimization
techniques, including on-chip monitors
TMPO, LETI, Reports on PV-tolerant noise and EMI reduction techniques, and on
TEKL
asynchronous and de-synchronized communication scheme benchmarking
Advanced asynchronous/de-synchronization flow. Delivery of the first deELX, POLI
synchronized design
LETI, UPC
NMX
NVM design and robustness assessment report
D4.3.3
ISD, THL
Functional and test specs for a validated controller for ADC and PLL
components. Fault-tolerant on-chip global communication scheme on a
multi-core SoC virtual platform
D4.4.1
UPC, TMPO
Report on yield prediction tool and regular structures for PV-tolerant
asynchronous blocks
D4.4.2
ST I, UNBO
Report on customizable and regular architectures [….] Delivery of a design
flow for mapping on mask-programmable computational blocks […]
D4.5.1
THL, LIRM
Report on programming methods and tools for PV-tolerant, reliable, and
predictable MPSoC architectures
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 44
WP4 Domain Overview per Task and Partner
T4.1
Digital IPs/macros
UPC, LETI
Analog/AMS IPs/macros
UPC, LETI
Asynchronous
IPs/macros/cells
T4.2
T4.3
ISD
TMPO, LETI
TMPO
ST I, UPC
LETI
ISD, THL, ST F, NMX
Interconnect schemes and
on-chip communication
LETI
ISD, THL, ST F
CAD flows and integration
ELX, TMPO, TEKL, POLI
ST I
ELX, TMPO, LETI
TMPO
Variability
EMC/EMI
Reliability/Fault tolerance
LETI
LETI, UPC
ST I, UNBO
LIRM
LIRM
ELX, TMPO, TEKL, POLI, ST I
ISD, THL, ST F, NMX
Manufacturability and yield
Reconfigurability
T4.5
ST I, UNBO
Regular/configurable
IPs/fabrics
Architectures/Microarchitectures
T4.4
THL
ST I,UPC, UNBO, TMPO
ST F, THL, ISD
Software and programming
methods
MODERN 2010 Review
March 1st, 2011
UNBO
LIRM, THL
ST I, UNBO
LIRM, THL
CONFIDENTIAL 45
WP4 Technology Overview per Task and Partner
Technology
T4.1
65nm
UPC
45nm
LETI
40nm
NVM
T4.3
T4.4
T4.5
POLI, ST I, TEKL,
ELX
90nm + eNVM
32nm
T4.2
LETI
TMPO
ST F, ISD
UPC, ST I,
UNBO, TMPO
ELX, TMPO
ISD
ST I, UPC, TMPO
LETI
THL
THL
NMX
MODERN 2010 Review
March 1st, 2011
LIRM
CONFIDENTIAL 46
D4.1.1: PV-aware adaptive compensation techniques (1)
LAVS (Local Adaptive Voltage Scaling Architecture)
– Monitor / Adapt V,F using
• Delay-based Diagnostic system
• Adaptation controller
• Local Power Manager
Vhigh
Vlow
Flow
Clock L
Adaptation
Controller
– Advantages:
• Operate on local, realistic silicon
corner (vs wc analysis)
• Monitor/adjust to variations along
circuit lifetime
• Optimize timing / power
perf
index
Clock H
Fhigh
Supply
Selector
Clock
Selector
Ftarget
LPM
performance
control
Sequencer
Vcore
Fcore
Probe 2
Core
Probe 1
Probe 3
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 47
D4.1.1: PV-aware adaptive compensation techniques (2)
Study of Delay-Based Variation Control using Body Bias (BB) and Voltage Scaling
(VS)
– Variation is Monitored using on-chip sensors: Leakage / Dynamic Power / Delay
– Based on sensor information, BB and VS is applied to reduce variability
– Study of correlation between observables:
• Delay distribution shows larger correlation
• Use of delay sensors can reduce not only delay variability, but also leakage and dynamic
power variability
Voltage Scaled Elastic clock architecture (with task 4.2)
– Elastic clocks allow clock period margin reduction
• Objective of analysis is to quantify this reduction with respect to Voltage noise
• Study of correlation between voltage at several chip locations.
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 48
D4.2.2: PV-tolerant noise and EMI reduction techniques (1)
QDI asynchronous NoC based on Muller gates: fully designed in STM
32nm technology
GALS interfaces to communicate with synchronous IPs:
– 2 Macros: Target / Initiator
– Performance
• Noc Area: 108 µm x 60 µm
• Asynchronous Peak :
~1GHz @tt32_1.00V_25C
• Interfaces :
800MHz @tt32_1.00V_25C
• Latency :
1 router : 0.8 ns
initiator to target : 1.6 ns
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 49
D4.2.2: PV-tolerant noise and EMI reduction techniques (2)
“Power shaping” methodology and design flow
for power robustness and low-EMI
– Uses standard indudstry formats (Verilog, SDF
SDC), exports modified Verilog + flow specific
clock tree synthesis directives.
– Proposed methodology applied to a 90nm IC
reference design provided by ST-I.
Smooth design flow integration
28% reduction of IC pad current peaks.
25% reduction of Max Dynamic Voltage Drop.
55% reduction of IC pad voltage fluctuations.
Up to 30 dBµV reduction of digital core
conducted EMI harmonics
Flow is now under formal evaluation by ST on 2
different product lines
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 50
D4.2.2: PV-tolerant noise and EMI reduction techniques (3)
Variability-tolerant low-EMI asynchronous circuits: flow to design PVTtolerant asynchronous cells
– Consolidated cells and macro-blocks (65 nm full Library [ + 45 nm library +
RAM & ROM)
– Realized flow to estimate current consumption profile and estimate EMI
– Demonstrated the efficiency of the approach on asynchronous ciphering
IPs like DES and AES, Compared with synchronous design
– Further attenuation made available by delay insertion (2.6x in time
domain, 10dB in frequency domain
Asynchronous circuit model
SystemVerilog
Synthesis
Simulation
Delay adaptation
SystemVerilog
circuit model
Li
b
current
estimation
4 mA
Synchronous
1.2 mA
Asynchronous
MODERN 2010 Review
March 1st, 2011
Asynchronous 60 dBµ
Synchronous 80 dBµ
CONFIDENTIAL 51
D4.2.3: Advanced De-synchronization Flows (1)
Automated block-level de-synchronization of
synchronous netlists
– Exploits existing Synthesis / P&R Tools
– Synthesis of matched delays
• Delay lines track circuit variability of the circuit at
multiple corners and voltages
• Delay synthesized using standard cells
• Tracks high-frequency variability (e.g. dynamic
voltage fluctuations)
– Sign-Off flow
• Flow requires specific sign-off procedure, based
on synchronous setup/hold constraints.
• Implemented in existing STA tools
– Results: AES cipher module (10K gates,17000 µm2, 40nm)
• 35% reduction vs nominal case.
• 21% reduction vs standard voltage scaling
• Robustness: de-synchronized circuit tracks hi-freq
voltage fluctuations (> 200mV) that lead to
Synchronous circuit fails
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 52
D4.2.3: Advanced De-synchronization Flows (2)
Asynchronous High-Level Synthesis (AHLS)
– Same SystemC model as synchronous (untimed or with TLM-style
handshaking)
• Standardized entry point vs Handshake Solutions
mul1
mul2
mul3
• Lower power vs de-synchronization
– No clock: Resources controlled by handshaking
• Based on Petri net formulation
add1
– Status
• Available: Petri net construction from DFG, State exploration, schedulingadd2
• Future Work: advanced pruning optimizations, comparison with other AHLS / Synchronous,
DFG generation from SysC, netlist generation for BE
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 53
D4.3.2: NVM Reliable Design
HIF
Read Path
Write Path
Buffer
Clocks
FIF
Two independent ECC levels
– Ci: Soft Decoded LDPC:
– Fully parallel solution
•
•
Needed RAM: 2 x 4 x 212 bits
~ 10 iterations, 450 “check machines”
(each check involves ~40 bits)
– Note: need for processing the whole WL
even if one ECC block is requested
Soft Code Reliability info
based on a predictive
model (wp2) tuned
on experimental data
– Co: BCH: 32-bit parallel architecture
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 54
D4.3.3: Fault Tolerant Design (1)
Design methodology for Reliable Multi-cores:
– Homogeneous multi-core systems equipped with spare elements
for transparent and deterministic workaround of local permanent
faults
– Hardware level
• exploit hardware redundancy and fault control
– Computation Resources: processor cores
– Storage resources: memory tiles and clusters
– Routing resources: physical links, router and network interfaces.
– System and application level (Link with Task 4.5.1)
• fault tolerant parallel programming paradigms
• possibly assisted by hardware extensions
• robust real-time operating system and algorithmic fault tolerance at user-level
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 55
D4.3.3: Fault Tolerant Design (2)
Design methodology for Reliable
Multi-cores:
– Fault
Tolerant
Multicore
Platform based on dynamic
redundancy control
• in-situ characterization
(BIST/BISR)
• non-intrusiveness of monitoring
process
• uninterruptible system operation
Results:
– Pedestrian recognition developed on
the SysC multicore architecture
– Characterized impact of task relocation
and simulated faults (Correct results,
Low impact on latency, no impact on
throughput)
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 56
D4.3.3: Fault Tolerant Design (3)
RTL implementation of fault tolerant routing on interconnect schemes
– Deployed on Spidergon STNoC technology
– adaptive fault tolerant routing through re-programming network interface
routing registers, dramatically reducing the consequences of link and
router faults
– As a side benefit, this introduces more freedom in dynamic modifications
of network topology, enhancing NoC flexibility
– RTL already been implemented by STMicroelectronics, but will remain
undisclosed due to industrial exploitation.
Usage planned on STMicroelectronics and ST-Ericsson platforms
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 57
D4.3.3: Fault Tolerant Design (4)
Design and implementation of a dynamic controller for test,
detect and repair faulty analog mixed signal (AMS) IP
– Design methodology based on dynamic redundancy control
• in-situ operational characterization (BIST/BISR)
• non-intrusiveness of monitoring process
• uninterruptible system operation
Developed behavioral models of PLL/ADC with process variation in SystemC-AMS
Performed functional validation and sensitivity analysis
– Takes into account Aging and Process Variation
Provided preliminary macroscopic monitoring metrics (eventually tp be linked to
electrical parameters) to characterize the operational range of AMS component
This will eventually lead to full operational characterization of the IPs
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 58
D4.4.1: Regular and Asynchronous design for yield and
variability (1)
Regular Structures
– Analysis of lithography effects
• Characterization of channel length variation due to lithography
• Statistics of channel length variation in benchmark circuits
• Impact of channel length variations in performance variability
– Lithography simulations
• Based on open-source 45nm kit
• Channel length dependence on distance to neighboring poly stripes
• Classification of poly distance distribution
– Benchmark circuit analysis
• Using Calibre nmDRC scripts to obtain class statistics
• From class statistics, channel length distribution statistics obtained
– Impact of channel length variation on variability
• Study variability including channel length statistical variation (non regular layout)
• Study variability without channel length variation (regular layout)
• Result: Quantify the advantage of using regular layout
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 59
D4.4.1: Regular and Asynchronous design for yield and
variability (2)
Design of Variability-tolerant Circuits
–
–
Study variability-tolerant asynchronous circuits and evaluate their benefits on manufacturability
and yield
Guarantee that the circuits are timing variations tolerant and analyze the impact on parametric
yield
Specification
Specification
Layout editor
M24 achievements:
•
Consolidated flow to characterize:
–
–
–
•
.oa
Schematic
edition
timing of asynchronous cells and macro-blocks
(lib files)
robustness of standard cells with respect to
timing variability
delay insensitivity of gate netlists
–
–
.sp
.sp
Implementation
Hspice
simulation
Post Synthesis done,
Post P&R Ongoing
DRC
LVS
.sp
Characterization
Validated on 65 nm process:
Automatic
layout
generation
Parasitic
extraction
.lib
.lib
Library
management
.v
Validation
MODERN 2010 Review
March 1st, 2011
Characterization
CONFIDENTIAL 60
Validation
D4.4.2: Customizable regular architectures (1)
vdd
gnd
Via programmable datapath for fast SoC design
– Pipelined array of identical pre-Layouted arithmethic
/ logic operators [200MHz @ 65nm]
– Functionality & Routing Customized by VIA4
connection [1 Mask]
gnd
Configuration through via connections
Design flow: from C-level DFG description [GriffyC] to programmable array
configuration:
– Implementation of the design flow front-end architecture.
– Implementation of flow for RTL generation from Griffy-C description
– Implementation of back-end flow for via programmable datapath configuration
MODERN 2010 Review March 1st, 2011
CONFIDENTIAL 61
D4.4.2: Customizable regular architectures (2)
Mask programmable Transistor Array
– Base Regular Cell with 4 Transistors (2xP, 2xN)
– Active Area not Continuous, Fixed Layers up to
Contacts
– Customization through M1/M2 Connections
– Advantages:
• Increased Yield
• Mask Cost reduction for Different Customizations
Design flow: from C-level DFG description [GriffyC] to transistor array
configuration
– GriffyC to RTL
– RTL to P&R
– P&R to mask configuration
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 62
D4.4.2: Customizable regular architectures (3)
Development of architecture & programming
model for application mapping on regular
multiprocessor architecture
– Hierarchical Multi-Many Core architecture
– Thread level parallelism
– Distributed, pipelined ASIC Acceleration mapped
on identical mask programmable macros
Development of a hardware/software design
methodology for application mapping and
accelerator design
– customizable System-C simulator
– customizable RTL model
– Automated generation of accelerator layout based
on mask programmed technology
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 63
D4.5.1: Methods and tools for PV-tolerant, reliable and
predictable MPSoC (1)
Fault tolerant HW/SW integrated model for Many
core SoC
– From Coarse-grained DFG description, produce faultrobust C -code suitable for datastream applications having
predictable fault reaction on MPSoC
– Run functional (High level) and timed systemC simulation
allowing the user to predict performance loss in any given
fault scenario
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 64
D4.5.1: Methods and tools for PV-tolerant, reliable and
predictable MPSoC (2)
Runtime task remapping in
homogeneous MPSoCs
– Distributed MPSoC architecture, from
high-level model to hardware
prototype
– Distributed memory MPSoC
System is capable of adapting itself to
perturbations
– Self-adaptive task migration
FPGA-based
prototype
• Monitors: CPU load, FIFO usage
– Dynamic Frequency scaling
SystemC
Model
Fault tolerance mechanism
– Based on “watchdog” techniques
– Each PE monitors neighbours
– Diagnostics, isolation and recovery
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 65
WP4 Cooperations
In T4.1 collaboration between LETI and ST F on technology transfer
In T4.1 cooperation between LETI and UPC on the temperature monitoring
activity, and to coordinate the activities of both institutions in MODERN
In T4.1 cooperation between ELX and UPC on voltage variation measurements
across chip
In T4.2 cooperation between ELX, POLI, and ST I on the design flow for
desynchronization and on EMI reduction techniques
In T4.2 cooperation between TEKL and ST I on the power shaping methodology
for EMI reduction and flow definition and integration of TEKL’s tool into ST
design flow
In T4.2 cooperation between LETI and TMPO on QDI asynchronous logic
implementation
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 66
WP4 Cooperations
In T4.3 common research activities and cooperation between ISD and THL, and
between THL and ST F
In T4.3 cooperation between ST F and UNBO has started on STNoC technology
In T4.4 cooperation between ST I, UPC and TMPO on the evaluation of the
impact of regular design
In T4.4 ST I and UNBO are cooperating on a design flow for mapping
applications on mask-programmable computational blocks, regular transistor
arrays, and via-/metal-programmable datapaths
In T4.5 cooperation between LIRM and LETI on fine-grain power optimization
under variability
In T4.5 cooperation between LIRM and ST F on MPSoC fault tolerance
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 67
WP4 Link w/- Other MODERN’s WPs
WP3
UPC, LETI
T3.3
UPC, LETI
T5.2
T4.1
ST I
T3.4
WP5
WP4
LETI, TMPO
T5.3
T4.2
THL
T4.3
T4.4
UPC, TMPO, ST I
ST I
THL, LIRM
T4.5
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 68
Published Papers
F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010.
I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. VARI, May 2010
C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio,” in Proc. Intl. Symp. on VLSI, Jul.
2010.
C. Jalier, D. Lattard, A. A. Jerraya, G. Sassatelli, P. Benoit, and L, Torres, “Heterogeneous vs. Homogeneous MPSoC Approaches for a Mobile LTE Modem,” in Proc. DATE,
Mar. 2010.
J. Altet, D. Gómez, C. Dufis, J. L. González, D. Mateo, X. Aragonés, F. Moll, and A. Rubio, “On Evaluating Temperature as Observable for CMOS Technology Variability,” in
Proc. VARI 2010, May 2010.
J. Cortadella, L. Lavagno, D. Amiri, J. Casanova, C. Macián, F. Martorell, J. A. Moya, L. Necchi, D. Sokolov, and E. Tuncer, “Narrowing the Margins with Elastic Clocks,” in Proc.
Intl. Conf. on Integrated Circuits Design and Technology, Jun. 2010.
C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “Flexible and Distributed Real-Time Control on a 4G Telecom MPSoC,” in Proc. ISCAS, Jun. 2010.
I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. Intl.
Symp. on VLSI, Jul. 2010.
I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs,”, in Proc. Intl. SOC Conf., Sep.
2010.
N. Hebert, P. Benoit, G. Sassatelli, and L. Torres, ‘’D-Scale: A Scalable System-level Dependable Method for MPSoCs,’’ in Proc. Asian Test Symposium, Dec. 2010.
M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, and A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010.
N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, “Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” in Proc. VARI, May 2010.
N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, "Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” JOLPE, vol. 6, n. 4, Dec. 2010.
Submitted Papers
2011: IEEE DATE (LIRM), IEEE ISCAS (LIRM)
MODERN 2010 Review
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WP4 Summary
Several WP4 meetings to prepare M24 deliverables
– F2f meetings ELX/UPC on July 12th and 19th and on October 5th, 2010.
– F2f meeting ST Catania Nov. 9th
– Three web meetings (Sep. ‘10, Dec. ‘10, Jan. ‘11)
Demonstrators
– System MPSoC platform, with task migration, failure analysis, power
optimization considering variability effects, and HW implementation of
several blocks to propose online optimization – LIRM T4.5
All M24 deliverables completed according to milestones
– No major criticality detected/reported by task leaders and partners
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Future Extensions within WP5 and Beyond
Within WP5, Thales expects to develop on FPGA the smart camera
multicore SoC, port the HAL to this implementation and test task migration
after fault injection using the pedestrian detection application.
– currently developing the supervisor and a basic processing tile, and
– considering improved fault tolerance through redundant on-chip networks
STMicroelectronics plans to commercialize STNoC technology, based on
source-based routing.
Expected future collaborations:
– ST-F, Thales and University of Bologna will develop a platform where all fault
tolerant STNoC features will be exploited.
– ISD and Thales on MPSoC task mapping.
– LIRMM and STMicroelectronics on fault tolerance.
– LIRMM and CEA/LETI on distributed computing and optimization techniques.
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CONFIDENTIAL 71
WP5 agenda
Progress, highlights and lowlights
Technical status and achievements of deliverable D5.1.2 (incl.
changes)
Structuring of demonstrators: goals and objectives
Link with other WPs and Tasks
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
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WP5 Progress, highlights and lowlights
Globally WP5 activities are on track
Second year deliverable achieved: D5.1.2 (see dedicated section)
Good progress on detailed demonstrator definition achieved as a
results on the activities progress in the “mother” work packages
Different technologies and technologies nodes are involved
During Catania meeting cooperation strenghtened
M24 deliverables on traks (considering ST-I shift from M24 to M36)
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Structuring of demonstrators: goals and objectives
3 technological area involved
– RF
– Power
– Logic (Cmos)
5 research area touched:
–
–
–
–
–
reliability
monitor and recover (aging)
substrate noise
on chip sensors
adaptation (AVFS)
Major basic concepts tested:
–
–
–
–
–
monitoring (T3.3)
redundancy (T3.3)
Adaptation (T4.1)
Regularity (T4.4)
Robust architectures (T4.5)
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Structuring of demonstrators: goals and objectives
possible summary matrix
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Test chip plan: owner UPC
Technology 65nm:
– LNA with Temperature monitoring
– VCO with monitor and control (T3.3)
Technology 40nm CMP:
– Design of Voltage Controlled Delay Line (VCDL) and DLL
– VCTA application for variation impact of regularity (T4.4)
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Test chip plan: owner AMS
Task 5.2 - TUG
Design and fabrication of benchmark structures.
Validation of proposed benchmark cases.
Outstanding deliverables:
– D5.2.2 – M27
– D5.2.3 – M36
SPECIFY
BENCHMARKS
PRIMARY
SIMULATION,
DESIGN AND
LAYOUT
FABRICATION
OF
BENCHMARK
STRUCTURES
VERIFICATION:
BENCHMARK CASES vs. MEASUREMENTS
STRESS
CASE_1
CASE_2
CASE_3
……….….
CASE_N
Benchmark Cases
Benchmark
Structures
Rel. Simulator
Rel. Simulator
Hu derivative
Structure 1
TUV
analytical
model
MINIMOS-NT
Reliability
WC models
NO
DO MEASUREMENTS
AGREE WITH THE RESULTS FROM
SIMULATION?
hierarchically structured
☺/X
FIND OUT
WHY
Structure 2
Structure 2
Structure 4
etc.
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YES
BENCHMARK
CASE
OK
Test chip plan: owner LETI; Architecture Overview
A fine grain Local Dynamic Adaptive voltage and frequency scaling
architecture
RunTime
Diagnostic:
– Process-Voltage-Temperature
– Timing fault detection or prevention (T3.3)
ANOC
CVPU
CVPU
Actuators:
– Based on Vdd-hopping
– Local clock generation using FLL
0.9v
0.7v
PE
0.9v
0.7v
PE
Power/Variability Control
– Local control with minimum hardware (T4.1, T4.2)
– Global control : high level algorithms
Main HW objective : a minimum hardware based on standard cells
and simple analog macros for flow insertion and maximum efficiency
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Test chip plan: owner LETI; LoCoMoTIV flooplan
32nm technology
Fully digital FLL :
Frequency
generation
PVT probes
Hopping transition
and switches :
Voltage genration
PE1
PE0
L2RAM
ANOC
CDMA
PE2
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Test chip plan: owner IFXA
Objective: development and verification of monitor & control (M&C)
strategies for AMS&RF circuits to deal with aging/reliability issues and
aging induced parameter variations in nanometer CMOS.
Close link to T3.3 (M&C concept development)
Outline
– Basic aging/reliability assessment  identify sensitivities
• Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2)
• Dedicated test-structures for transient effects and aging-parameter-variations
– Development of M&C concepts  T3.3
– Implementation and verification of M&C concepts
• Silicon based proof of concept
• Concept development for accelerated aging/stress tests  T5.2
• Development of characterization methods (fast transient effects)  T5.2
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Test chip plan: owner IFXA
to be completed
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T5.1 Test structures and D5.1.2
Partners: AMS, NMX, STF2, TUG
Technologies:
– 45nm CMOS technology developed by STMicroelectronics
– Non volatile memory technology from Numonyx
– HV-CMOS technology working up to 120V from Austriamicrosystems
T5.1 peculiarities, Goals and Obiectives:
–
–
–
–
Feed data to other WPs / verify estimation
Define improvement in test structures to increase accuracy
Development of advanced Mismatch test - structures
Development and Evaluation of PV Monitoring structures and Methods
Innovative aspects / returns:
– Applications of same concepts to different technologies with smart adaptations
– Higher accuracy in PV simulation results in silicon area savings
– Applicable for Product design with possible increase in Yield
Links between WPs and tasks:
–
–
–
–
T2.3: SPICE Monte Carlo models
T2.5: PV-aware compact modeling
T2.1 and T2.2: T5.1 will deliver the benchmark for process and device simulation
The experimental results (NMX restricted) will be used for comparison with simulations
for the validation of NMX methodology will be discussed within WP3, T3.2, D3.2.3 (M36)
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D5.1.2 achievements
Task 5.1 – AMS, TUG
Focus of D5.1.2 is the design and layout of:
– analog monitoring and characterization parameter
structures
– of monitoring structures utilizing Kelvin-Probe
measurement technique for standard and butted
devices
– matching test structures for HV-FETS:
• with standard pad-sharing approach
• with terminal multiplexing matching test structures
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Example I: MOSFET Monitoring Structure utilizing
Kelvin-Probe Measurement Technique
Realization for standard devices
Voltage Follower
+
Compensation of voltage drops
due to wiring
Ohmic Losses
Force
Sense
Point
Vin
Pad utilization of adjacent
unobserved devices for the sense
line reduce area consumption
Sense
DUT
“Sense” devices are active but
currentless
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Example I: MOSFET Monitoring Structure utilizing
Kelvin-Probe Measurement Technique
Realization for devices which are aimed to work at Vbs=0V
S & B commonly connected with metal
Device area reduction due to missing FOX between source and bulk
especially for short channel devices
A…gate line 1
B…gate line 2
C…sense line between drains
3…drain pad 1
6…drain pad 2
4…source/bulk pad
5…source/bulk pad
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Example II: 5.2. Design of terminal multiplexing
matching test structures for HV-FETs
Basis for matrix structure is given by standard pad sharing structure for
HV-FET matching characterization
Consideration of “golden rules”: symmetry, current direction, symmetric
connections, usage of guard rings etc.
Final structure for characterization is realized as matrix consisting of
equidistant placed devices
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Example II: 5.2. Design of terminal multiplexing
matching test structures for HV-FETs
Development of multiplexer test-structure for
distance dependent matching characterization
of HV-FETs
Utilization of Kelvin-technique applied to
individual transistor pairs within the matrix
Consideration of voltages up to 50V, which is
a typical voltage level for HV-LDMOS FETs
Design of special transmission gates
(switches) for gate and drain terminal
multiplexing
Facts:
– 208 HV-switches for gate bias multiplexing
– 24 HV-switches for drain bias multiplexing
– Maximum drain current Imax = 20mA
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Cooperation and dissemination
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