Transcript Presentazione di PowerPoint - Institute for Software Research

Putting Formal Description of
Software Architecture in Practice:
Good News, Bad News.
Paola Inverardi
UNIVERSITA’ DEGLI STUDI DELL’AQUILA
Area Informatica, Facolta’ di SSMMNN
Brief history of our work in SA
• Formal description of SA via CHAM
• Behavioral Analysis of the SA
• algebraic analysis and finite state modeling
• validation and quantitative analysis based
on FSTM
Our experience
• Modelling SA for three telecommunication
companies
• UML as ADL
• Poor dynamics descriptions
DYNAMICS
• A model of all possible system behaviours
• state diagrams for “manageable” processes
• implicit parallel notation for composite
processes-. P1||P2||…||Pn
• No explicit representation due to state
explosion
• Sequence diagrams/MSCs
ITALIAN TELECOM NETWORK ARCHITECTURE
WDM
ADM
ADM
ADM
ADM
ADM
ADM
STM-16 Ring
ADM
ADM
ADM
WL
WL
STM-16 Ring
ADM
ADM
ADM
ADM
ADM
ADM
National level
ADM
STM-4/16
SXA
ADM
Regional level
ADM
ADM
ADM
ADM
SXC
SXA
4/1
ADM
STM-4/16
SXA
ADM
STM-4/16
STM-1/4
ADM
ADM
ADM STM-1/4 ADM
ADM
ADM STM-1/4 ADM
ADM
City level
ADM
ADM
ADM
ADM
GOALS
Study of the SXA Cross Connettor.
Development of a SA description (formal / semi-formal) to
allow quantitative analysis
Try different description techniques. (UML, ADL,
Process Algebras)
The identification and structuring of the information
necessary to produce a performance model.
Reverse Engineering. Process
SXA SYSTEM – SOFTWARE CONFIGURATION
TLECOMM.
PROVIDER
LOCAL
TERMINAL
OSI
STACK
COMMAND
HANDLER
DATABASE
MANAGER
SYSTEM FUNCTION
Database
MIB
XCONN
SXA SYSTEM – HARDWARE CONFIGURATION
ET-MUX
ES-CORE
working
T-MUX
T-MUX
T-MUX
T-MUX
Rack
IO
Rack
IO
ES-CORE
protection
ET-MUX
Rack
IO
C-CORE
Rack
CENTRAl
SOFTWARE LAYERS
External Interfaces
CM
DN
DR EPS FM LPS TIM TM PM
Global Functions
Shelf Functions
Periferal Functions
Unit Handler
System Base
Hardware unit
XCONN
HARDWARE LAYERS
ES-CORE Protection
C-CORE
ES-CORE Working
GLOBAL
.
Timing
8
ETMSU
MSCU
MSCU
SHELF
LAN HUB
PSCU
PERIFERAL
C-LAN
2 TSU
PSCU
TDU
DPS
Phisical
ports
ASU
T-MUX
#1
T-MUX
# n < 30
2 TSU
PSCU
2 TSU
PSCU
TDU
DPS
Phisical
ports
ASU
Phisical
ports
ASU
ET-MUX
#1
ET-MUX
# n < 16
TDU
T-MUX16
#1
T-MUX16
#n<8
XCONN LAYERS
Global
GXC
Shelf
SSXC
CXC
TXC
BXC
STXC
SAXC
Periferal
PTXC
PSXC
REVERSE ENGINEERING PROCESS
System Domain Study
System Function XCONN
Domain Study
Architectural Description
Functional Partition
DOMAIN SYSTEM STUDY
Domain
System
Study
Components
High-Level
Documentation
XCONN
Domain
Study
Interviews
Architectural
Description
Functional
Partition
Domain
System
Study
High-Level
Sequence
Diagrams
(UML)
XCONN DOMAIN STUDY
Previous phases
Domain
System
Study
XCONN
Domain
Study
Architectural
Description
Functional
Partition
Components
detailed
description
Exchanched
Messages lists
XCONN
Domain
Study
Stereotyped class
diagrams (UML)
Deployment
Diagram (UML)
STEREOTYPED CLASS DIAGRAM (UML)
SYSTEM
ELEMENT MANAGER
<<SYSTEM FUNCTION>>
LPS
CMDH
<<SYSTEM FUNCTION>>
<<SYSTEM FUNCTION>>
XCONN
EPS
<<SYSTEM FUNCTION>>
<<SYSTEM FUNCTION>>
CM
FM
STEREOTYPED CLASS DIAGRAM (UML)
SYSTEM FUNCTION XCONN
<<component>>
Element Manager
<<component>>
CMDH
1..1
<<component>>
EPS
1..1
1..1
1..1
1..1
1..1
<<XCONN component>>
GXC
<<component>>
FM
1..1
1..1
1..1
1..1
<<component>>
CM
1..1
1..2
1..1
<<XCONN component>> 1..1 1..1 <<XCONN component>>
CXC
BXC
1..1
1..1
<<XCONN component>>
PSXC
1..1
1..*
1..1
<<XCONN component>>
SSXC
<<XCONN component>>
STXC
1..*
1..1
1..1
1..*
1..*
<<XCONN component>>
TXC
1..2
<<XCONN component>>
PTXC
1..1
1..1
<<component>> 1..1
LPS
1..*
ARCHITECTURAL DESCRIPTION
Previous activities
results
System
Domain
study
XCONN
domain
study
MSG abstraction
Components
Detailed
Description
SDL Code and
Diagrams
architectural
description
Architectural
description
Functional
partition
Static description
of components
with DARWIN
Components
Behavioral
description by
the FSP process
algebra
Feedback on previous
activities results
STATIC DESCRIPTION WITH DARWIN
Components hierarchy
STATIC DESCRIPTION WITH DARWIN
Graphic Description of the SAXC
component
SAXC
cxc[0]
cxc[1]
bxc[0]
txc[1]
txc[2]
bxc[1]
txc[n]
GRAPHIC SDL
SDL STATE
INPUT MESSAGES
OUTPUT MESSAGES
Sub-structure of the BXC process
FSP Description of the BXC process
FINITE STATE AUTOMATA
Space state
Components
# states
GXC
SSXC
PSXC
STXC
PTXC
CXC
BXC
TXC
15649
19968
4
336
40
7952
24
99
# transitions
15649
19968
4
333
40
4221
24
99
Composed Components
|| SAXC =( cxc[i:0..1]: CXC || bxc[i:0..1]: BXC || txc[i:1..2]: TXC)
|| XCONN = saxc:SAXC || gxc:GXC || stxc[i:0..1][j:1..Maxtmux]:
STXC || ptxc[i:0..1][j:1..Maxtmux]:PTXC || ssxc[i:0..1]:SSXC ||
psxc[i:0..1][j:1..Etmsu]:PSXC)
29633
51712
9
774
87
6990
48
262
# states
minimized
automata
184
30
4
84
18
2525
21
52
Space state
3,569814221783e+14
9,290070305824e+50
SAXC FSP DESCRIPTION
|| SAXC =( cxc[i:0..1]: CXC || bxc[i:0..1]: BXC ||
txc[i:1..2]: TXC) /
{
cxc[c:C].cb_stato_indirizzo[statobxc:Stato] /
bxc[c].cb_stato_indirizzo[statobxc],
cxc[c:C].cb_richiesta_allineamento_sb[allineamento:Tip
oallineamento] /
bxc[c].cb_richiesta_allineamento_sb[allineamento:Tipoa
llineamento],
………………………………………………
cxc[c:C].ct_inizio_configurazione[t:T] /
txc[t].ct_inizio_configurazione[c],
cxc[c:C].ct_lista_connessioni[t:T] /
txc[t].ct_lista_connessioni[c],
……………………………………………….
bxc[0].bb_richiesta_allineamento_sb[1] /
bxc[1].bb_richiesta_allineamento_sb,
bxc[0].bb_trasferimento_dati[1] /
bxc[1].bb_trasferimento_dati,
……………………………………………….
}.
RELABELLING
|| XCONN = (saxc:SAXC || gxc:GXC ||
stxc[i:0..1][j:1..Maxtmux]: STXC ||
ptxc[i:0..1][j:1..Maxtmux]:PTXC || ssxc[i:0..1]:SSXC ||
psxc[i:0..1][j:1..Etmsu]:PSXC) /
{
gxc.gc_stato_matrice[c:C] / saxc.cxc[c].gc_stato_matrice,
gxc.gc_stato_shelf[c:C][escore1:Statop][escore2:Statop][tmux
1:Statop][tmux2:Statop] /
saxc.cxc[c].gc_stato_shelf[escore1][escore2][tmux1][tmux2],
………………………………………………………
gxc.st_ack[t:T][st:St] / stxc[t][st].gst_ack,
gxc.stg_stati_switch_pgroup[t:T][st:St] /
stxc[t][st].stg_stati_switch_pgroup,
saxc.cxc[c:C].ssc_richiesta_configurazione
/ssxc[c].ssc_richiesta_configurazione,
saxc.cxc[c:C].ssc_report_permessi /
ssxc[c].ssc_report_permessi,
………………………………………………………
saxc.txc[t:T].tst_tabella_matrice[st :St] [statostxc:Stato] /
stxc[t][st].tst_tabella_matrice[statostxc],
saxc.txc[t:T].tst_inizio_configurazione[st :St] /
stxc[t][st].tst_inizio_configurazione,
……………………………………………………….
ssxc[ss:Ss].psss_ssxcack[ps:Ps] / psxc[ss][ps].psss_ssxcack,
ssxc[ss:Ss].psss_richiesta_configurazione[ps:Ps] /
psxc[ss][ps].psss_richiesta_configurazione,
………………………………………………………..
}.
FUNCTIONAL PARTITION
System
Domain
Study
Previous
activities
results
XCONN
Domain
Study
Architectural
Description
Functional
Partition
SDL
Diagrams and
code
Functional
Partition
Messagge
Sequence Chart
(MSC)
Activity diagrams
(UML)
MESSAGE SEQUENCE CHART (MSC)
Components
istances
GXC : GXC
GXC_
READY
CXC attivo :
CXC
CXC_READY
_ACT
gc_nuovexc
FSP processes
state before
performing the
action
GXC_W_
ACK_CONF
CXC_CALCOLO_
PATH_LISTA_XC
FSP process state
after performing the
action
automata
transition.
EM : ELEM EN
C M DH : CMD H
G XC : G X C
C X C A CT : CX C
BX C A CT : BX C
T X C (n ) : T X C
SS X C A C T :
T M A NA G E R
SSXC
e ch _ n u o ve xc
G X C_
CX C_RE A DY
RE A DY
_A CT
c hg _n uo ve x c ( )
P e r o g n i c on ne ssi o n e pre se n t e ne l
m e ssa gg io a p p l ic a l 'al go ri t m o d i p a t h
g c_ n u o ve xc
I P O T E S I a ) L 'a l go ri t m o h a su cc es so
G X C_W_A C
K _CO NF
CX C_CA LCO LO _P A T H_
L IS T A _ X C
c g _ re p o rt _ x c _ st a b i l i t e ( )
n m e ssa g g i pe r o gn i T X C
c o i nv ol t o .
g c h _ re p o rt _ x c _ st a b i l i t e ( )
C X C _ C O N N E S S IO N I_
T X C1
c h e_ re po rt_ xc _s t ab il i t e
c t _ l i st a _ c o n n e ssi o n i ( )
G X C_
RE A DY
C XC _ CO N NE SS I O N I _
T X C (n )
c ss_ l e g g i _ x c _ 2 _ st a d i o ( )
c b _ ri c h i e st a _ a l l i n e a m e n t o _ sb ( )
L o ri c e v e d a t u t t i i T X C
c o i n v o l ti .
CX C _ W A I T _ T O T A
L_ A C K
t c _ re p o rt _ c o n f i g u ra z i o n e ( )
cg _ re p or t _ c o n fi g u ra z i o ne 13 ( )
s sc _re p o rt _c on fi g ur az io n e ( )
c g_ re po rt_ co nf i gu ra zi on e2 ( )
b c _ re p o rt _ a l l i n e a m e n t o ( )
c g_ al li n ea m en to ( )
C X C _ R EA D Y _
AC T
COLLABORATION DIAGRAMS (UML)
1: ech_nuovexc
EM : ELEMENT
MANAGER
2: chg_nuovexc( )
CMDH :
CMDH
GXC :
GXC
6: che_report_xc_stabilite
5: gch_report_xc_stabilite( )
4: cg_report_xc_stabilite( )
11: cg_report_configurazione13( )
13: cg_report_configurazione2( )
15: cg_allineamento( )
SSXC ACT
: SSXC
3: gc_nuovexc
12: ssc_report_configurazione( )
8: css_leggi_xc_2_stadio( )
9: cb_richiesta_allineamento_sb( )
CXC ACT
: CXC
BXC ACT
: BXC
14: bc_report_allineamento( )
10: tc_report_configurazione( )
7: ct_lista_connessioni( )
TXC(n) :
TXC
Summarizing
• Issue of complexity: Have clear in mind
what the SA has to be for
• Domain specific ADL, complementing
standard notations with ad hoc notations,
e.g. FSP
• Predictive analysis and evaluation of the
architectural choices