Transcript Lecture 3: R4000 + Intro to ILP

Question: Who Cares About the
Memory Hierarchy?
CPU
CPU-DRAM Gap
“Moore’s Law”
100
10
1
“Less’ Law?”
µProc
60%/yr.
Processor-Memory
Performance Gap:
(grows 50% / year)
DRAM
DRAM
7%/yr.
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
Performance
1000
• 1980: no cache in µproc; 1995 2-level cache on chip
(1989 first Intel µproc with a cache on chip)
Generations of Microprocessors
• Time of a full cache miss in instructions executed:
1st Alpha:
2nd Alpha:
3rd Alpha:
340 ns/5.0 ns = 68 clks x 2 or
266 ns/3.3 ns = 80 clks x 4 or
180 ns/1.7 ns =108 clks x 6 or
136
320
648
Caching
• Principle: results of operations that are
expensive should be kept around for reuse
• Examples:
–
–
–
–
–
–
CPU caching
Forwarding table caching
File caching
Web caching
Query caching
Computation caching
• Most processor performance improvements in
the lastr
What is a cache?
• Small, fast storage used to improve average access
time to slow memory.
• Exploits spacial and temporal locality
• In computer architecture, almost everything is a cache!
–
–
–
–
–
–
Registers a cache on variables
First-level cache a cache on second-level cache
Second-level cache a cache on memory
Memory a cache on disk (virtual memory)
TLB a cache on page table
Branch-prediction a cache on prediction information?
Proc/Regs
Bigger
L1-Cache
L2-Cache
Memory
Disk, Tape, etc.
Faster
Example: 1 KB Direct Mapped Cache
• For a 2 ** N byte cache:
– The uppermost (32 - N) bits are always the Cache Tag
– The lowest M bits are the Byte Select (Block Size = 2 ** M)
Block address
31
9
Cache Tag
Example: 0x50
4
0
Cache Index
Byte Select
Ex: 0x01
Ex: 0x00
Stored as part
of the cache “state”
Cache Tag
Cache Data
Byte 31
0x50
Byte 63
: :
Valid Bit
Byte 1
Byte 0
0
Byte 33 Byte 32 1
2
3
:
:
Byte 1023
:
:
Byte 992 31
Set Associative Cache
• N-way set associative: N entries for each Cache
Index
– N direct mapped caches operates in parallel
• Example: Two-way set associative cache
– Cache Index selects a “set” from the cache
– The two tags in the set are compared to the input in parallel
– Data is selected based on the tag result
Valid
Cache Tag
:
:
Adr Tag
Compare
Cache Data
Cache Index
Cache Data
Cache Block 0
Cache Block 0
:
:
Sel1 1
Mux
0 Sel0
OR
Hit
Cache Block
Cache Tag
Valid
:
:
Compare
Disadvantage of Set Associative Cache
• N-way Set Associative Cache versus Direct Mapped
Cache:
– N comparators vs. 1
– Extra MUX delay for the data
– Data comes AFTER Hit/Miss decision and set selection
• In a direct mapped cache, Cache Block is available
BEFORE Hit/Miss:
– Possible to assume a hit and continue. Recover later if miss.
Valid
Cache Tag
:
:
Adr Tag
Compare
Cache Data
Cache Index
Cache Data
Cache Block 0
Cache Block 0
:
:
Sel1 1
Mux
0 Sel0
OR
Hit
Cache Block
Cache Tag
Valid
:
:
Compare
Basic Units of Cache
•
•
•
•
Cache Line/Set (index)
Cache Block (tag)
Cache Sector or Subblock (valid bit)
S: cache size, A: degree of associativity,
B: block size, N: # of cache lines,
I: # of index bits
S = B*A*N
N = 2I/B
Cache performance
• Miss-oriented Approach to Memory Access:
MemAccess


CPUtime  IC   CPI

 MissRate  MissPenalty   CycleTime
Execution
Inst


MemMisses


CPUtime  IC   CPI

 MissPenalty   CycleTime
Execution
Inst


– CPIExecution includes ALU and Memory instructions
• Separating out Memory component entirely
– AMAT = Average Memory Access Time
– CPIALUOps does not include memory instructions
 AluOps
CPUtime  IC  
 CPI
Inst

AluOps

MemAccess

 AMAT   CycleTime
Inst

AMAT  HitTime  MissRate  MissPenalty
  HitTimeInst  MissRate Inst  MissPenalty Inst  
 HitTimeData  MissRateData  MissPenaltyData 
Impact on Performance
• Suppose a processor executes at
– Clock Rate = 200 MHz (5 ns per cycle), Ideal (no misses) CPI = 1.1
– 50% arith/logic, 30% ld/st, 20% control
• Suppose that 10% of memory operations get 50 cycle
miss penalty
• Suppose that 1% of instructions get same miss penalty
• CPI = ideal CPI + average stalls per instruction
1.1(cycles/ins) +
[ 0.30 (DataMops/ins)
x 0.10 (miss/DataMop) x 50 (cycle/miss)] +
[ 1 (InstMop/ins)
x 0.01 (miss/InstMop) x 50 (cycle/miss)]
= (1.1 + 1.5 + .5) cycle/ins = 3.1
• 58% of the time the proc is stalled waiting for memory!
• AMAT=(1/1.3)x[1+0.01x50]+(0.3/1.3)x[1+0.1x50]=2.54
Example: Harvard Architecture
• Unified vs Separate I&D (Harvard)
Proc
Unified
Cache-1
Unified
Cache-2
I-Cache-1
Proc
D-Cache-1
Unified
Cache-2
• Table on page 384:
– 16KB I&D: Inst miss rate=0.64%, Data miss rate=6.47%
– 32KB unified: Aggregate miss rate=1.99%
• Which is better (ignore L2 cache)?
– Assume 33% data ops  75% accesses from instructions (1.0/1.33)
– hit time=1, miss time=50
– Note that data hit has 1 stall for unified cache (only one port)
AMATHarvard=75%x(1+0.64%x50)+25%x(1+6.47%x50) = 2.05
AMATUnified=75%x(1+1.99%x50)+25%x(1+1+1.99%x50)= 2.24
Four Questions for Memory
Hierarchy Designers
• Q1: Where can a block be placed in the upper level?
(Block placement)
– Fully Associative, Set Associative, Direct Mapped
• Q2: How is a block found if it is in the upper level?
(Block identification)
– Tag/Block
• Q3: Which block should be replaced on a miss?
(Block replacement)
– Random, LRU
• Q4: What happens on a write?
(Write strategy)
– Write Back or Write Through (with Write Buffer)
Improving Cache Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.
Reducing Misses
• Classifying Misses: 3 Cs
– Compulsory—The first access
to a block is not in the cache,
so the block must be brought into the cache. Also called cold
start misses or first reference misses.
(Misses in even an Infinite Cache)
– Capacity—If
the cache cannot contain all the blocks needed
during execution of a program, capacity misses will occur due to
blocks being discarded and later retrieved.
(Misses in Fully Associative Size X Cache)
– Conflict—If
block-placement strategy is set associative or
direct mapped, conflict misses (in addition to compulsory &
capacity misses) will occur because a block can be discarded and
later retrieved if too many blocks map to its set. Also called
collision misses or interference misses.
(Misses in N-way Associative, Size X Cache)
• More recent, 4th “C”:
– Coherence - Misses caused
by cache coherence.
3Cs Absolute Miss Rate
(SPEC92)
0.14
1-way
Conflict
Miss Rate per Type
0.12
2-way
0.1
4-way
0.08
8-way
0.06
Capacity
0.04
0.02
64
32
16
8
Cache Size (KB)
128
Compulsory vanishingly
small
4
2
1
0
Compulsory
2:1 Cache Rule
miss rate 1-way associative cache size X
= miss rate 2-way associative cache size X/2
0.14
1-way
Conflict
2-way
0.1
4-way
0.08
8-way
0.06
Capacity
0.04
0.02
Cache Size (KB)
128
64
32
16
8
4
2
0
1
Miss Rate per Type
0.12
Compulsory
3Cs Relative Miss Rate
100%
Miss Rate per Type
1-way
80%
Conflict
2-way
4-way
8-way
60%
40%
Capacity
20%
128
64
Flaws: for fixed block size
Good: insight => invention Cache Size (KB)
32
16
8
4
2
1
0%
Compulsory
How Can Reduce Misses?
• 3 Cs: Compulsory, Capacity, Conflict
• In all cases, assume total cache size not changed:
• What happens if:
1) Change Block Size:
Which of 3Cs is obviously affected?
2) Change Associativity:
Which of 3Cs is obviously affected?
3) Change Compiler:
Which of 3Cs is obviously affected?
Mapping Between Cache and
Memory
000
001
010
011
100
101
110
111
0000
0001
0010
0011
0100
0101
0110
0111
Locality
• Temporal Locality: things that get
referenced recently tend to be referenced
in the near future
• Spatial Locality: things that are close to
those that are referenced recently tend to
be referenced in the near future
1. Reduce Misses via Larger
Block Size
25%
1K
20%
15%
16K
10%
64K
5%
256K
Block Size (bytes)
256
128
64
32
0%
16
Miss
Rate
4K
2. Reduce Misses via Higher
Associativity
• 2:1 Cache Rule:
– Miss Rate DM cache size N Miss Rate 2-way cache
size N/2
• Beware: Execution time is only final measure!
– Will Clock Cycle time increase?
– Hill [1988] suggested hit time for 2-way vs. 1-way
external cache +10%,
internal + 2%
Example: Avg. Memory Access
Time vs. Miss Rate
• Example: assume CCT = 1.10 for 2-way, 1.12 for
4-way, 1.14 for 8-way vs. CCT direct mapped
Cache Size
(KB)
1-way
1
2.33
2
1.98
4
1.72
8
1.46
16
1.29
32
1.20
64
1.14
128
1.10
Associativity
2-way 4-way
2.15
2.07
1.86
1.76
1.67
1.61
1.48
1.47
1.32
1.32
1.24
1.25
1.20
1.21
1.17
1.18
8-way
2.01
1.68
1.53
1.43
1.32
1.27
1.23
1.20
(Red means A.M.A.T. not improved by more associativity)
3. Reducing Misses via a
“Victim Cache”
• How to combine fast hit time
of direct mapped
yet still avoid conflict misses?
• Add buffer to place data
discarded from cache
• Jouppi [1990]: 4-entry victim
cache removed 20% to 95% of
conflicts for a 4 KB direct
mapped data cache
• Used in Alpha, HP machines
TAGS
DATA
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
To Next Lower Level In
Hierarchy
4. Reducing Misses via
“Pseudo-Associativity”
• How to combine fast hit time of Direct Mapped and have the
lower conflict misses of 2-way SA cache?
• Divide cache: on a miss, check other half of cache to see if
there, if so have a pseudo-hit (slow hit)
Hit Time
Pseudo Hit Time
Miss Penalty
Time
• Drawback: CPU pipeline is hard if hit takes 1 or 2 cycles
– Used in MIPS R1000 L2 cache, similar in UltraSPARC
– Better for caches not tied directly to processor (L2)
Skewed Associative Cache
• Different hash functions for different
banks
• Concurrent version of Pseudo-associative
cache
• Why does it work?
5. Reducing Misses by Hardware
Prefetching of Instructions & Datals
• E.g., Instruction Prefetching
– Alpha 21064 fetches 2 blocks on a miss
– Extra block placed in “stream buffer”
– On miss check stream buffer
• Works with data blocks too:
– Jouppi [1990] 1 data stream buffer got 25% misses from
4KB cache; 4 streams got 43%
– Palacharla & Kessler [1994] for scientific programs for 8
streams got 50% to 70% of misses from
2 64KB, 4-way set associative caches
• Prefetching relies on having extra memory
bandwidth that can be used without penalty
6. Reducing Misses by
Software Prefetching Data
• Data Prefetch
– Load data into register (HP PA-RISC loads)
– Cache Prefetch: load into cache (MIPS IV, PowerPC, SPARC v. 9)
– Special prefetching instructions cannot cause faults; a form of
speculative execution
• Prefetching comes in two flavors:
– Binding prefetch: Requests load directly into register.
» Must be correct address and register!
– Non-Binding prefetch: Load into cache.
» Can be incorrect. Frees HW/SW to guess!
• Issuing Prefetch Instructions takes time
– Is cost of prefetch issues < savings in reduced misses?
– Higher superscalar reduces difficulty of issue bandwidth
7. Reducing Misses by
Compiler Optimizations
• McFarling [1989] reduced caches misses by 75%
on 8KB direct mapped cache, 4 byte blocks in software
• Instructions
– Reorder procedures in memory so as to reduce conflict misses
– Profiling to look at conflicts(using tools they developed)
• Data
– Merging Arrays: improve spatial locality by single array of compound elements
vs. 2 arrays
– Loop Interchange: change nesting of loops to access data in order stored in
memory
– Loop Fusion: Combine 2 independent loops that have same looping and some
variables overlap
– Blocking: Improve temporal locality by accessing “blocks” of data repeatedly
vs. going down whole columns or rows
Merging Arrays Example
/* Before: 2 sequential arrays */
int val[SIZE];
int key[SIZE];
/* After: 1 array of stuctures */
struct merge {
int val;
int key;
};
struct merge merged_array[SIZE];
Reducing conflicts between val & key;
improve spatial locality
Loop Interchange Example
/* Before */
for (k = 0; k < 100; k = k+1)
for (j = 0; j < 100; j = j+1)
for (i = 0; i < 5000; i = i+1)
x[i][j] = 2 * x[i][j];
/* After */
for (k = 0; k < 100; k = k+1)
for (i = 0; i < 5000; i = i+1)
for (j = 0; j < 100; j = j+1)
x[i][j] = 2 * x[i][j];
Sequential accesses instead of striding
through memory every 100 words; improved
spatial locality
Loop Fusion Example
/* Before */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
a[i][j] = 1/b[i][j] * c[i][j];
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
d[i][j] = a[i][j] + c[i][j];
/* After */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
{
a[i][j] = 1/b[i][j] * c[i][j];
d[i][j] = a[i][j] + c[i][j];}
2 misses per access to a & c vs. one miss per
access; improve spatial locality
Blocking Example
/* Before */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
{r = 0;
for (k = 0; k < N; k = k+1){
r = r + y[i][k]*z[k][j];};
x[i][j] = r;
};
• Two Inner Loops:
– Read all NxN elements of z[]
– Read N elements of 1 row of y[] repeatedly
– Write N elements of 1 row of x[]
• Capacity Misses a function of N & Cache Size:
– 2N3 + N2 => (assuming no conflict; otherwise …)
• Idea: compute on BxB submatrix that fits
Blocking Example
/* After */
for (jj = 0; jj < N; jj = jj+B)
for (kk = 0; kk < N; kk = kk+B)
for (i = 0; i < N; i = i+1)
for (j = jj; j < min(jj+B-1,N); j = j+1)
{r = 0;
for (k = kk; k < min(kk+B-1,N); k = k+1) {
r = r + y[i][k]*z[k][j];};
x[i][j] = x[i][j] + r;
};
• B called Blocking Factor
• Capacity Misses from 2N3 + N2 to 2N3/B+N2
• Conflict Misses Too?
Y
1 2 3 4
5 6 7 8
9 10 11 12
13 14 15 16
Z
1 2 3 4
5 6 7 8
9 10 11 12
13 14 15 16
Y1*Z1, Y5*Z1, Y9*Z1, Y13*Z1, Y2*Z5, Y6*Z5, Y10*Z5, Y14*Z5,
Y3*Z9, Y7*Z9, Y11*Z9, Y15*Z9, Y4*Z13, Y8*Z13, Y12*Z13, Y16*Z13
Y1*Z2, Y5*Z2, Y9*Z2, Y13*Z2, Y2*Z6, Y6*Z6, Y10*Z6, Y14*Z6,
Y3*Z10, Y7*Z10, Y11*Z10, Y15*Z10, Y4*Z14, Y8*Z14, Y12*Z14, Y16*Z14
Reducing Conflict Misses by Blocking
Miss Rate
0.1
Direct Mapped Cache
0.05
Fully Associative Cache
0
0
50
100
150
Blocking Factor
• Conflict misses in caches not FA vs. Blocking size
– Lam et al [1991] a blocking factor of 24 had a fifth the misses
vs. 48 despite both fit in cache
Summary of Compiler Optimizations to
Reduce Cache Misses (by hand)
vpenta (nasa7)
gmty (nasa7)
tomcatv
btrix (nasa7)
mxm (nasa7)
spice
cholesky
(nasa7)
compress
1
1.5
2
2.5
3
Performance Improvement
merged
arrays
loop
interchange
loop fusion
blocking
Summary: Miss Rate Reduction

CPUtime  IC  CPI

E xecutio n

Memory accesses

 Miss rate Miss penalty  Clock cycle time

Instruction
• 3 Cs: Compulsory, Capacity, Conflict
1.
2.
3.
4.
5.
6.
7.
Reduce Misses via Larger Block Size
Reduce Misses via Higher Associativity
Reducing Misses via Victim Cache
Reducing Misses via Pseudo-Associativity
Reducing Misses by HW Prefetching Instr, Data
Reducing Misses by SW Prefetching Data
Reducing Misses by Compiler Optimizations
• Prefetching comes in two flavors:
– Binding prefetch: Requests load directly into register.
» Must be correct address and register!
– Non-Binding prefetch: Load into cache.
» Can be incorrect. Frees HW/SW to guess!
Improving Cache Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.
Write Policy:
Write-Through vs Write-Back
• Write-through: all writes update cache and underlying
memory/cache
– Can always discard cached data - most up-to-date data is in memory
– Cache control bit: only a valid bit
• Write-back: all writes simply update cache
– Can’t just discard cached data - may have to write it back to memory
– Cache control bits: both valid and dirty bits
• Other Advantages:
– Write-through:
» memory (or other processors) always have latest data
» Simpler management of cache
– Write-back:
» much lower bandwidth, since data often overwritten multiple times
» Better tolerance to long-latency memory?
WT vs. WB
• Write burst
• Error tolerance
• Speculative write: DB and WT
What happens on a Cache miss?
• For in-order pipeline, 2 options:
– Freeze pipeline in Mem stage (popular early on: Sparc, R4000)
IF
ID
IF
EX
ID
Mem stall stall stall … stall Mem
Wr
EX stall stall stall … stall stall Ex Wr
– Use Full/Empty bits in registers + MSHR queue
» MSHR = “Miss Status/Handler Registers” (Kroft)
Each entry in this queue keeps track of status of outstanding
memory requests to one complete memory line.
• Per cache-line: keep info about memory address.
• For each word: register (if any) that is waiting for result.
• Used to “merge” multiple requests to one memory line
» New load creates MSHR entry and sets destination register to
“Empty”. Load is “released” from pipeline.
» Attempt to use register before result returns causes
instruction to block in decode stage.
» Limited “out-of-order” execution with respect to loads.
Popular with in-order superscalar architectures.
• Out-of-order pipelines already have this functionality
built in… (load queues, etc).
Write Policy 2:
Write Allocate vs Non-Allocate
(What happens on write-miss)
• Write allocate: allocate new cache line in cache
– Usually means that you have to do a “read miss” to
fill in rest of the cache-line!
– Alternative: per/word valid bits
• Write non-allocate (or “write-around”):
– Simply send write data through to underlying
memory/cache - don’t allocate new cache line!
Write Miss Policy
•
•
•
•
Allocate and fetch: normal
Allocate but no fetch
No allocate: write around/bypassing
Cacheability
Review: Improving Cache
Performance
AMAT  HitTime  MissRate  MissPenalty
1. Reduce the miss rate,
2. Reduce the time to hit in the cache.
3. Reduce the miss penalty
1. Fast Hit times
via Small and Simple Caches
• Why Alpha 21164 has 8KB Instruction and
8KB data cache + 96KB second level cache?
– Small data cache and clock rate
• Direct Mapped, on chip
2. Fast hits by Avoiding Address
Translation
• Send virtual address to cache? Called Virtually Addressed Cache or
just Virtual Cache vs. Physical Cache
– Every time process is switched logically must flush the cache; otherwise get false
hits
» Cost is time to flush + “compulsory” misses from empty cache
– Dealing with aliases (sometimes called synonyms);
Two different virtual addresses map to same physical address
– I/O must interact with cache, so need virtual address
• Solution to aliases
– HW guaranteess covers index field & direct mapped, they must be unique;
called page coloring
• Solution to cache flush
– Add process identifier tag that identifies process as well as address within
process: can’t get a hit if wrong process
Virtual Memory Hardware
• Translation Lookaside Buffer (TLB): cache
for page table entries
• Typically full associative
• Block size?
• TLB refill: HW or SW
• Variable page size
• Process ID in TLB tags
Virtually Addressed Caches
CPU
CPU
VA
VA
VA
VA
Tags
TB
CPU
PA
Tags
$
$
TB
VA
PA
PA
L2 $
TB
$
PA
PA
MEM
MEM
Conventional
Organization
Virtually Addressed Cache
Translate only on miss
Synonym Problem
MEM
Overlap $ access
with VA translation:
requires $ index to
remain invariant
across translation
Virtually Indexed and Tagged
• Homonym problem
– A1 in P1 and A1 in P2 are mapped to different PA
– Process ID comes into rescue
• Synonym problem
– A1 in P1 and A2 in P2 are mapped to same PA
– Multiple copies of PA  inconsistent
– For direct-mapped cache, if the index part of A1 and
A2 are the same, or if A1 and A2 are mapped to the
same cache set, it is OK.
Virtually Indexed Physically Tagged
• If index is physical part of address, can
start tag access in parallel with translation
so that can compare to physical tag
31
Page Address
Address Tag
12 11
Page Offset
Index
0
Block Offset
• Limits cache to page size: what if want
bigger caches and uses same trick?
– Higher associativity moves barrier to right
– Page coloring
3. Fast Hit Times Via Pipelined
Writes
• Pipeline Tag Check and Update Cache as separate stages; current
write tag check & previous write cache update
• Only STORES in the pipeline; empty during a miss
Store r2, (r1)
Add
Sub
Store r4, (r3)
Check r1
--M[r1]<-r2&
check r3
• In shade is “Delayed Write Buffer”; must be checked on reads;
either complete write or read from buffer
4. Fast Writes on Misses Via
Small Subblocks
• If most writes are 1 word, subblock size is 1 word, &
write through then always write subblock & tag
immediately
– Tag match and valid bit already set: Writing the block was proper, &
nothing lost by setting valid bit on again.
– Tag match and valid bit not set: The tag match means that this is the
proper block; writing the data into the subblock makes it appropriate to
turn the valid bit on.
– Tag mismatch: This is a miss and will modify the data portion of the
block. Since write-through cache, no harm was done; memory still has
an up-to-date copy of the old value. Only the tag to the address of
the write and the valid bits of the other subblock need be changed
because the valid bit for this subblock has already been set
• Doesn’t work with write back due to last case
Review: Improving Cache
Performance
AMAT  HitTime  MissRate  MissPenalty
1. Reduce the miss rate,
2. Reduce the time to hit in the cache.
3. Reduce the miss penalty
0. Faster Memory
• This requires a bit of discussion.
• Hold a bit until we discuss memory.
1. Reducing Miss Penalty:
Read Priority over Write on Miss
• Write through with write buffers offer RAW
conflicts with main memory reads on cache misses
– If simply wait for write buffer to empty, might increase read
miss penalty (old MIPS 1000 by 50% )
– Check write buffer contents before read;
if no conflicts, let the memory access continue
• Alternative: Write Back
– Read miss replacing dirty block
– Normal: Write dirty block to memory, and then do the read
– Instead copy the dirty block to a write buffer, then do the
read, and then do the write
– CPU stall less since restarts as soon as do read
1. Reducing Penalty: Read Priority
over Write on Miss
Processor
Cache
DRAM
Write Buffer
• Write Buffer is needed between the Cache and Memory
– Processor: writes data into the cache and the write buffer
– Memory controller: write contents of the buffer to memory
• Write buffer is just a FIFO:
– Typical number of entries: 4
– Works fine if:Store frequency (w.r.t. time) << 1 / DRAM write cycle
– Must handle burst behavior as well!
RAW Hazards from Write Buffer!
• Write-Buffer Issues: Could introduce RAW Hazard with memory!
– Write buffer may contain only copy of valid data 
Reads to memory may get wrong result if we ignore write buffer
• Solutions:
– Simply wait for write buffer to empty before servicing reads:
» Might increase read miss penalty (old MIPS 1000 by 50% )
– Check write buffer contents before read (“fully associative”);
» If no conflicts, let the memory access continue
» Else grab data from buffer
• Can Write Buffer help with Write Back?
– Read miss replacing dirty block
» Copy dirty block to write buffer while starting read to memory
3
8
3
8
RAS/
CAS
Write
DATA
RAS/
CAS
Read
DATA
Processor + DRAM
DRAM
Proc
3
8
3
8
RAS/
CAS
Read
DATA
RAS/
CAS
Write
DATA
8
Write
DATA
8
Read
DATA
2. Reduce Miss Penalty:
Subblock Placement
• Don’t have to load full block on a miss
• Have valid bits per subblock to indicate valid
• (Originally invented to reduce tag storage)
Valid Bits
Subblocks
3. Reduce Miss Penalty:
Early Restart and Critical Word
First
• Don’t wait for full block to be loaded before
restarting CPU
– Early restart—As soon as the requested word of the block
arrives, send it to the CPU and let the CPU continue execution
– Critical Word First—Request the missed word first from memory
and send it to the CPU as soon as it arrives; let the CPU continue
execution while filling the rest of the words in the block. Also
called wrapped fetch and requested word first
• Generally useful only in large blocks,
• Spatial locality a problem; tend to want next
sequential word, so not clear if benefit by early
restart
block
4. Reduce Miss Penalty:
Non-blocking Caches to reduce stalls
on misses
• Non-blocking cache or lockup-free cache allow data
cache to continue to supply cache hits during a miss
– requires F/E bits on registers or out-of-order execution
– requires multi-bank memories
• “hit under miss” reduces the effective miss penalty
by working during miss vs. ignoring CPU requests
• “hit under multiple miss” or “miss under miss” may
further lower the effective miss penalty by
overlapping multiple misses
– Significantly increases the complexity of the cache controller as
there can be multiple outstanding memory accesses
– Requires multiple memory banks (otherwise cannot support)
– Penium Pro allows 4 outstanding memory misses
Value of Hit Under Miss for SPEC
Hit Under i Misses
2
1.8
Avg. Mem. Acce ss Time
1.6
1.4
0->1
1.2
1->2
1
2->64
0.8
B as e
0.6
0.4
0->1
1->2
2->64
Base
“Hit under n Misses”
0.2
Integer
ora
spice2g6
nasa7
alvinn
hydro2d
mdljdp2
wave5
su2cor
doduc
swm256
tomcatv
fpppp
ear
mdljsp2
compress
xlisp
espresso
eqntott
0
Floating Point
• FP programs on average: AMAT= 0.68 -> 0.52 -> 0.34 -> 0.26
• Int programs on average: AMAT= 0.24 -> 0.20 -> 0.19 -> 0.19
• 8 KB Data Cache, Direct Mapped, 32B block, 16 cycle miss
5. Second level cache
• L2 Equations
AMAT = Hit TimeL1 + Miss RateL1 x Miss PenaltyL1
Miss PenaltyL1 = Hit TimeL2 + Miss RateL2 x Miss PenaltyL2
AMAT = Hit TimeL1 +
Miss RateL1 x (Hit TimeL2 + Miss RateL2 + Miss PenaltyL2)
• Definitions:
– Local miss rate— misses in this cache divided by the total number of
memory accesses to this cache (Miss rateL2)
– Global miss rate—misses in this cache divided by the total number of
memory accesses generated by the CPU
(Miss RateL1 x Miss RateL2)
– Global Miss Rate is what matters
Comparing Local and Global
Miss Rates
• 32 KByte 1st level cache;
Increasing 2nd level cache
• Global miss rate close to single
level cache rate provided L2 >>
L1
• Don’t use local miss rate
• L2 not tied to CPU clock cycle!
• Cost & A.M.A.T.
• Generally Fast Hit Times and
fewer misses
• Since hits are few, target miss
reduction
Linear
Cache Size
Log
Cache Size
Reducing Misses:
Which apply to L2 Cache?
• Reducing Miss Rate
1.
2.
3.
4.
5.
6.
7.
Reduce Misses via Larger Block Size
Reduce Conflict Misses via Higher Associativity
Reducing Conflict Misses via Victim Cache
Reducing Conflict Misses via Pseudo-Associativity
Reducing Misses by HW Prefetching Instr, Data
Reducing Misses by SW Prefetching Data
Reducing Capacity/Conf. Misses by Compiler Optimizations
L2 cache block size &
A.M.A.T.
Relative CPU Time
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.95
1.54
1.36
16
1.28
1.27
32
64
1.34
128
256
Block Size
• 32KB L1, 8 byte path to memory
512
Reducing Miss Penalty Summary

CPUtime  IC  CPI

E xecutio n

Memory accesses

 Miss rate Miss penalty  Clock cycle time

Instruction
• Five techniques
–
–
–
–
–
Read priority over write on miss
Subblock placement
Early Restart and Critical Word First on miss
Non-blocking Caches (Hit under Miss, Miss under Miss)
Second Level Cache
• Can be applied recursively to Multilevel Caches
– Danger is that time to DRAM will grow with multiple levels in
between
– First attempts at L2 caches can make things worse, since
increased worst case is worse
Cache Optimization Summary
hit time
miss
penalty
miss rate
Technique
Larger Block Size
Higher Associativity
Victim Caches
Pseudo-Associative Caches
HW Prefetching of Instr/Data
Compiler Controlled Prefetching
Compiler Reduce Misses
Priority to Read Misses
Subblock Placement
Early Restart & Critical Word 1st
Non-Blocking Caches
Second Level Caches
Small & Simple Caches
Avoiding Address Translation
Pipelining Writes
MR
+
+
+
+
+
+
+
MP HT
–
+
+
+
+
+
–
–
+
+
+
+
Complexity
0
1
2
2
2
3
0
1
1
2
3
2
0
2
1
What is the Impact of What
You’ve Learned About Caches?
1000
2000
1999
1998
1997
1996
1995
1994
1993
1992
DRA M
1991
1990
1989
1988
1987
1986
1985
1984
1983
1982
1981
1980
• 1960-1985: Speed
= ƒ(no. operations)
• 1990
100
– Pipelined
Execution &
Fast Clock Rate
10
– Out-of-Order
execution
– Superscalar
Instruction Issue 1
• 1998: Speed =
ƒ(non-cached memory accesses)
• What does this mean for
– Compilers?,Operating Systems?, Algorithms?
Data Structures?
CPU
Cache Parameter Estimation
• D: cache size, b: cache line size, a: degree of
associativity
• A strided access to an N-element array, with stride
being s, s=1, 2, 4, … N/2
• Each iteration contains a read and write of the same
array element
• Four cases:
– N <= D  Tno-miss
– N > D and 1<= s < b: Tno-miss + Ms/b
– N > D and N/s > D/b and b <= s < N/a: Tnomiss + M
– N> D and N/a <= s <= N/2 : Tno-miss
Virtual Memory Hardware in X86
Architecture
Virtual Address
Segment Selector
Offset
TI PL
Physical Address
Linear Address Two-Level
Page Table
GDT/LDT
Base
31:24
Limit
P DPL
19:16
Base
15:00
Base
23:16
Limit
15:00
Segment Descriptor Format
Page Frame Address
Page Table Entry Format
U W P
Segment Limit Check
X86 architecture’s virtual memory hardware
supports both segmentation and paging
Virtual Address = Segment Selector + Offset
segmentation
base + offset <= limit
Linear Address
paging
Physical Address
Array Bound Checking
•
•
Prevent unauthorized modification of the
address space (e.g., return address or
bank account) through buffer overflowing
 The cleanest solution
Check each memory reference with respect
to the upper/lower limits of its associated
object
1. Figure out which is the associated object
2. Perform the limit check (more time-consuming)
•
Current software-based array bound
checking methods: 2-30 times slowdown
The CASH Approach
• Goal: Exploiting segment limit check
hardware to perform array bound checking
for free
• Idea: Each array or buffer is treated as a
separate segment and referenced
accordingly
offset = &(B[M]) – B_Segment_Base;
for (i = M; i < N; I++) {
B[i] = 5;
GS = B_Segment_Selector;
for (i = M; i < N; i++) {
}
GS:offset = 5;
offset += 4;
}
Array Access Code Generation
A[i] = 10
Without Array Bound Check
movl
leal
movl
movl
-60(%ebp), %eax
0(, %eax, 4), %edx
-56(%ebp), %eax
$10, (%edx, %eax)
;
;
;
;
load i
i * 4
load a
mem[a+4*i] = 10
Checking Array Bound using Cash
movl
leal
movl
movw
movw
subl
movl
-60(%ebp), %eax
0(, %eax, 4), %edx
-56(%ebp), %eax
-52(%ebp), %ecx
0(%ecx), %gs
4(%ecx), %eax
$10, %gs:(%edx,%eax)
;
;
;
;
;
;
;
load i
i * 4
load a
load a's shadow structure ptr
load GS
compute offset from base
check bounds and Mem[a+4*i]=10
Intra-AS Protection
• A program and an untrusted component: OS
and its device drivers, Apache and CGIs,
Java program and C components, etc.
• Run kernel at SPL0 (0-4GB), extensible
application at SPL2 (0-3GB) and extension
at SPL3 (0-3GB)
• Exposed pages of extensible application at
PPL 1
• Design Issues
– Control transfer
– Data sharing
– Libraries
PaX
• Non-executable stack and heap
• Invariant: VM areas that can be modified
cannot be executed; VM areas that can be
executed cannot be modified
• Partition the address space into two disjoint
segments, one CS and one DS
• Updates happen in DS, and instruction fetch
happen in CS
• Use randomization to address return-to-libc
attacks
Main Memory Background
• Performance of Main Memory:
– Latency: Cache Miss Penalty
» Access Time: time between request and word arrives
» Cycle Time: time between requests
– Bandwidth: I/O & Large Block Miss Penalty (L2)
• Main Memory is DRAM: Dynamic Random Access Memory
– Dynamic since needs to be refreshed periodically (8 ms, 1% time)
– Addresses divided into 2 halves (Memory as a 2D matrix):
» RAS or Row Access Strobe
» CAS or Column Access Strobe
• Cache uses SRAM: Static Random Access Memory
– No refresh (6 transistors/bit vs. 1 transistor
Size: DRAM/SRAM 4-8,
Cost/Cycle time: SRAM/DRAM 8-16
Main Memory Deep Background
•
•
•
•
•
“Out-of-Core”, “In-Core,” “Core Dump”?
“Core memory”?
Non-volatile, magnetic
Lost to 4 Kbit DRAM (today using 64Kbit DRAM)
Access time 750 ns, cycle time 1500-3000 ns
Static vs. Dynamic Memory
6-Transistor SRAM Cell
0
0
bit
word
word
(row select)
1
1
bit
• Write:
1. Drive bit lines (bit=1, bit=0)
2.. Select row
• Read:
bit
replaced with pullup
to save area
1. Precharge bit and bit to Vdd or Vdd/2 => make sure equal!
2.. Select row
3. Cell pulls one line low
4. Sense amp on column detects difference between bit and bit
bit
1-Transistor Memory Cell (DRAM)
• Write:
– 1. Drive bit line
– 2.. Select row
• Read:
– 1. Precharge bit line to Vdd/2
– 2.. Select row
bit
– 3. Cell and bit line share charges
» Very small voltage changes on the bit line
– 4. Sense (fancy sense amp)
» Can detect changes of ~1 million electrons
– 5. Write: restore the value
• Refresh
– 1. Just do a dummy read to every cell.
row select
DRAM Capacitors: more
capacitance in a small area
• Trench capacitors:
–
–
–
–
• Stacked capacitors
Logic ABOVE capacitor
Gain in surface area of capacitor
Better Scaling properties
Better Planarization
– Logic BELOW capacitor
– Gain in surface area of capacitor
– 2-dim cross-section quite small
Classical DRAM Organization (square)
bit (data) lines
r
o
w
d
e
c
o
d
e
r
row
address
Each intersection represents
a 1-T DRAM Cell
RAM Cell
Array
word (row) select
Column Selector &
I/O Circuits
data
Column
Address
• Row and Column Address
together:
– Select 1 bit a time
DRAM Read Timing
• Every DRAM access
begins at:
RAS_L
– The assertion of the RAS_L
– 2 ways to read:
early or late v. CAS
CAS_L
A
WE_L
256K x 8
DRAM
9
OE_L
D
8
DRAM Read Cycle Time
RAS_L
CAS_L
A
Row Address
Col Address
Junk
Row Address
Col Address
Junk
WE_L
OE_L
D
High Z
Junk
Data Out
Read Access
Time
Early Read Cycle: OE_L asserted before CAS_L
High Z
Data Out
Output Enable
Delay
Late Read Cycle: OE_L asserted after CAS_L
4 Key DRAM Timing
Parameters
• tRAC: minimum time from RAS line falling to the
valid data output.
– Quoted as the speed of a DRAM when buy
– A typical 4Mb DRAM tRAC = 60 ns
– Speed of DRAM since on purchase sheet?
• tRC: minimum time from the start of one row access
to the start of the next.
– tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns
• tCAC: minimum time from CAS line falling to valid
data output.
– 15 ns for a 4Mbit DRAM with a tRAC of 60 ns
• tPC: minimum time from the start of one column
access to the start of the next.
– 35 ns for a 4Mbit DRAM with a tRAC of 60 ns
Main Memory Performance
Cycle Time
Access Time
Time
• DRAM (Read/Write) Cycle Time >> DRAM
(Read/Write) Access Time
– 2:1; why?
• DRAM (Read/Write) Cycle Time :
– How frequent can you initiate an access?
– Analogy: A little kid can only ask his father for money on
Saturday
• DRAM (Read/Write) Access Time:
– How quickly will you get what you want once you initiate an
access?
– Analogy: As soon as he asks, his father will give him the money
• DRAM Bandwidth Limitation analogy:
– What happens if he runs out of money on Wednesday?
Increasing Bandwidth - Interleaving
Access Pattern without Interleaving:
CPU
Memory
D1 available
Start Access for D1
Start Access for D2
Memory
Bank 0
Access Pattern with 4-way Interleaving:
CPU
Memory
Bank 1
Access Bank 0
Memory
Bank 2
Memory
Bank 3
Access Bank 1
Access Bank 2
Access Bank 3
We can Access Bank 0 again
Main Memory Performance
• Wide:
• Simple:
– CPU/Mux 1 word;
Mux/Cache, Bus,
Memory N words
(Alpha: 64 bits &
256 bits)
– CPU, Cache, Bus, Memory
same width
(32 bits)
• Interleaved:
– CPU, Cache, Bus 1 word:
Memory N Modules
(4 Modules); example is
word interleaved
Main Memory Performance
• Timing model
– 1 to send address,
– 4 for access time, 10 cycle time, 1 to send data
– Cache Block is 4 words
• Simple M.P.
= 4 x (1+10+1) = 48
• Wide M.P.
= 1 + 10 + 1
= 12
• Interleaved M.P. = 1+10+1 + 3 =15
address
address
address
address
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
Bank 0
Bank 1
Bank 2
Bank 3
Avoiding Bank Conflicts
• Lots of banks
int x[256][512];
for (j = 0; j < 512; j = j+1)
for (i = 0; i < 256; i = i+1)
x[i][j] = 2 * x[i][j];
• Even with 128 banks, since 512 is multiple of 128, conflict on
word accesses
• SW: loop interchange or declaring array not power of 2 (“array
padding”)
• HW: Prime number of banks
–
–
–
–
–
bank number = address mod number of banks
address within bank = address / number of words in bank
modulo & divide per memory access with prime no. banks?
address within bank = address mod number words in bank
bank number? easy if 2N words per bank
Fast Bank Number
• Chinese Remainder Theorem
As long as two sets of integers ai and bi follow these rules
bi  x mod ai,0  bi  ai, 0  x  a 0  a1  a 2 
and that ai and aj are co-prime if i  j, then the integer x has only one
solution (unambiguous mapping):
– bank number = b0, number of banks = a0 (= 3 in example)
– address within bank = b1, number of words in bank = a1
(= 8 in example)
– N word address 0 to N-1, prime no. banks, words power of 2
Bank Number:
Address
within Bank: 0
1
2
3
4
5
6
7
Seq. Interleaved
0
1
2
0
3
6
9
12
15
18
21
1
4
7
10
13
16
19
22
2
5
8
11
14
17
20
23
Modulo Interleaved
0
1
2
0
9
18
3
12
21
6
15
16
1
10
19
4
13
22
7
8
17
2
11
20
5
14
23
Alternative:Incremental
Computation
V = <Z, F, S, L, R>
Z + F*R = W1 * D + B1
S*R = Kw * D + Kb
W2 = (Z+ F*R + S*R) / D
= W1 + Kw + (B1+Kb) / D
B2 = (Z+ F*R + S*R) mod D
= (B1 + Kb) mod D
Independent Memory Banks
• Memory banks for independent accesses
vs. faster sequential accesses
– Multiprocessor
– I/O
– CPU with Hit under n Misses, Non-blocking Cache
• Superbank: all memory active on one block transfer
(or Bank)
• Bank: portion within a superbank that is word
interleaved (or Subbank)
…
Superbank
Superbank Number
Bank
Superbank Offset
Bank Number
Bank Offset
Independent Memory Banks
• How many banks?
number banks  number clocks to access word in bank
– For sequential accesses, otherwise will return to original bank
before it has next word ready
– (like in vector case)
• Increasing DRAM => fewer chips => harder to have
banks
Fast Memory Systems: DRAM specific
• Multiple CAS accesses: several names (page mode)
– Extended Data Out (EDO): 30% faster in page mode
• New DRAMs to address gap;
what will they cost, will they survive?
– RAMBUS: startup company; reinvent DRAM interface
» Each Chip a module vs. slice of memory
» Short bus between CPU and chips
» Does own refresh
» Variable amount of data returned
» 1 byte / 2 ns (500 MB/s per chip)
– Synchronous DRAM: 2 banks on chip, a clock signal to DRAM, transfer
synchronous to system clock (66 - 150 MHz)
– Intel claims RAMBUS Direct (16 b wide) is future PC memory
• Niche memory or main memory?
– e.g., Video RAM for frame buffers, DRAM + fast serial output
Fast Page Mode Operation
– N rows x N column x M-bit
– Read & Write M-bit at a time
– Each M-bit access requires
a RAS / CAS cycle
• Fast Page Mode DRAM
– N x M “SRAM” to save a row
Column
Address
N cols
DRAM
Row
Address
N rows
• Regular DRAM Organization:
• After a row is read into the
register
– Only CAS is needed to access
other M-bit blocks on that row
– RAS_L remains asserted while
CAS_L is toggled
1st M-bit Access
N x M “SRAM”
M bits
M-bit Output
2nd M-bit
3rd M-bit
4th M-bit
Col Address
Col Address
Col Address
RAS_L
CAS_L
A
Row Address
Col Address
SDRAM timing
CAS
RAS
(New Bank)
x
CAS Latency
• Micron 128M-bit dram (using 2Meg16bit4bank ver)
– Row (12 bits), bank (2 bits), column (9 bits)
End RAS
Burst
READ
DRAM History
• DRAMs: capacity +60%/yr, cost –30%/yr
– 2.5X cells/area, 1.5X die size in 3 years
• ‘98 DRAM fab line costs $2B
– DRAM only: density, leakage v. speed
• Rely on increasing no. of computers & memory per
computer (60% market)
– SIMM or DIMM is replaceable unit
=> computers use any generation DRAM
• Commodity, second source industry
=> high volume, low profit, conservative
– Little organization innovation in 20 years
• Order of importance: 1) Cost/bit 2) Capacity
– First RAMBUS: 10X BW, +30% cost => little impact
DRAM Future: 1 Gbit+ DRAM
•
•
•
•
Blocks
Clock
Data Pins
Die Size
Mitsubishi
512 x 2 Mbit
200 MHz
64
24 x 24 mm
Samsung
1024 x 1 Mbit
250 MHz
16
31 x 21 mm
– Sizes will be much smaller in production
• Metal Layers
• Technology
3
0.15 micron
4
0.16 micron
Minimum Memory Size
DRAMs per PC over Time
‘86
1 Mb
32
4 MB
8 MB
16 MB
32 MB
64 MB
DRAM Generation
‘89
‘92
‘96
‘99
‘02
4 Mb 16 Mb 64 Mb 256 Mb 1 Gb
8
16
4
8
2
4
1
8
2
128 MB
4
1
256 MB
8
2
Potential
DRAM Crossroads?
• After 20 years of 4X every 3 years,
running into wall? (64Mb - 1 Gb)
• How can keep $1B fab lines full if buy
fewer DRAMs per computer?
• Cost/bit –30%/yr if stop 4X/3 yr?
• What will happen to $40B/yr DRAM
industry?
Cache Cross Cutting Issues
• Superscalar CPU & Number Cache Ports
must match: number memory
accesses/cycle?
• Speculative Execution and non-faulting
option on memory/TLB
• Parallel Execution vs. Cache locality
– Want far separation to find independent operations vs.
want reuse of data accesses to avoid misses
• Cache consistency in I/O and MP => multiple
copies of data
– Consistency
Alpha 21064
• Separate Instr & Data
TLB & Caches
• TLBs fully associative
• TLB updates in SW
(“Priv Arch Libr”)
• Caches 8KB direct
mapped, write thru
• Critical 8 bytes first
• Prefetch instr. stream
buffer
• 2 MB L2 cache, direct
mapped, WB (off-chip)
• 256 bit path to main
memory, 4 x 64-bit
modules
• Victim Buffer: to give
read priority over
write
• 4 entry write buffer
between D$ & L2$
Instr
Data
Write
Buffer
Stream
Buffer
Victim Buffer
Alpha Memory Performance:
Miss Rates of SPEC92
100.00%
AlphaSort
I$ miss = 6%
D$ miss = 32%
L2 miss = 10%
Li
Compress
Ear
Tomcatv
Spice
Miss Rate
10.00%
I$
8K
D $ 8K
1.00%
L2 2M
0.10%
0.01%
I$ miss = 2%
D$ miss = 13%
L2 miss =
0.6%
I$ miss = 1%
D$ miss = 21%
L2 miss = 0.3%
Alpha CPI Components
CPI
• Instruction stall: branch mispredict (green);
• Data cache (blue); Instruction cache (yellow); L2$ (pink)
Other: compute + reg conflicts, structural conflicts
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
AlphaSort Espresso
L2
I$
D$
I Stall
Other
Sc
Mdljsp2
Ear
Alvinn
Mdljp2
Pitfall: Predicting Cache Performance
from Different Prog.
(ISA, compiler, ...)
35%
D$, Tom
30%
D: tomcatv
• 4KB Data cache miss
rate 8%,12%, or
25%
28%?
• 1KB Instr cache miss
D$, gcc
20%
rate 0%,3%,or 10%?Miss
Rate
• Alpha vs. MIPS
15% D$, esp
for 8KB Data $:
17% vs. 10%
10%
• Why 2X Alpha v.
MIPS?
I$, gcc
D: gcc
D: espresso
I: gcc
I: espresso
I: tomcatv
5%
0%I$, esp
1
2
I$, Tom
4
8
16
Cache Size (KB)
32
64
128
Pitfall: Simulating Too Small
an Address Trace
4.5
4
Cummlati
3.5
ve
3
Average
Memory 2.5
Access
2
Time
1.5
1
I$ = 4 KB, B=16B
0
D$ = 4 KB, B=16B
L2 = 512 KB, B=128B
MP = 12, 200
1
2
3
4
5
6
7
8
9 10 11 12
Instructions Executed (billions)
Another Level of Indirection
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Masking physical memory errors
Copy on write
Locality enhancement
L2 cache management
DRAM-Based Cache
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Slow and need refreshing
Slow -> Larger transistor
Refreshing  no access means invalid
Similar technique used in switch/router
buffer
Memory Wall
• What if the CPU is so fast that we cannot
even afford compulsory misses
• Intelligent RAM (IRAM) or Processor-inMemory
• Fast data copying within DRAM
• Memory-oriented architecture: assuming
processing logic is abundant
Need for Error Correction!
• Motivation:
– Failures/time proportional to number of bits!
– As DRAM cells shrink, more vulnerable
• Went through period in which failure rate was low enough
without error correction that people didn’t do correction
– DRAM banks too large now
– Servers always corrected memory systems
• Basic idea: add redundancy through parity bits
– Simple but wastful version:
» Keep three copies of everything, vote to find right value
» 200% overhead, so not good!
– Common configuration: Random error correction
» SEC-DED (single error correct, double error detect)
» One example: 64 data bits + 8 parity bits (11% overhead)
– Really want to handle failures of physical components as well
» Organization is multiple DRAMs/SIMM, multiple SIMMs
» Want to recover from failed DRAM and failed SIMM!
» Requires more redundancy to do this
» All major vendors thinking about this in high-end machines
More esoteric Storage Technologies?
• Tunneling Magnetic Junction RAM (TMJ-RAM):
– Speed of SRAM, density of DRAM, non-volatile
(no refresh)
– New field called “Spintronics”: combination of
quantum spin and electronics
– Same technology used in high-density disk-drives
• MEMs storage devices:
– Large magnetic “sled” floating on top of lots of
little read/write heads
– Micromechanical actuators move the sled back
and forth over the heads
Something new: Structure of
Tunneling Magnetic Junction
• Tunneling Magnetic Junction RAM (TMJ-RAM)
– Speed of SRAM, density of DRAM, non-volatile (no
refresh)
– “Spintronics”: combination quantum spin and electronics
– Same technology used in high-density disk-drives
MEMS-based Storage
• Magnetic “sled” floats
on array of read/write
heads
– Approx 250 Gbit/in2
– Data rates:
IBM: 250 MB/s w 1000 heads
CMU: 3.1 MB/s w 400 heads
• Electrostatic actuators
move media around to
align it with heads
– Sweep sled ±50m in < 0.5s
• Capacity estimated to be
in the 1-10GB in 10cm2
See Ganger et all: http://www.lcs.ece.cmu.edu/research/MEMS