Transcript Chapter 7. Basic Processing Unit

UNIT - II
Some Fundamental
Concepts
Fundamental Concepts
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Processor fetches one instruction at a time and
perform the operation specified.
Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
Instruction Register (IR)
Executing an Instruction
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Fetch the contents of the memory location pointed
to by the PC. The contents of this location are
loaded into the IR (fetch phase).
IR ← [[PC]]
Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
Carry out the actions specified by the instruction in
the IR (execution phase).
PC
Instruction
Address
lines
decoder and
MAR
control logic
Memory
bus
MDR
Data
lines
IR
Y
R0
Constant 4
Select
MUX
Add
ALU
control
lines
Sub
A
B
R n - 1
ALU
Carry -in
XOR
TEMP
Z
Processor Organization
Fi gure 7.1. Si ngl e-bus organi zati on of the datapath i nsi de a processor.
Datapath
Textbook Page 413
Internal organization of the
processor
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ALU
Registers for temporary storage
Various digital circuits for executing different micro
operations.(gates, MUX,decoders,counters).
Internal path for movement of data between ALU
and registers.
Driver circuits for transmitting signals to external
units.
Receiver circuits for incoming signals from external
units.
PC:

Keeps track of execution of a program

Contains the memory address of the next instruction to be
fetched and executed.
MAR:
 Holds the address of the location to be accessed.
 I/P of MAR is connected to Internal bus and an O/p to external
bus.
MDR:
 Contains data to be written into or read out of the addressed
location.
 IT has 2 inputs and 2 Outputs.
 Data can be loaded into MDR either from memory bus or from
internal processor bus.
The data and address lines are connected to the internal bus via
MDR and MAR
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Registers:
The processor registers R0 to Rn-1 vary considerably from one
processor to another.
 Registers are provided for general purpose used by
programmer.
 Special purpose registers-index & stack registers.
 Registers Y,Z &TEMP are temporary registers
used by
processor during the execution of some instruction.
Multiplexer:
 Select either the output of the register Y or a constant value 4
to be provided as input A of the ALU.
 Constant 4 is used by the processor to increment the contents
of PC.

ALU:
Used to perform arithmetic and logical
operation.
Data Path:
The registers, ALU and interconnecting bus are
collectively referred to as the data path.
Register Transfers
Internal processor
bus
Riin
Ri
Riout
Yin
Y
Constant 4
Select
MUX
A
B
ALU
Zin
Z
Textbook Page 416
Zout
Figure 7.2. Input and output gating for the registers in Figure 7.1.
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The input and output gates for register Ri are
controlled by signals isRin and Riout .
Rin Is set to1 – data available on common bus
are loaded into Ri.
Riout Is set to1 – the contents of register are
placed on the bus.
Riout Is set to 0 – the bus can be used for
transferring data from other registers .
Data transfer between two
registers:
EX:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting
R1out=1. This places the contents of R1 on
the processor bus.
2. Enable input of register R4 by setting
R4in=1. This loads the data from the
processor bus into register R4.
Architecture
Internal processor
bus
Riin
Ri
Riout
Yin
Y
Constant 4
Select
MUX
A
B
ALU
Zin
Z
Zout
Figure 7.2. Input and output gating for the registers in Figure 7.1.
Performing an Arithmetic or
Logic Operation
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The ALU is a combinational circuit that has no
internal storage.
ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
What is the sequence of operations to add the
contents of register R1 to those of R2 and store the
result in R3?
1.
2.
3.
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in
Step 1: Output of the register R1 and input of
the register Y are enabled, causing the
contents of R1 to be transferred to Y.
Step 2: The multiplexer’s select signal is set to
select Y causing the multiplexer to gate the
contents of register Y to input A of the ALU.
Step 3: The contents of Z are transferred to the
destination register R3.
1
Q
Ri in
Riout
Clock
Figure 7.3. Input and outputating
g for one gister
re
bit.
Register Transfers
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All operations and data transfers are controlled by the processor clock.
Figure 7.3. Input and output gating for one register bit.
data lines
MDRoutE
MDRout
bus
MDR
MDR inE
MDRin
Figure 7.4. Connection and control signals for
gister
re MDR.
Fetching a Word from Memory
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Address into MAR; issue Read operation; data into MDR.
Figure 7.4. Connection and control signals for register MDR.
Fetching a Word from Memory
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The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).
Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
Timing
Assume MAR
is always available
on the address lines
of the memory bus.
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Move (R1), R2
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in
storing a word in memory
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Address is loaded into MAR
Data to be written loaded into MDR.
Write command is issued.
Example:Move R2,(R1)
R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC
Execution of a Complete
Instruction
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Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the
memory location pointed to by R3)
Perform the addition
Load the result into R1
5
R1out , Y in , WMF C
6
MDR out , SelectY,Add, Zin
7
Zout , R1 in , End
PC
Instruction
Address
lines
decoder and
MAR
control logic
Memory
bus
MDR
Data
lines
IR
Execution of a Complete
Instruction
Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.
Y
R0
Constant 4
Select
MUX
Add
ALU
control
lines
Sub
A
B
R n - 1
ALU
Carry -in
XOR
TEMP
Z
Figure 7.1. Single-bus organization of the datapath inside a processor.
Add (R3), R1
Execution of Branch
Instructions
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A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given
in the branch instruction.
The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
UnConditional branch
Execution of Branch
Instructions
Step Action
1
PCout , MAR in , Read, Select4,Add, Z in
2
Zout , PCin , Yin , WMF C
3
MDR out , IR in
4
Offset-field-of-IRout, Add, Z in
5
Z out , PCin , End
Figure 7.7. Control sequence for an unconditional branch instruction.
Bus A
Bus B
Bus C
Incrementer
PC
Register
f ile
MUX
Constant 4
A
ALU
R
B
Instruction
decoder
IR
MDR
MAR
Multiple-Bus Organization
Memory b
us
data lines
Address
lines
Figure 7.8. T hree-b
us organization of the datapath.
Textbook Page 424
• Allow the contents of two
different registers to be
accessed simultaneously and
have their contents placed on
buses A and B.
• Allow the data on bus C to
be loaded into a third register
during the same clock cycle.
• Incrementer unit.
• ALU simply passes one of
its two input operands
unmodified to bus C
 control signal: R=A or R=B
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General purpose registers are combined into
a single block called registers.
3 ports,2 output ports –access two different
registers and have their contents on buses A
and B
Third port allows data on bus c during same
clock cycle.
Bus A & B are used to transfer the source
operands to A & B inputs of the ALU.
ALU operation is performed.
The result is transferred to the destination
over the bus C.
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ALU may simply pass one of its 2 input operands
unmodified to bus C.
The ALU control signals for such an operation R=A
or R=B.
Incrementer unit is used to increment the PC by 4.
Using the incrementer eliminates the need to add
the constant value 4 to the PC using the main ALU.
The source for the constant 4 at the ALU input
multiplexer can be used to increment other address
such as loadmultiple & storemultiple
Multiple-Bus Organization
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Add R4, R5, R6
Step Action
1
PCout, R=B, MAR in , Read, IncPC
2
WMFC
3
MDR outB , R=B, IR in
4
R4outA , R5outB , SelectA, Add, R6in , End
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.
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Step 1:The contents of PC are passed
through the ALU using R=B control signal &
loaded into MAR to start a memory read
operation
At the same time PC is incrementer by 4
Step 2:The processor waits for MFC
Step 3: Loads the data ,received into MDR
,then transfers them to IR.
Step 4: The execution phase of the
instruction requires only one control step to
complete.
Instruction
Address
lines
decoder and
MAR
control logic
Memory
bus
MDR
Data
lines
IR
Y
R0
Constant 4
Select
MUX
Add
ALU
control
lines
Sub
A
B
R n - 1
ALU
Carry -in
XOR
TEMP
Z
Figure 7.1. Single-bus organization of the datapath inside a processor.
Exercise
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What is the control
sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
Hardwired Control
Overview
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To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
Two categories: hardwired control and
microprogrammed control
Hardwired system can operate at high speed;
but with little flexibility.
Control Unit Organization
Clock
CLK
Control step
counter
External
inputs
IR
Decoder/
encoder
Condition
codes
Control signals
Figure 7.10. Control unit organization.
External
inputs
INS2
IR
Instruction
decoder
Encoder
Condition
codes
INSm
Run
End
Control signals
Figure 7.11. Separation of the decoding and encoding functions.
Detailed Block Description
Generating Zin
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Zin = T1 + T6 • ADD + T4 • BR + …
Branch
T4
Add
T6
T1
Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
Branch<0
Add
Branch
N
T7
N
T5
T4
T5
Generating End
End
Figure 7.13. Generation of the End control signal.
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End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Instruction
cache
Data
cache
Bus interface
Processor
Sy stem us
b
Main
memory
Input/
Output
Figure 7.14. Block diagram of a complete processor
.
A Complete Processor
Microprogrammed
Control
PCin
PCout
MAR in
Read
MDRout
IRin
Yin
Select
Add
Zin
Z out
R1out
R1in
R3out
WMFC
End
Microprogrammed Control
Micro instruction
1
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
2
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
3
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
4
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
5
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
6
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
7
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
Figure 7.15 An example of microinstructions for Figure 7.6.
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Control signals are generated by a program similar to machine
language programs.
Control Word (CW); microroutine; microinstruction : Textbook page430
3
MDR out , IR in
4
R3out , MAR in , Read
5
R1out , Y in , WMF C
6
MDR out , SelectY,Add, Zin
7
Zout , R1 in , End
Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.
Overview
Textbook page 421
Clock
PC
Control
store
CW
Basic organization of a
microprogrammed control unit
Figure 7.16. Basic organization of a microprogrammed control unit.
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Control store
One function
cannot be carried
out by this simple
organization.
Conditional branch
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The previous organization cannot handle the situation when the control
unit is required to check the status of the condition codes or external
inputs to choose between alternative courses of action.
Use conditional branch microinstruction.
AddressMicroinstruction
0
PCout , MAR in , Read, Select4,Add, Z in
1
Zout , PCin , Y in , WMFC
2
MDRout , IR in
3
Branch to starting addressof appropriatemicroroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25
If N=0, then branch to microinstruction0
26
Offset-field-of-IRout , SelectY, Add, Z in
27
Zout , PCin , End
Figure 7.17. Microroutine for the instruction Branch<0.
Microprogrammed Control
External
inputs
IR
Clock
Starting and
branch address
generator
PC
Control
store
Figure 7.18.
Condition
codes
CW
Organization of the control unit to allow
conditional branching in the microprogram.
Microinstructions
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A straightforward way to structure
microinstructions is to assign one bit position
to each control signal.
However, this is very inefficient.
The length can be reduced: most signals are
not needed simultaneously, and many signals
are mutually exclusive.
All mutually exclusive signals are placed in
the same group in binary coding.
F1 (4 bits)
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1010:
1011:
F2 (3 bits)
No transf er 000:
PC
001:
out
MDRout
010:
Zout
011:
R0
100:
out
R1
101:
out
R2
110:
out
R3
111:
out
TEMPout
Of f set
out
F3 (3 bits)
F4 (4 bits)
No transf er000: No transf er 0000: Add
PCin
001: MARin
0001: Sub
IRin
010: MDRin
Zin
011: TEMPin
1111: XOR
R0in
100: Yin
R1in
16 ALU
R2in
f unctions
R3in
F5 (2 bits)
00: No action
01: Read
10: Write
Partial Format for the
Microinstructions
F6
F7
F8
F6 (1 bit)
F7 (1 bit)
F8 (1 bit)
0: SelectY
1: Select4
0: No action
1: WMFC
0: Continue
1: End
Figure 7.19. An example of a partial format for field-encoded microinstructions.
What is the price paid for
this scheme?
Require a little more hardware
Further Improvement
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Enumerate the patterns of required signals in
all possible microinstructions. Each
meaningful combination of active control
signals can then be assigned a distinct code.
Vertical organization
Textbook page 434
Horizontal organization
Microprogram Sequencing
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If all microprograms require only straightforward
sequential execution of microinstructions except for
branches, letting a μPC governs the sequencing
would be efficient.
However, two disadvantages:
Having a separate microroutine for each machine instruction results
in a large total number of microinstructions and a large control store.
Longer execution time because it takes more time to carry out the
required branches.
Example: Add src, Rdst
Four addressing modes: register, autoincrement,
autodecrement, and indexed (with indirect forms).
Textbook page 436
- Bit-ORing
- Wide-Branch Addressing
- WMFC
Mode
Contents of IR
OP code
0 1
11 10
0
Rsrc
87
Address
(octal)
Microinstruction
000
4, Add, Zin
PCout, MARin, Read, Select
001
Zout, PCin, Yin, WMFC
002
MDRout, IRin
003
Branch { PC
PC5,4 
Rdst
4 3
0
Textbook page 439
101 (from Instruction decoder);
[IR10,9]; PC3  [IR 10]  [IR9]  [IR8]}
121
Rsrcout , MARin , Read, Select4, Add,inZ
122
Zout, Rsrcin
123
Branch {PC 170;PC0  [IR8]}, WMFC
170
MDRout, MARin, Read, WMFC
171
MDRout, Yin
172
Rdstout , SelectY
, Add, Zin
173
Zout, Rdstin, End
Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.
Note:Microinstruction at location 170 is not executed for this addressing mode.
Microinstructions with NextAddress Field
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The microprogram we discussed requires several
branch microinstructions, which perform no useful
operation in the datapath.
A powerful alternative approach is to include an
address field as a part of every microinstruction to
indicate the location of the next microinstruction to
be fetched.
Pros: separate branch microinstructions are virtually
eliminated; few limitations in assigning addresses to
microinstructions.
Cons: additional bits for the address field (around
1/6)
Decoding circuits
Microinstructions with NextAddress Field
A R
Control store
I R
Next address
Microinstruction decoder
Control signals
Figure 7.22. Microinstruction-sequencing organization.
002
003
0 0 0 0 0 0 1 1 0 1 0 01 0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00
0
0
0
0
0
1
0
1
0
0
121
122
0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01
0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00
1
0
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
7
7
0
1
2
3
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
00
00
01
10
0
0
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
01
00
00
00
Implementation of the
Microroutine
Figure 7.24. Implementation of the microroutine of Figure 7.21 using a
next-microinstruction address field.
(See Figure 7.23 for encoded signals.)
Other control signals
Figure 7.25. Some details of the control-signal-generating circuitry.
bit-ORing
Further Discussions
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
Prefetching
Emulation