Transcript Two Transistor Current Source

CO2006: Electronics II, Spring 20010
Integrated Circuit Biasing and
Active Loads
張大中
中央大學 通訊工程系
[email protected]
中央大學 通訊系 張大中
Electronics II, 2010
1
Two Transistor Current Source
 The two-transistor current source is also called a current mirror, which consists of two
matched (or identical) transistors, Q1 and Q2, operating at the same temperature.
I REF  I C 1  I B 1  I B 2  I C 1  2 I B 1
I O  I C 2  I REF

2 
 I C 2  2 I B 2  I C 2  1 




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
2 
1  
 

I REF 
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V

 V BE  V

R1
2
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Output Resistance with Early Effect
 Taking the Early effect into account
IO
I REF

1
1 2/

1  V CE 2 / V A
1  V CE 1 / V A
V CE 2  V I  V BEo  V

For finite Early voltage, a change in the V I
dc bias condition in the load circuit affects
the collector-emitter voltage of Q 2.
ro
dI O

dV CE 2

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I REF
1 2/
IO
VA

1
rO

1
VA

1
1  V BE / V A
(V BE  V A )
4
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Mismatched Transistors
 In practice, transistor Q1 and Q2 may not be exactly identical.
I REF  I C 1  I S 1 e
IO  I C 2  I S 2e
V BE / V T
V BE / V T
If Q1 and Q2 are not identical, then I S 1  I S 2 .
 Relationship between the bias and reference currents
I
I O  I REF  S 2
 I S1




 I S is a strong function of temperature. Thus Q1 and Q2 must be close to one
another on the semiconductor for the similar operation situation (including temperature).
 By using different sizes of transistors, we can design the circuit such that
I O  I REF .
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Basic Three Transistor Current Source
Assume that all transistor are identical.
I REF  I C 1  I B 3
IB3 
IE3
1  3

2IB2
1  3

2 IO
 2 (1   3 )
IC1  IC 2  IO


2

 I C 2 1 

 2 (1   3 )

(
1


)
2
3 

2 IC 2
I REF  I C 2


2
1




(
1


)
2
3


I O  I REF
I REF 
V

V
ro 2

 V BE 3  V BE  V
R1

 2V BE  V
R1
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

• The approximation of I O  I REF is better.
• The change in load current with a change in  is much
smaller.
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Cascode Current Source
 Current-source circuits can be designed such that the output resistance is much greater
than that of the two-transistor circuit.
 For a constant reference current, the base voltages of Q2 and Q4 are constant, which
implies these terminals are at signal ground.
V be 4   I x ( ro 2 // r 4 )
Assume that all transistor are identical.
 V  I x ( ro 2 // r 4 ) 

I x  g m 4V be 4   x

ro 4


 V x  I x ( ro 2 // r 4 ) 

  g m 4 I x ( ro 2 // r 4 )  

r
o4


Ro 
Vx
Ix
 ro 4 (1   )  r 4
  ro4
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Resistance Analysis of the Cascode Current Source
ib
ib
io 4
g m 4V be 4  g m 4 ( ro 2 // r 4 ) ib
io 4  [1  g m 4 ( ro 2 // r 4 )] ib
R o  ( ro 2 // r 4 )  ro 4 [1  g m 4 ( ro 2 // r 4 )]
 r 4  ro 4 (1  g m 4 r 4 )
 r 4  ro 4 (1   )
  ro 4
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Wilson Current Source
I REF  I C 1  I B 3  I C 2  I B 3
IE3
IC 2
Assume that all transistor are identical.

2 
 I C 2  2 I B 2  I C 2  1  
 

1 

2 
1
 I E 3 1   

IC 3
  1 2/


ro 3 / 2
1 

IC 3
2
I REF 
1 
2
IC 3 
IC 3

1
I O  I REF 
1
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2
 (2   )
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Widlar Current Source
I REF  I C 1  I S e
IO  IC 2  I S e
V BE 1 / V T
V BE
2
(   1)
Assume that all transistor are identical.
/ VT
I
V BE 1  V T ln  REF
 IS




I 
V BE 2  V T ln  O 
 IS 
I
V BE 1  V BE 2  V T ln  REF
 IO




 I E 2 RE  IO RE
 I REF
I O R E  V T ln 
 IO
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



V BE 1  V BE 2  I O  I REF
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Output Resistance
R o 1  r 1 //
1
g m1
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// ro 1 // R1
(For typical parameters, it is small.)
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Output Resistance
V 2   I x ( R E // r 2 )
V x  I x ro 2  g m 2 ro 2V 2  I x ( R E // r 2 )
Vx
Ix
 R o  ro 2 1  ( R E // r 2 )( g m 2  1 / ro 2 ) 
 ro 2 [1  g m 2 ( R E // r 2 )]
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Multitransistor Current Mirrors
I O 1  I O 2  ...  I ON 
I REF
1 N
1

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Multioutput Transistor Current Source
I 1  I 2  I 3  I REF
I O  3 I REF
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Generalized Current Mirrors
Assume that all transistor are identical and
the base current effects are neglected.
I REF 
V

 V EB ( Q R 1 )  V BE ( Q R 2 )  V

R1
I O 1  I REF
I O 2  2 I REF
I O 3  I REF
I O 4  3 I REF
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Two Transistor MOSFET Current Source
I REF  K n 1 (V GS  V TN 1 )
V GS  V TN 1 
I REF
K n1
I O  K n 2 (V GS  V TN 2 )

 K n2 

2
I REF
K n1
2

 V TN 1  V TN 2 

2
If M1 and M2 are identical
transistors, then I O  I REF .
The output current can be
controlled by aspect ratios,
IO 
K n2
K n1
 I REF 
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(W / L ) 2
(W / L ) 1
 I REF
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Output Resistance
 Taking into account the finite output resistance of transistors,
I REF  K n 1 (V GS  V TN 1 ) (1  1V DS 1 )
2
I O  K n 2 (V GS  V TN 2 ) (1   2V DS 2 )
2
Assume that all physical parameters are identical for both devices.
IO

I REF
(W / L ) 2 (1   V DS 2 )

(W / L ) 1 (1   V DS 1 )
Let (W / L ) 2  (W / L ) 1 .
1
RO

dI O
dV DS 2
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  I REF 
1
ro
ro
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Reference Current
 The M3 transistor is used as a resistor.
K n 1 (V GS 1  V TN 1 )  K n 3 (V GS 3  V TN 3 )
2

 V GS 3   1 

(W / L ) 1

(W / L ) 3
V GS 1 
V

 V GS 1  V GS 3  V
V GS 1 
k
1 k
 (V


2
(W / L ) 3 
  V TN
(W / L ) 1 

V ) 
1 k
1 k
 V TN
 V GS 2
k 
(W / L ) 3
(W / L ) 1
W   1

2
IO  
   n C ox  (V GS 2  V TN )
 L 2  2

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Cascode Current Mirror
 The output resistance is designed to be much greater
than that of the two-transistor circuit.
I x  g mV gs 4 
V x  ( V gs 4 )
ro 4
V gs 4   I x ro 2
Ix 
ro 2
Ro 
Vx
ro 4
Ix
I x  g m ro 2 I x 
Vx
ro 4
 ro 4  ro 2 (1  g m ro 4 )
 ro 4  g m ro 2 ro 4
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Wilson Current Mirror
 For modified MOSFET Wilson current source circuit, the drain-to-source voltages of M1,
M2, and M4 are held constant.
 The primary advantage of these circuits is the increase in output resistance, which
further stabilizes the load current.
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Bias-Independent Current Source
 PMOS devices are matched, the
current I D 1 and I D 2 are equal.
I D1 
k n  W 
2

 (V GS 1  V TN )
2  L 1
 ID2
(W / L ) 1
(W / L ) 2
k n  W 
2


 (V GS 2  V TN )
2  L 2
Always
Saturation
 (V GS 1  V TN )  V GS 2  V TN
V GS 2  V GS 1  I D 2 R  V GS 1  I D 1 R
 I D 1  K n 1 (V GS 1  V TN )
 V GS 1  V TN 
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2
I D1
K n1
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Bias-Independent Current Source
(W / L ) 1
(W / L ) 2
 (V GS 1  V TN )  V GS 2  V TN
(W / L ) 1

(W / L ) 2
I D1
K n1
 V GS 1  V TN  I D 1 R

I D1
K n1
R 
1
K n1 I D 1

1 


 I D1R
(W / L ) 1 

(W / L ) 2 
(For a given current I D 1 , one
can find the value of R.)
The currents I D 1 and I D 2 are independent of the supplied voltages as
long as M2 and M3 are biased in the saturation region.
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JFET Current Sources
 The device remains biased in the saturation region.
v DS  v DS ( sat )  v GS  V P  | V P |
(V P is negative)
In the saturation region, the current is

v
i D  I DSS  1  GS
VP

1
ro

di D
dv DS
2

 (1   v DS )  I DSS (1   v DS )

  I DSS
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Cascode JFET Current Source
 Increase the output resistance of a JFET current source
Assuming Q1 and Q2 are identical,
2

v
i D  I DSS (1   v DS 1 )  I DSS  1  GS 2
VP

v GS 2   v DS 1 , v DS 2  V DS  v DS 1

 (1   v DS 2 )

For a given V DS , v DS 1 (and then i D ) can be determined by

v
(1   v DS 1 )   1  DS 1
VP

2

 [1   (V DS  v DS 1 )]

 Output Resistance
I x  g mV gs 2  [V x  ( V gs 2 )] / ro 2
 g m (  I x ro 1 )  [V x  ( V gs 2 )] / ro 2
Ro 
Vx
Ix
 ro 2  ro 1  g m ro 1 ro 2
 ro 2  ro 1 (1  g m ro 2 )
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DC Analysis of BJT Active Load Circuits
 Q2 is referred to as the active load device for driver transistor Q0.
I C 0  I S 0 [e
V I / VT
I C 2  I S 2 [e
V EB
2

V
] 1  CE 0
V AN

/ VT





V
] 1  EC 2
V AP

I REF  I C 1  I S 1 [ e
V EB 1 / V T




V
] 1  EC 1
V AP




Assuming Q1 and Q2 are identical,
I S 1  I S 2 and V EC 1  V EB 1  V EB 2 .
V O  V CE 0 
V AN V AP
V AN  V AP
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V /V

I S 0e I T 
V AN
1


(V


I REF  V AN  V AP

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
 V EB 2 )
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Voltage Gain of BJT Active Load Circuits
 Voltage Transfer Function and Load Curve
V CE 0 ( sat )  V O  V

 V EC 2 ( sat )
 Voltage Gain
Av 
dV O
dV I
 V AN V AP
  
 V AN  V AP
I REF  I S 0 e
Av 
dV O
dV I
 I S 0
 
 I
  REF
 1
 
  VT
 V I / VT
 e

V I / VT
 V AN V AP
  
 V AN  V AP
 1
 
 V
 T



 (1 / V T )

1
1

V AN
V AP
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DC Analysis of MOSFET Active Load Circuit
I REF  K p 1 (V SG  | V TP 1 |) (1   1V SD 1 )
2
I 2  K p 2 (V SG  | V TP 2 |) (1   2V SD 2 )
2
Assuming M1 and M2 are identical,
1   2   p , V TP 1  V TP 2  V TP , and K p 1  K p 2  K p .
V SD 1  V SG , V O  V
I REF

I2

VO 

(1   pV SD 1 )
(1   pV SD 2 )
 V SD 2

(1   pV SG )
(1   p (V

 V O ))
I REF
K n (V I  V TN ) (1   nV O )
2
[1   p (V

 V SG )]
n   p
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
K n (V I  V TN )
2
I REF (  n   p )
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Voltage Gain of MOSFET Active Load Circuits
 Voltage Transfer Function and Load Curve
 Voltage Gain
Av 
dV O

 2 K n (V I  V TN )
dV I
I REF (  n   p )
g m  2 K n (V I  V TN )
ron  1 /  n I REF
Av 
 gm
 1
1 



r

r
on
op


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rop  1 /  p I REF
  g m ( ron // rop )
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Small-Signal Analysis of BJT Active Load Circuit
 In the Q1 portion of the equivalent circuit, there are no
independent AC sources to excite any current or
voltages.
V 1  V 2  0
Ro  ro 2
Ro  ro 2
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Small-Signal Voltage Gain
Av 

Vo
Vi
  g m ( ro // R L // ro 2 )
 gm
 1
1
1 
 


RL
ro 2 
 ro
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
g m  I Co / V T
 gm
g0  g L  go2
g o  I Co / V AN
g o 2  I Co / V AP
g L  1 / RL
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Small-Signal Analysis of MOSFET Active Load circuit
 There is no AC excitation, the signal voltage V sg 1 and V sg 2
are zero.
Ro  ro 2
Ro  ro 2
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Small-Signal Voltage Gain
Av 

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Vo
Vi
  g m ( ro // R L // ro 2 )
 gm
g0  g L  go2
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Advanced MOSFET Active Load
g mV gs 1 
Vo
Ro 3

 V gs 2
ro 1
 g mV gs 2 
V o  ( V gs 2 )
ro 2
V o  ( V gs 2 )
ro 2
Av 
 g mV gs 2  0
Vo
Vi
 gm
 gm
2

gm
Ro 3

2
1
ro 1 ro 2

1
ro 3 ro 4

1
ro 1 ro 2
R o 3  ro 3  ro 4 (1  g m ro 3 )
(See Cascode Current
Mirror, p.24)
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