Transcript lecture5_FSM - George Mason University ECE Home Page

ECE 545
Lecture 5
Finite State Machines
ECE 545 – Introduction to VHDL
George Mason University
Arrays
ECE 545 – Introduction to VHDL
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Arrays of std_logic_vectors
32
L(0)
REP_BLOCK
32
1
L(1)
REP_BLOCK
32
2
L(2)
3
REP_BLOCK
32 L(3)
...
..........
32 L(M-1)
M
REP_BLOCK
32
ECE 545 – Introduction to VHDL
L(M)
3
Arrays of std_logic_vectors
TYPE sig_array IS ARRAY(0 TO M) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
…
SIGNAL L: sig_array;
…
BEGIN
L(0) <= A;
CASCADE: for I in 1 to M generate
C: REP_BLOCK
port map(REP_IN => L(I-1),
REP_OUT=>L(I));
END GENERATE;
Z <= L(M);
END Structural;
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Finite State Machine Resources
• Volnei A. Pedroni, Circuit Design with VHDL
Chapter 8, State Machines
• Sundar Rajan, Essential VHDL: RTL Synthesis
Done Right
Chapter 6, Finite State Machines
Chapter 10, Getting the Most from Your State
Machine
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Structure of a Typical Digital System
Data Inputs
Execution
Unit
(Datapath)
Data Outputs
ECE 545 – Introduction to VHDL
Control Inputs
Control
Signals
Control
Unit
(Control)
Control Outputs
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Execution Unit (Datapath)
• Provides All Necessary Resources and
Interconnects Among Them to Perform
Specified Task
• Examples of Resources
• Adders, Multipliers, Registers, Memories, etc.
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Control Unit (Control)
• Controls Data Movements in an
Operational Circuit by Switching
Multiplexers and Enabling or Disabling
Resources
• Follows Some ‘Program’ or Schedule
• Often Implemented as Finite State Machine
or collection of Finite State Machines
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Finite State Machines
Refresher
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Finite State Machines (FSMs)
• Any Circuit with Memory Is a Finite State
Machine
• Even computers can be viewed as huge FSMs
• Design of FSMs Involves
• Defining states
• Defining transitions between states
• Optimization / minimization
• Above Approach Is Practical for Small
FSMs Only
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Moore FSM
• Output Is a Function of a Present State Only
Inputs
Next State
function
Next State
clock
reset
Present State
Register
Output
function
ECE 545 – Introduction to VHDL
Present State
Outputs
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Mealy FSM
• Output Is a Function of a Present State and
Inputs
Inputs
Next State
function
Next State
clock
reset
Present State
Register
Output
function
ECE 545 – Introduction to VHDL
Present State
Outputs
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Moore Machine
transition
condition 1
state 1 /
output 1
ECE 545 – Introduction to VHDL
state 2 /
output 2
transition
condition 2
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Mealy Machine
transition condition 1 /
output 1
state 2
state 1
transition condition 2 /
output 2
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Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs Can Be
Functionally Equivalent
• Equivalent Mealy FSM can be derived from
Moore FSM and vice versa
• Mealy FSM Has Richer Description and
Usually Requires Smaller Number of States
• Smaller circuit area
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Moore vs. Mealy FSM (2)
• Mealy FSM Computes Outputs as soon as
Inputs Change
• Mealy FSM responds one clock cycle sooner
than equivalent Moore FSM
• Moore FSM Has No Combinational Path
Between Inputs and Outputs
• Moore FSM is more likely to have a shorter
critical path
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Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
0
1
S0 / 0
1
reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
ECE 545 – Introduction to VHDL
0
S1 / 0
0
S1: “1”
observed
1
S2 / 1
S2: “10”
observed
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Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
0/0
1/0
S0
reset
Meaning
of states:
1/0
S1
0/1
S0: No
elements
of the
sequence
observed
ECE 545 – Introduction to VHDL
S1: “1”
observed
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Moore & Mealy FSMs – Example 1
clock
0
1
0
0
0
S0
S1
S2
S0
S0
S0
S1
S0
S0
S0
input
Moore
Mealy
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Finite State Machines
in VHDL
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FSMs in VHDL
• Finite State Machines Can Be Easily
Described With Processes
• Synthesis Tools Understand FSM
Description If Certain Rules Are Followed
• State transitions should be described in a
process sensitive to clock and asynchronous
reset signals only
• Outputs described as concurrent statements
outside the process
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Moore FSM
process(clock, reset)
Inputs
Next State
function
Next State
clock
reset
concurrent
statements
ECE 545 – Introduction to VHDL
Present State
Register
Present State
Output
function
Outputs
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Mealy FSM
process(clock, reset)
Inputs
Next State
function
Next State
clock
reset
concurrent
statements
ECE 545 – Introduction to VHDL
Present State
Present State
Register
Output
function
Outputs
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Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
0
1
S0 / 0
reset
ECE 545 – Introduction to VHDL
1
0
S1 / 0
1
S2 / 1
0
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Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Moore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Moore_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Moore_state <= S1;
ELSE
Moore_state <= S0;
END IF;
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Moore FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Moore_state <= S2;
ELSE
Moore_state <= S1;
END IF;
WHEN S2 =>
IF input = ‘0’ THEN
Moore_state <= S0;
ELSE
Moore_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
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Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
0/0
1/0
S0
reset
ECE 545 – Introduction to VHDL
1/0
S1
0/1
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Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);
SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
Mealy_state <= S0;
END IF;
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Mealy FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
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Moore FSM – Example 2: State diagram
resetn
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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Moore FSM – Example 2: State table
Next state
Present
state w = 0 w = 1
A
B
C
ECE 545 – Introduction to VHDL
A
A
A
B
C
C
Output
z
0
0
1
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Moore FSM
process(clock, reset)
Input: w
Next State
function
Next State
clock
resetn
concurrent
statements
ECE 545 – Introduction to VHDL
Present State
Register
Present State: y
Output
function
Output: z
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Moore FSM – Example 2: VHDL code (1)
USE ieee.std_logic_1164.all ;
ENTITY simple IS
PORT ( clock
resetn
w
z
END simple ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
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Moore FSM – Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
WHEN C =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
END CASE ;
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Moore FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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Moore FSM
process
Input: w
(w,
y_present)
process
(clock,
resetn)
Next State
function
Next State: y_next
clock
resetn
concurrent
statements
ECE 545 – Introduction to VHDL
Present State
Register
Output
function
Present State:
y_present
Output: z
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Alternative VHDL code (1)
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y_present, y_next : State_type ;
BEGIN
PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
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Alternative VHDL code (2)
WHEN C =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
END CASE ;
END PROCESS ;
PROCESS (clock, resetn)
BEGIN
IF resetn = '0' THEN
y_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
y_present <= y_next ;
END IF ;
END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ;
END Behavior ;
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Mealy FSM – Example 2: State diagram
resetn
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
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Mealy FSM – Example 2: State table
Next state
Output z
Present
state
w= 0
w= 1
w= 0
w= 1
A
B
A
A
B
B
0
0
0
1
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Mealy FSM
process(clock, reset)
Input: w
Next State
function
Next State
clock
resetn
concurrent
statements
ECE 545 – Introduction to VHDL
Present State: y
Present State
Register
Output
function
Output: z
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Mealy FSM – Example 2: VHDL code (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Mealy IS
PORT ( clock : IN
resetn : IN
w
: IN
z
: OUT
END Mealy ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF Mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
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Mealy FSM – Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
END CASE ;
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Mealy FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
WITH y SELECT
z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
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State Encoding
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State Encoding Problem
• State Encoding Can Have a Big Influence
on Optimality of the FSM Implementation
• No methods other than checking all possible
encodings are known to produce optimal circuit
• Feasible for small circuits only
• Using Enumerated Types for States in
VHDL Leaves Encoding Problem for
Synthesis Tool
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Types of State Encodings (1)
• Binary (Sequential) – States Encoded as
Consecutive Binary Numbers
• Small number of used flip-flops
• Potentially complex transition functions leading
to slow implementations
• One-Hot – Only One Bit Is Active
• Number of used flip-flops as big as number of
states
• Simple and fast transition functions
• Preferable coding technique in FPGAs
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Types of State Encodings (2)
State
Binary Code
One-Hot Code
S0
S1
S2
000
001
010
10000000
01000000
00100000
S3
S4
S5
S6
011
100
101
110
00010000
00001000
00000100
00000010
S7
111
00000001
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A user-defined attribute for manual
state assignment
(ENTITY declaration not shown)
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
ATTRIBUTE ENUM_ENCODING
ATTRIBUTE ENUM_ENCODING OF State_type
SIGNAL y_present, y_next : State_type ;
BEGIN
: STRING ;
: TYPE IS "00 01 11" ;
con’t ...
Figure 8.34
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Using constants for manual state assignment (1)
ARCHITECTURE Behavior OF simple IS
SUBTYPE ABC_STATE is STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT A : ABC_STATE := "00" ;
CONSTANT B : ABC_STATE := "01" ;
CONSTANT C : ABC_STATE := "11" ;
SIGNAL y_present, y_next : ABC_STATE;
BEGIN
PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN y_next <= A ;
ELSE y_next <= B ;
END IF ;
… con’t
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