Transcript Full Serial Integrated Scan

TOPIC : Scan based Design
Module 4.3 : Scan architectures and testing
UNIT 4 : Design for Testability
Introduction
There are several forms of scan designs;
they differ primarily in how the scan cells
are designed.
 We will illustrate three generic forms of
scan design :
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◦ Full Serial Integrated Scan
◦ Isolated Serial Scan
◦ Non-serial Scan
Normal sequential circuit
Full serial integrated scan circuit
Full Serial Integrated Scan Architecture
Full Serial Integrated Scan
The normal parallel-load register R has
been replaced by a scan register Rs.
 When N_bar/T = 0 (normal mode), Rs
operates in the parallel-latch mode; hence
both circuits operate the same way.
 Now Y becomes easily controllable and E
easily observable. Hence test generation
cost can be drastically reduced.

Isolated Serial Scan
In this, scan register is in the normal data
path.
 This scan architecture, the selection of
the CPs and Ops associated with the scan
register Rs is left up to the desigener.

Full isolated scan
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If Rs is used both to
observe and control all
the storage cells in S.
A test vector yl is
scanned (shifted) into Rs,
loaded into R', and then
applied to the circuit C.
The response e can be
loaded into R',
transferred to Rs, and
then scanned out.
The register Rs is said to
act as a shadow
register to R'.
Non serial Scan
It aim to give full controllability and
observability to all storage cells in a circuit.
 Storage cells are arranged in a randomaccess bit – addressable memory.
 During normal operation the storage cells
operate in their parallel-load mode.
 Scan in – appropriate cell is addressed, the
data are applied to Sin. The output of the
cells are wired-OR together.
 Advantage – Only bits in R that need to
changes must be addressed and modified;
this saves scanning data through entire
register.
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Non serial Scan Example
Random-access scan