Transcript Memory Decoding 20060028

Memory Address Decoding
 Design a 1MB memory system consisting of multiple memory chips
— Solution 1:
256KB
256KB
256KB
256KB
M1
M2
M3
M4
CS
A0 – A7
A18
A19
IO/M
2-to-4
decoder
CS
CS
CS
CS
Memory Address Decoding
A19 A18
1 1
A19 A18
1 0
A19 A18
0 1
A19 A18
0 0
FFFFF
C0000
BFFFF
80000
7FFFF
40000
3FFFF
00000
M4
M3
M2
M1
Memory Address Decoding
 Design a 1MB memory system consisting of multiple memory chips
— Solution 2:
256KB
256KB
256KB
256KB
M1
M2
M3
M4
CS
A2 – A19
A1
2-to-4
decoder
A0
CS
IO/M
CS
CS
CS
Memory Address Decoding
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1110
1101
1100
M4
M3
M2
M1
A 1A0
Pipelining
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0011
0010
0001
0000
M4
M3
M2
M1