Transcript A Temperature Sensor in 0.18 µm CMOS with 62µW Power

A Temperature Sensor
in 0.18µm CMOS
with 62µW Power Consumption
and a Range of -120..120°C
Jan-Rutger Schrader
Anne Stellinga
Kofi Makinwa
Contents
1.
2.
The Mars Seismometer Project
Temperature Sensor
1. Architecture
2. Detailed Implementation
3. Measurement Results
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3
Seismometer
CAD view of
broadband
seismometer
Test
configuration
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SHAMROC Readout Chip
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SHAMROC Readout Chip
5x5mm
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Why a Temperature Sensor?
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Problem
Temperature on Mars <-100°C at night, >0°C day
Electronics (self-heating): -55°C … 85°C
Required 24-bit SHAMROC ADC accuracy is 3ppm/°C
Solution
On-chip temperature sensor measures die temperature
ADC output values corrected using a (2nd order)
polynome
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Specifications
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Temperature range:
Resolution:
Non-linearity:
Conversion time:
Power:
Supply voltage:
-120°C … 120°C
0.06°C
±0.25°C
33ms
62μW
3.3V analog, 1.8V digital
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Temperature Measurement Circuit: “Bipolar Core”
I
p·I
+
Vbe
Vbe 
kT
ln(p)
q
-
E
E
(p=current ratio)
B
B
C
C
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Block Schematic of Complete Temperature Sensor
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Front-end and Timing
8Cs
8Cs
Correlated Double Sampling
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Opamp
30uA
60uA
60uA
Vb1
Vin+
Vin-
Vb2
Vb2
Vb3
Vb3
Vout+
Vout-
Vcmfb
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Test Chip
UMC 0.18μm RF CMOS
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Chip Micrograph
Active area: 0.29 mm²
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Measured Error versus Reference Temperature
Non-linearity ±0.25°C
3σ spread around ±0.3°C level
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Measured Power Consumption
Power
[µW]
Analog
Digital
IO
Total
Always Always Average
on
off
(33ms
conversion)
806
2
28
30
26
26
67
5
8
902
33
62
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DARE vs Faraday digital library
2 tape-outs, same VHDL
Power
[µW]
Always
on
Always
off
Digital,
DARE
Digital,
Faraday
317
273
Average
(33ms
conversion)
274
30
26
26
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Radiation Hardening
Enclosed gate layout (leakage)
IMEC DARE library
Guard rings (latchup)
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Radiation Tests
• 16krad
No parameter shifts (SHAMROC TID-requirements)
• 44krad
• 136krad
Output drift 0.75%
Output drift 6%
• 409krad
Chips stopped functioning
Power unchanged
Analog power in ONstate increased
Large increase in analog
& digital power
• No influence observed on IO-power.
• DARE digital library: SEU-resistant logic.
Preliminary SEU test:
only 1 possible single-event transient in multi-day test.
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End
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