Transcript Lecture 4 - Rabieramadan.org

Microprocessor
Dr. Rabie A. Ramadan
Al-Azhar University
Lecture 4
Machine Cycles and Bus Timings

Microprocessor includes 158 different
instruction types.
• Each instruction has two parts:
• Operation code (known as opcode) and operand.
OUT
(10H), A
Operand to specify that the
byte should be sent from the
accumulator to port 10H
Opcode to
output data
2
Machine Cycles and Bus Timings
OUT
(10H), A
Operand to specify that the
byte should be sent from the
accumulator to port 10H
Opcode to
output data

Assume that the instruction is stored in 2 Bytes

The Z80 has to perform three operations:
• Read Byte 1 from the first memory location
• Read Byte 2 from the next memory location
• Send Data to port 10H
3
Machine Cycles and Bus Timings

Instruction
• the time required to complete the execution of an instruction. The Z80
instruction cycle consists of one to six machine cycles or one to six
operations.

Machine Cycle
• The time required to complete one operation of accessing memory,
accessing I/O, or acknowledging an external request. This cycle may
consist of three to six T-states.

T-state
• One subdivision of operation performed in one clock period. These
subdivisions are internal states synchronized with the system clock and
each T-state is equal to one clock period.

4
Opcode Fetch Machine Cycle (M1)
Address
2002
Machine Code
010001112  (47H)
Instruction
LD B, A
Comment
Copy A into B
5
Opcode Fetch Machine Cycle (M1)
6
Opcode Fetch Machine Cycle (M1)
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The Timing of the opcode Fetch Machine
8
The Timing of the
opcode Fetch Machine
9
The Timing of the
opcode Fetch
Machine
10
The Timing of the
opcode Fetch
Machine
11
Memory Read Machine Cycle

The instruction consists of two bytes;
• Opcode and Data byte.
• The Z80 must first read these bytes from memory
• Requires at least two machine cycles.
• The machine cycle is opcode fetch, and
• the second machine cycle is Memory Read
12
13
14
15
Memory Write Cycle

This is a one-byte instruction with two machine cycles:
• Opcode Fetch and Memory Write.
• Z80 fetches the code (77H) and
• it copies the byte 9FH from the accumulator into the memory
location 2350H.
16
17
18
19
Memory Interfacing
20
Interfacing Memory



An address should be placed on the
address lines.
The low-order address lines are
decoded by the internal decoder of the
memory chip, and the addressed
register is identified.
The high-order address should be
decoded to generate a Chip Select
signal, and the memory chip is
selected by asserting the Chip Select CS
low.
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Interfacing Memory

To read from the addressed register, the RD
should be asserted low to enable the
output buffer, and then the data byte
from the register will be placed on the
I/O lines.

To write into the addressed register, the WR
should be asserted low to enable the
input buffer, and then data bits from the
data lines are stored into the register.
22
How does the Z80 Read from or
Write into Memory?
23
Basic Concepts in Memory
Interfacing

Interface Function:
• Be able to select the chip
• Identify the register
• Enable the appropriate buffer.
24
Read from the Memory
25
Write into memory register
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Address Decoding



3 input lines A0-A2 (Memory Select Buffer (MSB))
A3 – A7 are control lines since the address starts at F0H to F7H
3 lines enable only one o/p line
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
0
1
1
1
= F7H
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Example 1: Interfacing the 2764
EPROM



Used in industry to develop
microprocessor-based products.
8k (8192  8) memory chip with
8 data lines
Housed in a 28-pin package.
28
Chip Configuration
29

What is the Memory Addresses Range?
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0000H  1FFFH
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Interfacing CMOS 6116 Static R/W
Memory





This is a 2k static memory chip
organized as 2048 x 8 format.
It has 11 address lines (A10-A0),
8 data lines
3 control signals:
31
Chip Configuration
32
Memory Interface

What is the addresses range? Assume A12 and A11 are do not care .
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
1
0
0
X
X
1
1
1
1
1
1
1
1
1
1
1
8000  87FF -- Address ranges may differ due to the do not care at A12
33 and A11
Reading Assignment

Please Read
•
•
Chapter 3
Chapter 4
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