Transcript Lab3

Programmable Logic
System Design
Lab03- Simulation Preliminary
SOC LAB.
Chang-Ting Chen
2013.10
Lab Description
 認識實驗版 Spartan-3 Starter Kit Board
 撰寫 VHDL，利用 Switch 模組控制 LED 模組
 定義I/O腳位(I/O Pins)，產生燒錄檔(*.bit)，
燒錄並觀察在 FPGA 板子上的結果
Spartan-3 Starter Kit Board
Create Xilinx Project
 若忘記 Xilinx 開新 Project 的設定請參考 Lab1 的講義
 Device Family 選 Spartan3 系列
 Device 型號詳見盒上便條紙 (xc3s200/xc3s400)
 Package 選 ft256
 其它用 Xilinx 預設即可
Use Switches to Light LEDs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo is
Port (
swt : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0));
end demo;
architecture Behavioral of demo is
begin
led(7 downto 0) <= swt(7 downto 0);
end Behavioral;
Pin Assignment
 Add the Implementation Constraints File
Pin Assignment (Cont’d)
腳位在FPGA板上都有寫
只需要填寫 Loc 欄即可
Pin Assignment (Cont’d)

Properties of Generate Programming File 右鍵→Properties
Pin Assignment (Cont’d)
 Check Create Bit File (若已勾選則不用動)
 FPGA Start-Up Clock => JTAG Clock
Programming Process
Programming Process (Cont’d)
 Select Boundary-Scan Mode (預設)
 Select Automatically connect and identify (預設)
Detecting Boundary-scan Chain
Assign Configuration File to FPGA
Bypass Platform Flash PROM
Program Process
在左邊的圖示上按右鍵→Program
Programming succeeded

取消 Verify 選項 → 按 OK 進行燒錄 → 成功後出現以下畫面
Assignment
 以VHDL 撰寫描述此一真值表並完成波形模擬圖、腳位
設定以及Download。並輸入訊號觀察與模擬設計是否相
符。