CEN 226

: Computer Organization & Assembly Language :

CSC 225

(Lec#3)

By Dr. Syed Noman

Basic Programming Model- 8086 CPU Internal Organization

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Registers

• • • • • • • The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer.

Eight of the registers are known as general purpose registers i.e. they can be used by the programmer for data manipulation.

Each of the registers is 16 bits long i.e. can contain a 16-bit binary number.

The first four registers are sometimes referred to as data registers. They are the ax, bx, cx and dx registers.

The second four are referred to as index/pointer registers. They are the sp, bp, si and di registers.

The data registers can be treated as 16-bit registers or they can each be treated as two 8-bit registers. Each 8-bit register can be used independently.

The ax register may be accessed as ah and al (H and L refer to high-order

and low-order bytes).

▫

Similarly



bx may be accessed as bh, bl

 

cx may be accessed as ch, cl dx may be accessed as dh, dl

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General-Purpose Registers

• • • • • • • • • 8086 CPU has 8 general purpose registers; each register has its own name:

AX - the accumulator register (divided into AH / AL).

BX - the base address register (divided into BH / BL).

CX - the count register (divided into CH / CL).

DX - the data register (divided into DH / DL).

SI - source index register.

DI - destination index register.

BP - base pointer.

SP - stack pointer

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8086 CPU Broad Division

• • • 8086C CPU can be broadly divided into two separated groups: 1. Execution Unit (EU): The Execution Unit executes all instructions. An execution unit is a part of a CPU that performs the operations and calculations called for by the program. Execution Unit (EU) contains Arithmetic Logic Unit, which is a core component of all CPUs. ALUs are capable of calculating the results of a wide variety of basic arithmetical computations. 2. Bus Interface Unit (BIU): It is the part of the processor that interfaces with the rest of the PC. The BIU provides various functions, including generation of the memory and I/O addresses for the transfer of data between outside the CPU, and the EU.

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8086 CPU Broad Division

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8086 CPU Internal Architecture

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Model Description

• • • • The EU receives program instruction codes and data from the BIU, executes these instructions, and store the results in the general registers. By passing the data back to the BIU, data can also be stored in a memory location or written to an output device. Note that the EU has no connection to the system buses. It receives and outputs all its data through the BIU.

BIU Elements: Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction. The memory interface is slower than the processor execution time so this speeds up overall performance

Segment Registers:

▫ CS, DS, SS and ES are 16b registers.

▫ Used with the 16b Base registers to generate the 20b address.

▫ ▫ Allow the 8086/8088 to address 1MB of memory.

Changed under program control to point to different segments as a program executes.

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Model Description

• • • Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register.

CPU will perform the operations into the execution unit, next, it decodes and interprets instruction to perform calculations, and then send to Arithmetic Logic Unit (ALU) that is capable of calculating the results of a wide variety of basic arithmetical computations. When it is finished, ALU will be connected to a set of inputs and a set of outputs through Bus Interface that is the part of the processor that interfaces with the rest of the PC.

The fundamental operation of CPU will operate in memory unit all the times. Moreover, CPU also executes instructions to read data from input devices and then writes back to output devices 9

Intel 8086/8088 Microprocessor

• • • • • 8086 is a 16-bit processor – because the size of the “accumulator” register, AX, is 16 bits. Has 20 address pins (16 multiplexed with data) – because address and data cannot be travelled at the same time. When address is generated it is latched and then after control bus, data is travelled.

Can address a max. of 2^20 = 1,048,576 = 1 Million locations Address ranges from 00000H to FFFFFH Memory is byte addressable - Every byte has a separate address. 10

Segment and Segment Registers

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Segment Registers

• • • • • • •

Segment Registers CS - points at the segment containing the current program.

DS - generally points at segment where variables are defined.

ES - extra segment register, it's up to a coder to define its usage.

SS - points at the segment containing the stack.

Although it is possible to store any data in the segment registers, this is never a good idea. The segment registers have a very special purpose - pointing at accessible blocks of memory.

Segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345h (hexadecimal), we should set the DS = 1230h and SI = 0045h. This is good, since this way we can access much more memory than with a single register that is limited to 16 bit values.

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Address Calculation

• • • • CPU makes a calculation of physical address by multiplying the segment register by 10h and adding general purpose register to it (1230h * 10h + 45h = 12345h): The address formed with 2 registers is called an effective address. By

default

BX, SI and DI registers work with DS segment register;

BP and SP work with SS segment register.

Other general purpose registers cannot form an effective address! Also, although BX can form an effective address, BH and BL

cannot.

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8086 Address Calculation

• The logical address A4FB:4872h means offset 4872h within segment A4FBh, that is, the segment starting at physical address A4FB0h. To obtain the corresponding 20 bit physical (i.e., absolute) address, the 8086/8088 microprocessor first shifts the segment base address 4 bits to the left (this is equivalent to multiplying by 10H), and then adds the offset. Thus the physical address for A4FB:4872h is: 14

8086 Address Calculation

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8086 Address Calculation

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