Transcript 數位系統設計概論

第3章
VHDL Concurrent語法
義守大學電機工程學系
陳慶瀚
[email protected]
1. VHDL Operators
1.1 Comparison Operator
= : 等於
> : 大於
< : 小於
/= : 不等於
比較運算子的運算結果有兩種狀態：“TRUE”和“FALSE”
1.2 Logic Declaration
AND
OR
NOT
NOR
NAND
XOR
XNOR
邏輯運算子可以應用在三種資料型態：BIT, BOOLEAN 和STD_LOGIC
1.3 Arithmetic Operator
所有Synthetizer都支援
“+” : 加法
“-” : 減法
有些Synthetizer支援
“ * ” : 乘法
“ABS” : 求絕對值
編譯時設定數值運算時使用
“/” : 除法
“**” : 次方
“MOD” : 求模數
“REM” : 求餘數
1.4 Bitwise Operator
ROL
ROR
SLL
SRL
SLA
SRA
:
:
:
:
:
:
向左旋轉位元運算
向右旋轉位元運算
向左位移位元運算
向右位移位元運算
向左位移位元運算，空出位元補'1'
向右位移位元運算，空出位元補'1'
用法：X2 <= X1 ROL 2; -- 向左旋轉2位元
1.5 VHDL其他特殊符號
“--” : 註解
“=>” : 名稱對應
“&” : 字串串接
“ : ” : 用於名稱的模式、資料型別、或標題的宣
告
‘ U’ : 未知值
‘X’或‘-’ : 任意值
‘0’或‘L’ : 邏輯狀態0
‘1’或‘H’ :邏輯狀態1
‘Z’ : 高阻抗
2 Block
Block
• Blocks are a partition
mechanism of with
VHDL
• Each block represents
a self-contained area
of model
ARCHITECTURE cpu_block OF cpu IS
SIGNAL ibus dbus :tw32;
BEGIN
ALU :BLOCK
SIGNAL qbus :tw32;
BEGIN
--alu behavior statements
END BLOCK ALU
REG8 :BLOCK
SIGNAL zbus :tw32;
BEGIN
REG1 :BLOCK
SIGNAL qbus :tw32;
BEGIN
-- reg1 behavior statements
END BLOCK REG1
-- more REG8 statements
END BLOCK REG8
END cpu_block
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3. VHDL Assignment
3.1 Assignment Operator
－ Assignment Operator for Signal
<=
－ Assignment Operator for Variable :=
Signal assignment 也可以加上時間的延遲, 如 a <= b AFTER
10ns 表示由訊號 b 變化到造成 a 改變的延遲是10ns
3.2 Conditional Signal Assignment
Conditional Signal Assignment
• 語法 :
Signal assignment
the other value/signal
WHEN condition ELSE
[WHEN…ELSE…]
• Example :
sel <= 0 WHEN
1 WHEN
2 WHEN
3 WHEN
4;
a
a
a
a
=
=
=
=
‘0’
‘1’
‘0’
‘1’
AND
AND
AND
AND
b
b
b
b
=
=
=
=
‘0’
‘0’
‘1’
‘1’
ELSE
ELSE
ELSE
ELSE
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3.3 Selective Signal Assignment
Select Signal Assignment
• 語法 :
WITH expression SELECT
signal assignment
WHEN expression value,
the other assignment WHEN other expression value ;
• Example:
WITH sel SELECT
q <= i0 WHEN 0,
i1 WHEN 1,
i2 WHEN 2,
i4 WHEN 3,
‘X’ WHEN OTHERS;
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3.4 Driver Problem
Driver Problem
• Bad Example :
ARCHITECTURE bad
BEGIN
q <= i0 WHEN a
q <= i1 WHEN a
q <= i2 WHEN a
q <= i3 WHEN a
END bad;
OF mux IS
=‘0’
=‘0’
=‘1’
=‘1’
AND
AND
AND
AND
b
b
b
b
=
=
=
=
‘0’
‘1’
‘0’
‘1’
ELSE
ELSE
ELSE
ELSE
ARCHITECTURE better OF mux IS
BEGIN
q <= i0 WHEN a =‘0’ AND b =
i1 WHEN a =‘0’ AND b =
i2 WHEN a =‘1’ AND b =
i3 WHEN a =‘1’ AND b =
‘x’; -- unknown
END bad;
‘0’
‘1’
‘0’
‘1’
ELSE
ELSE
ELSE
ELSE
‘0’;
‘0’;
‘0’;
‘0’;
• Better Example :
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3.5 Example- 4to1Multiplexer
Example - 4-1 MUX
USE ieee.std_logic_1164.all
MUX4
ENTITY mux4 IS
PORT (i0,i1,i2,i3,a,b :IN STD_LOGIC);
q :OUT STD_LOGIC);
END mux4
I0
I1
Q
I2
I3
A
B
Mux function table
A
B
Q
0
0
I0
0
1
I1
1
0
I2
1
1
I3
ARCHOITECTUR OF mux4 IS
SIGNAL sel :INTEGER;
BEGIN
WITH sel SELECT
q <= i0 WHEN 0,
i1 WHEN 1,
i2 WHEN 2,
i4 WHEN 3,
‘X’ WHEN OTHERS;
sel <= 0 WHEN a = ‘0’ AND b = ‘0’ ELSE
1 WHEN a = ‘1’ AND b = ‘0’ ELSE
2 WHEN a = ‘0’ AND b = ‘1’ ELSE
3 WHEN a = ‘1’ AND b = ‘1’ ELSE
4;
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END;
3.6 Example- 2to4 Decoder
Example - Decoder
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
2 to 4 decoder
table
addr
word
00
1110
01
1101
10
1011
11
0111
ENTITY decoder IS
PORT( addr :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
word :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END decoder;
ARCHITECTURE df OF decoder
BEGIN
word <= "1110" WHEN addr
"1101" WHEN addr
"1011" WHEN addr
"0111" WHEN addr
"1111" ;
END df;
IS
=
=
=
=
"00"
"01"
"10"
"11"
ELSE
ELSE
ELSE
ELSE
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3.7 Exercise
請以When-Else敘述式的VHDL語法描述下面真值表的組合邏輯電路。
【註】真值表的布林邏輯 D  A BC  ABC
輸入
輸出
A
B
C
D
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
0
END