Transcript Programmable Logic

Logic and Computer Design Fundamentals
Chapter 6 – Selected
Design Topics
Part 4 – Programmable Implementation
Technologies
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.
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Overview
 Programmable Implementation
Technologies (section 6.8)
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•
•
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Why Programmable Logic?
Read-Only Memories (ROMs)
Programmable Logic Arrays (PLAs)
Programmable Array Logic (PALs)
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Why Programmable Logic?
 Small and Medium Scale Integration
• Up to 200 gates per device/IC
• Most common is 74xx series (gates, FF, Decoders …)
 Advantages
• Easy to understand functions
• Exceptional Signal Visibility
 Disadvantages
• Low logic density means big boards or small designs
• Higher power consumption
• Failure concern per function
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Why Programmable Logic?
 Large Scale Integration
• Ranging from 200 to 200,000 gates per device.
• Small memories, programmable logic devices
 Advantages
• Higher logic density means smaller boards or larger
designs.
• Many devices can be programmed and reprogrammed,
saving expense when changes are made.
 Disadvantages
• Need to learn how to use and program
• Signal visibility is reduced
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Why Programmable Logic ?
 Many programmable logic devices are fieldprogrammable, i. e., can be programmed outside of the
manufacturing environment
 Most programmable logic devices are erasable and
reprogrammable.
• Allows “updating” a device or correction of errors
• Allows reuse the device for a different design - the
ultimate in re-usability!
• Ideal for course laboratories
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Programmable Configurations
 Read Only Memory (ROM) - a fixed array of AND
gates and a programmable array of OR gates
 Programmable Array Logic (PAL) - a
programmable array of AND gates feeding a
fixed array of OR gates.
 Programmable Logic Array (PLA) - a
programmable array of AND gates feeding a
programmable array of OR gates.
PAL is a registered trademark of Lattice Semiconductor Corp. Chapter 6 - Part 4
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Gate Symbols
Figure 6-18 Conventional and Array Logic Symbols for OR Gate
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Read Only Memory
 Read Only Memories (ROM) or Programmable Read Only
Memories (PROM) are OP logic devices with a fixed AND
array and a programmable OR array.
 have:
• k input lines,
k line decoder
k-to-2
• m output lines, and
• m = 2k decoded minterms
D7
X
X
X
D6
X
X
D5
• n OR gates
X
 Usually referred as x n ROM
 Can implement n functions
with k inputs
2k
A
B
C
D4
A2 D3
D2
A1 D1
A0 D0
X
X
F3
F2
X
X
F1
F0
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Read Only Memory
 A program for a ROM or PROM is simply a multipleoutput truth table
• If a 1 entry, a connection is made to the
corresponding minterm for the corresponding
output
• If a 0, no connection is made
 There is no advantage of simplifying the function
when using ROM since we need to specify the entire
list of minterms.
 Can be viewed as a memory with the inputs as
addresses of data (output values), hence ROM or
PROM names!
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Read Only Memory Example
 Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
 The fixed "AND" array is a
X
X
X
D7
“decoder” with 3 inputs and 8
D6
X
X
D5
outputs implementing minterms.
X
D4
 The programmable "OR“
A2 D3
A
X
array uses a single line to
D2
X
X
B
A1 D1
represent all inputs to an
X
A0 D0
C
OR gate. An “X” in the
array corresponds to attaching the
minterm to the OR
 Read Example: For input (A2,A1,A0)
= 001, output is (F3,F2,F1,F0 ) = 0011.
F0
F2
F1
F3
 What are the simplified expressions for F3, F2 , F1 and F0 in terms of (A2,
A1, A0)?
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Programmable Array Logic (PAL)
 PAL is the opposite of ROM; it is PLD that has a
programmable AND array and a fixed OR array.
 Function has to be reduced into SOP before it is
programmed into the PAL
 Disadvantage
• ROM guaranteed to implement any M functions
of N inputs. PAL may have too few inputs to the
OR gates.
 Advantages
• For given internal complexity, a PAL can have
larger k (inputs) and n (outputs)
• Some PALs have outputs that can be
complemented, adding POS functions
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Figure
W = ABC + ABCD
X = A +BCD
Y = AB + CD +BD
Z = W + ACD + ABCD
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Programmable Logic Array (PLA)
 Compared to a ROM and a PAL, a PLA is the
most flexible having a programmable set of
ANDs combined with a programmable set of
ORs.
 A PLA has all of its product terms connectable
to all outputs, overcoming the problem of the
limited inputs to the PAL OR gates
 Some PLAs have outputs that can be
complemented (using XOR gates), adding POS
functions
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Programmable Array Logic (PLA)
 The PAL is the opposite of the ROM, having a
programmable set of ANDs combined with fixed ORs.
A
3-input, 3-output PLA with 4 product terms
B
C
X
X
1
X
X
X
X
X
X
C C B B AA
X
X
AB
2
X
BC
3
X
AC
4
X
X Fuse intact
Fuse blown
Used to produce POS or
complement of function
AB
X
X
0
1
F1
F2
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ROM, PAL and PLA Summary
Fixed
AND array
(decoder)
Inputs
Programmable
Connections
Programmable
OR array
Outputs
(a) Programmable read-only memory (PROM)
Inputs
Programmable
Connections
Programmable
AND array
Fixed
OR array
Outputs
(b) Programmable array logic (PAL) device
Inputs
Programmable
Connections
Programmable Programmable
AND array
Connections
Programmable
OR array
Outputs
(c) Programmable logic array (PLA) device
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