1

Basic Processor Architecture

2

Building Blocks of Processor Systems MEM ORY CONTRO L DATAPATH CPU

Processor System Architecture

3

The typical processor system consists of:

   CPU (central processing unit)    ALU (arithmetic-logic unit) Control Logic Registers, etc… Memory Input / Output interfaces

Interconnections between these units:

   Address Bus Data Bus Control Bus

Bus and CPU Bus:

A shared group of wires used for communicating signals among devices • • • address bus: the device and the location within the device that is being accessed data bus: the data value being communicated control bus: describes the action on the address and data buses

CPU:

Core of the processor, where instructions are executed • • • High-level language: a = b + c Assembly language: add r1 r2 r3 Machine language: 0001001010111010101 4

Memory and I/O Memory:

Where instructions (programs) and data are stored • • Organized in arrays of locations (addresses), each storing one byte (8 bits) in general A

read

operation to a particular location always returns the last value stored in that location 5

I/O devices:

Enable system to interact with the world • • • • Device interface (a.k.a. controller or adapter) hardware connects actual device to bus The CPU views the I/O device registers just like memory that can be accessed over the bus. However, I/O registers are connected to external wires, device control logic, etc.

Reads

may not return last value written

Writes

may have side effects

6

8085 Microprocessor Architecture

7

The 8085 Bus Structure

The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the other units using a 16-bit address bus, an 8-bit data bus and a control bus.

8

The 8085 Bus Structure Address Bus

 Consists of 16 address lines: A 0 – A 15  Operates in

unidirectional

mode: The address bits are always sent from the MPU to peripheral devices, not reverse.

  16 address lines are capable of addressing a total of 2 16 = 65,536 (64k) memory locations.

Address locations: 0000 (hex) – FFFF (hex)

9

The 8085 Bus Structure Data Bus

 Consists of 8 data lines: D 0 – D 7  Operates in

bidirectional

mode: The data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPU.

 Data range: 00 (hex) – FF (hex)

Control Bus

 Consists of various lines carrying the control signals such as read / write enable, flag bits.

10

The 8085: CPU Internal Structure The internal architecture of the 8085 CPU is capable of performing the following operations:

     Store 8-bit data (Registers, Accumulator) Perform arithmetic and logic operations (ALU) Test for conditions (IF / THEN) Sequence the execution of instructions Store temporary data in RAM during execution

The 8085: CPU Internal Structure

11 Simplified block diagram

12

The 8085: Registers

13

The 8085: CPU Internal Structure Registers

 Six general purpose 8-bit registers: B, C, D, E, H, L  They can also be combined as register pairs to perform 16-bit operations: BC, DE, HL  Registers are programmable (data load, move, etc.)

Accumulator

 Single 8-bit register that is part of the ALU !

 Used for arithmetic / logic operations – the result is always stored in the accumulator.

14

The 8085: CPU Internal Structure Flag Bits

 Indicate the result of condition tests.

  Carry, Zero, Sign, Parity, etc.

Conditional operations (IF / THEN) are executed based on the condition of these flag bits.

Program Counter (PC)

 Contains the memory address (16 bits) of the instruction that will be executed in the next step.

Stack Pointer (SP)

15

Example: Memory Read Operation

16

Example: Instruction Fetch Operation

  All instructions (program steps) are stored in memory.

To run a program, the individual instructions must be read from the memory in sequence, and executed.

 Program counter puts the 16-bit memory address of the instruction on the address bus  Control unit sends the Memory Read Enable signal to access the memory  The 8-bit instruction stored in memory is placed on the data bus and transferred to the instruction decoder  Instruction is decoded and executed

17

Example: Instruction Fetch Operation

18

Example: Instruction Fetch Operation

19

8085 Functional Block Diagram