Transcript C - Weebly

COMBINATIONAL CIRCUITS
1. Combinational
LOGIC CIRCUITS:
2. Sequential
Combinational logic circuits (circuits without a memory):
Combinational switching networks whose outputs depend only
on the current inputs.
Sequential logic circuits (circuits with memory):
In this kind of network, the outputs depend on the current inputs
and the previous inputs. These networks employ storage elements
and logic gates. [Chapters 5 and 9]
COMBINATIONAL CIRCUITS
Most important standard combinational circuits are:
• Adders
• Subtractors
• Comparators
• Decoders
• Encoders
• Multiplexers
Available in IC’s as MSI and used as
standard cells in complex VLSI (ASIC)
Designing a Combinational Circuit
• From the Specification of the circuit,
determine the number of inputs and output.
Assign a symbol to each
• Derive the Truth Table that defines required
relationship between inputs and outputs
• Obtain Boolean function for each output as a
function of the input variable
• Draw the logic diagram and verify the
correctness of the design
DESIGNE CRITERIA
– MIN NO OF GATES
– MIN NO OF INPUTS
– MIN PROPAGATION TIME
– LIMITATION OF DRIVING CAPABILITIES OF
EACH GATE
ARITHMATIC OPERATIONS
• BASIC OPERATION IS ADDITION OF
TWO BINARY DIGITS. WHEN 0+0=0,
0+1=1, 1+0=1. AND 1+1=10.
• THEN FIRST THREE OPERATIONS
PRODUCE SUM OF ONE DIGIT
• FORTH PRODUCE TWO DIGITS.
HIGHER SIGNIFICANT BIT IS CALLED A
• CARRY
Binary Adder-Subtractor
• Most Basic arithmetic function is Addition of two
binary digits
– 0+0=0, 1+0=1, 0+1=1, 1+1=10 (Carry)
– Carry is added to the next higher order pair of significant
values
• A combinational circuit that performs addition of two
bit is called Half Adder
• A combinational circuit that performs addition of
three bits is called Full Adder (Adding two half
adder)
• Binary Adder Subtractor performs addition and
subtraction
BINARY ADDER – Half Adder
X
Y
S
C
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
BINARY ADDER - Full Adder
Inputs
INPUTS
x y z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Outputs
OUTPUTS
S
C
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
C
S  z  ( x  y)
Full Adder in SOP
Implementation Full Adder with two half Adders
S  z  ( x  y )  z  ( xy' x' y )
 z ' ( xy' x' y )  z ( xy' x' y )'
 z ' ( xy' x' y )  z[(x' y )(x  y ' )]
 z ' ( xy' x' y )  z ( x' y ' xy)
 xy'z'  x'yz' xyz  x' y ' z
HALF SUBSTRACTOR
1. TRUTH TABLE H/SUB
X
Y
D
B
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
TRUTH TABLE H-SUB
FULL SUBSTRACTOR
TRUTH TABLE F/SUB
Inputs
x
0
0
0
0
1
1
1
1
Outputs
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
B
D
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
TRUTH TABLE F- SUB
CODE CONVERTION
BCD TO EXCESS-3
•
INPUT
OUTPUT EX-3
A B C D
W X Y Z
0 0 0 0
0+3
0 0 1 1
0 0 0 1
1+3
0 1 0 0
0 0 1 0
2+3
0 1 0 1
0 0 1 1
3+3
0 1 1 0
0 1 0 0
4+3
0 1 1 1
0 1 0 1
5+3
1 0 0 0
0 1 1 0
6+3
1 0 0 1
0 1 1 1
7+3
1 0 1 0
1 0 0 0
8+3
1 0 1 1
1 0 0 1
9+3
1 1 0 0
DRAW K-MAPS WITH Don,t Care for WXYZ.
DRAW DIAGRAM
Analysis Procedure
• Determine the function that circuit
implements
• Ensure that circuit is combinational and not
sequential
– No feedback (Output of one circuit as a input to
another)
• Logic diagram
• Obtain the Boolean function or truth table
•
ANALYSIS OF COMBINATIONAL LOGIC
 ABC
 T3  T2
 A B C
 F2 'T1
 AB  AC  BC
ANALYSIS OF COMBINATIONAL LOGIC
F1  T3  T2  F2 ' T1  ABC
 ( AB  AC  BC)' ( A  B  C )  ABC
 ( A' B' )( A'C ' )(B'C ' )( A  B  C )  ABC
 ( A' B' C ' )( AB' AC' BC' B' C )  ABC
 A' BC' A' B' C  AB' C ' ABC
F2  AB  AC  BC
ANALYSIS OF COMBINATIONAL LOGIC
Inputs
INPUTS
Outputs
OUTPUTS
A
B
C
F1
F2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
From the truth table can you tell the function of the circuit?
MULTI LEVEL NAND CCTS
REPLACE INVERTERS WITH NAND GATES
FUNCTIONS REMAIN THE SAME
MULTI LEVEL NAND CCTS
• BOOLEAN FUNCTION IMPLEMENTATION
• F= A(B+CD)+BC’
• STEP -1. From Algebric Expression draw Logic
Diagram with AND ,OR. NOT Gates.
• STEP -2. Draw 2nd Logic Diagram with NAND
Gates.
• STEP 3. Remove Casecade Inverters.Remove
Single Inverter and complement Variable.
• F= (A+B’)(CD+E)
ANALYSIS PROCEDURE
•
•
•
•
•
STEP-1.
STEP-2
STEP-3
STEP-4
STEP-5
Given Logic Diagram.
Boolean Function.
Truth Table.
K-Map
Function
SYMBOLS OF NAND GATE
STEP-1 Draw NAND
Logic Diagram
BLOCK DIAGRAM
TRANSFORMATION
Remove Bubbles
Step-3
COVERT N AND TO AND
INVERT and INVERT OR
STEP-2
MULTI
LEVEL NOR CIRCUITS
REPLACE NOT WITH NOR GATES
ANALYSIS PROCEDURE AND BLOCK DIAGRAM
TRANSFORMATION IS THE SAME AS NAND CCTS
X OR COVERED IN CHAP 3
EXCLUSIVE-OR AND
EQUIVALENCE FUNCTIONS
ALREADY COVERED IN 3RD
CHAPTER
•END OF
TH
4
CHAPTER
• BCD  Excess 3 Code
• Digit 8
• Company
–
–
–
–
1 Manager
2 Clerk
1 Guards
During office hours When manager present atleast
one clerk
– During office hours When Manager missing both
clerks should be present
– After Business hours guard should be present
• Input
– Manager A, Clerk B, Clerk C, Guard D, Businesshours E
• Output
– Alarm F
DESIGN OF COMBINATIONAL LOGIC
Example: Design a combinational circuit with three inputs and one
output. The output is a 1 when the binary value is less than three.
The output is 0 otherwise.
x
y
z
F
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
0
x
1
1
0
0
y
1
1
1
0
0
y
yz
00
01
1
1
11
10
1
F  x' y' x' z '
x 1
z
z
F
•START OF
TH
5
CHAPTER
CCT OF BINORY FULL ADDER
Binary Adder
• Binary Adder is a circuit that produces sum of
two binary number
• It can be constructed with full adders (FA)
connected in cascade, with output carry from
one connected to the input carry of the next
3
2
1
0
i
full adder
0
1
1
0
Ci
• For Example
1
0
1
1
A
i
1011+00111110
0
0
1
1
Bi
1
1
1
0
Si
0
0
1
1
Ci+1
CASCADE 4-BIT FULL ADDER
BINARY ADDER
For Example
1011+001111
110
3
2
1
0
i
0
1
1
0
Ci
1
0
1
1
Ai
0
0
1
1
Bi
1
1
1
0
Si
0
0
1
1
Ci+1
Carry Propagation
Addition of two numbers in parallel implies that all bits are available
for computation.
Total propagation delay = propagation delay of a gate  # gate levels
In this case no of gate levels are =8
available only after C3 has
propagated through
Carry Propagation
Q: Find the total C propagation delay in the 4-bit full adder circuit.
Although some out (1/0)
will be there, it may not
be correct. Stable value
only after carry
propagation
Carry Propagation
The carry propagation time is a limiting factor on the speed with
which two numbers are added.
The most widely technique for reducing the carry propagation time
in a parallel adder uses the principle of carry lookahead
If define two variables P & G.
Carry Propagate from Ci to Ci+1
Pi  Ai  Bi
Si  Pi  Ci
Carry Generate from Input
Gi  Ai Bi
Ci 1  Gi  Pi Ci
Carry Lookahead Generator
Si  Pi  Ci
Ci 1  Gi  Pi Ci
C0  input carry
C1  G0  P0C0
C2  G1  P1C1  G1  P1 (G0  P0C0 )  G1  P1G0  P1 P0C0
C3  G2  P2C2  G2  P2G1  P2 P1G0  P2 P1 P0C0
Boolean Function for Carry is expressed in SOP
(2 level AND and OR gate)
4-bit Adder with Carry Lookahead
XOR Generates P
AND Generates G
Pi  Ai  Bi
Gi  Ai Bi
Si  Pi  Ci
Overflow
Overflow occurs when two numbers of n digits are added and the
sum occupies n +1 digits.
If V = 0  no overflow: n-bit results is correct.
If V = 1 overflow: The result contains n + 1 bits, and the (n+1)th bit is the
actual sign.( It means for 8bits we need 9bits)
V  C3  C 4
Decimal Adder BCD Adder
•
•
•
•
•
Binary adder  (1+1) Bit + 1 Carry= 3 bits
BCD(4+4) Bits + 1 Carry= 9 bits input
Max output is 9+9+1=19
4 bit adder
Input 2 BCD numbers
–
–
–
–
Sum will be in binary form
Output binary number from 0 to 19
AIM: Convert Binary back to BCD
When Binary Sum >1001 Add 0110 to corresponding Binary
number for correction.
– Correction is needed when K=1
– For no 1010 to1111 need correction, have 1 in Z8 and Z4 or
Z8 and Z2 Thus Boolean Function C=K+Z8Z4+Z8Z2. will
be used to get C=1 It will apply 0110 to second 4bit Adder
and carry in the output.
– Second addition take place. If carry occurs neglect it.
BCD Adder
Magnitude Comparator
A magnitude comparator is a combinational circuit that compares
two numbers, A and B, and then determines their relative magnitudes.
A>B
A=B
A<B
NOT REQUIRED BUT CAN BE
EXPLANED IF STUDENT WISH
Algorithm Consider two numbers, A and B, with four digits each:
A  A3 A2 A1 A0
B  B3 B2 B1B0
xi  Ai Bi  Ai ' Bi ' for i  0,1, 2, 3 XNOR (note mistake p. 133)
xi  1 if A  B  0 or A  B  1
For equality to exist, all x i variables must be equal to 1:
( A  B)  x3 x2 x1 x0
 AND operation
Magnitude Comparator
To determine if A is greater than or less than B, we inspect the relative
magnitudes of significant digits.
If the two digits are equal, we compare the next lower significant pair
of digits. The comparison continues until a pair of unequal digits is
reached.
The sequential comparison can be expressed by:
( A  B)  A3 B3'  x3 A2 B2'  x3 x2 A1B1'  x3 x2 x1 A0 B0'
( A  B)  A3' B3  x3 A2' B2  x3 x2 A1' B1  x3 x2 x1 A0' B0
Compare: A  1010and B  0101 ( A  B)  1
A  0101and B  1010 ( A  B)  1
4-bit Magnitude Comparator
XNOR
 A3' B3  x3 A2' B2  x3 x2 A1' B1  x3 x2 x1 A0' B0
 A3 B3'  x3 A2 B2'  x3 x2 A1B1'  x3 x2 x1 A0 B0'
 x3 x2 x1 x0
DECODERS
A decoder is a combinational circuit that converts binary information
from n input lines to 2n unique output lines.
i.e. Given a binary number input we want a specific output.
Applications:
• Microprocessor memory system: selecting different banks of memory.
• Microprocessor I/O: Selecting different devices.
• Microprocessor instruction decoding: Enabling different functional
units.
• Memory: Decoding memory addresses (e.g. in ROM).
• Bell for Mess Kitchen
3-to-8-line DECODER Truth Table
0
0
0
0
1
1
1
1
Binary Inputs
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D0
1
0
0
0
0
0
0
0
D1
0
1
0
0
0
0
0
0
D2
0
0
1
0
0
0
0
0
Outputs
D3
D4
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
D5
0
0
0
0
0
1
0
0
D6
0
0
0
0
0
0
1
0
D7
0
0
0
0
0
0
0
1
•Three inputs are decoded into eight outputs, each representing one
of the minterms of the three input variable
•If the input corresponds to minterm mi then the decoder ouputi will
be the single asserted output.
•Binary to OCTAL conversion IS ONE OF ITS APPLICATION
3-to-8-line DECODER
2-to-4-line DECODER with Enable Input
The decoder is enabled when E = 0. The output whose value = 0 represents the
minterm is selected by inputs A and B.
The decoder is disabled when E = 1 D0 … D3 = 1
A Decoder with enable input is called a decoder/demultiplexer.
Demultiplexer receives information from a single line and directs it to the output
lines.
Multiplexer is opposite of DeMultiplexer (Concept can be used to share Network)
Complemented outputs
A 4 x 16 DECODER
• When w = 0, the top decoder is enabled and the bottom is disabled.
Top decoder generates 8 minterms 0000 to 0111, while the bottom
decoder outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is enabled.
Bottom decoder generates 8 minterms 1000 to 1111, while the top
decoder outputs are 0’s.
Combinational Logic (Full-Adder) using Decoder
( x, y, z)  (1,2,4,7)
( x, y, z)  (3,5,6,7)
Encoding
• Encoding - the opposite of decoding
• Circuits that perform encoding are called encoders
• An encoder has 2n (or fewer) input lines and n
output lines which generate the binary code
corresponding to the input values
• Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.
Encoder Example
• A Octal-to- Binary encoder
– Inputs: 8 inputs corresponding to octal
digits 0 through 7, (D0, … , D7).
– Outputs: 3 bits Binary number.
– Function: If input bit Di is a 1, then the
output (X,Y,Z) is the Binary number for i,
• The truth table could be formed, but
alternatively, the equations for each of
the three outputs can be obtained
directly. Circuit is drawn on board
TRUTH TABLE ENCODER
Interchange outputs & inputs
D0
D1
D2
D3
D4
D5
D6
D7
X
Y
Z
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Encoder Example (continued)
• Input Di is a term in equation X,Y,Z is 1 in
the binary value for i.
• Equations:
Z = D1 + D3+ D5 + D7
Y = D2 + D3 + D6 + D7
X = D4 + D5 + D6 + D7
Two inputs at one time gives undefined
condition in the output
We get 0 o/p for all 0 i/p and D0
Priority Encoder
• If more than one input value is 1, then the
encoder just designed does not work.
• One encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
• Among the 1s that appear, it selects the most
significant input position (or the least significant
input position) containing a 1 and responds with
the corresponding binary code for that position.
• Valid Bit indicator set to 1 when one or more
inputs are equal to 1 If all inputs are 0, there is
no valid input and V is equal to 0.
MULTIPLEXERS/DATA SELECTORS
• A multiplexer is a combinational circuit that selects one of many
input lines (2n) and steers it to its single output line.
• Like a electronic Switch to select a source (Data Selector)
• There are (2n) and n selection lines whose bit combinations determine
which input is selected.
• The outputs of different AND gates are passed to a single OR Gate
4-to-1LINE MULTIPLEXER DESIGN
1
0
QUADRUPLE 2-to-1LINE MULTIPLEXER
Multiplexer can be combined with common selection inputs to provide multiple bit
selection logic.
This circuit has four Multiplexers, each capable of selecting one of two input lines
Output Yo can be selected to come from either input Ao or Bo
ENABLE must be active for Normal operation
This circuit allows us to consider one of two 4 bits sets of data lines
BOOLEAN FUNCTION IMPLEMENTATION
USING MUX(Procedure)
– Function in sum of minterms
– Take truth table
– Take single variable of highest order A and
complement for 0 to 3 minterms and
uncomplement for remaining terms
– Draw implementation Table
– Circle all minterms given in function
– Inspect each column separately IF
– Two columns not circled apply 0 to
corresponding mux input
CONTINUE
BOOLEAN FUNCTION WITH MUX
•
•
•
•
•
If two minterms are circled apply 1
If bottom minterm is circled apply A
If top minterm is circled apply A’ to mux
IMPLEMNT ON BOARD
2nd Method. Use A and B for selection,C for
input of Mux
F ( A, B, C )  (1,3,5,6)
F ( A, B, C, D)  (0,1,3,4,8,9,15)
DIFFERENCE OF MUX AND DECODER
• Decoder need additionl OR gate
• One Decoder can generate all minterms.
In mux one mux needed for each o/p
function.
• Decoder is used for decoding Binary info
• Mux is used to form a salected path
between multipal sources and single
destination
RANDOM ACCESS MEMORY
RAM IS READ/WRITE MEMORY. In which data can be written
or read from any sel address in any sequence.
TYPES
Static RAM(SRAM)
Dynamic RAM(DRAM)
Types of SRAM
Asynchronous SRAM
Synchronous burst SRAM
Types of DRAM
Fast Page Mode DRAM
Extended Data Out DRAM
Burst EDO DRAM
Synchronous DRAM
Storage Cell
READ ONLY MEMORY
It is a memory device in which a fixed set of info is
stored
Determined by no of words =2k & word= n
bits=number of outputs
TYPES OF ROM & function
•
•
•
•
Mask Programming
PROM
Erasable PROM
Functions
– It gives output for each minterm of SOP
– It is storage unit. Store words. i/p gives address to
words which is applied to the o/p
– Used in design of control unit.
• Micro Programmed control unit Use ROM to store
Binary con info
SIZE OF ROM
• Size is specified by number of bits.It means unit
has 4 o/p,9 i/p,to secify=512 words or
512*4=2048 bits.
• 32*4 ROM address is 5 bit no to 32 minterms
using 32 AND gates and 5 inverters
• 4 OR gates ,each having 32 links.
• Fuse can be linked as desired.
• F1 (A1,A0 )={(1,2,3,)}
• F2 (A1,A0)={(0,2)}
32*4 ROM 5 input variables are decoded into32 lines by
means of32 AND gates and 5
inverters
3*8 ROM
TRUTH TABLE
32*8 ROM
•
•
•
•
•
I4,I3,I2,I1,I0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
A7A6A5A4A3A2A1A0
1 0 1 1 0 1 1 0
0 0 0 1 1 1 0 1
1 1 0 0 0 10 1
1 0 1 1 0 0 1 1
• 1 1 1 1 1
0 0 1 1 0 0 1 1
Programming the ROM as given in truth table
Input=00011. output=10110010 from truthtable
EXAMPLE 5.5 ROM IMPLEMENTATION PAGE 187
Step1 Derive Truth Table for the ROM. As B0=A0 so no
need
B1 is always =0 so o/p is known We need to generate 4
outputs Therefore we need 3 input and 4 outputs 3 i/p gives 8
words of 4bits
PLA
PLA
• It is similar to PROM except PLA does not provide full
coding because Decoder is replaced by an array of AND
gates programmed to generate any product term of i/p
variables and connect to OR gates to give SOP for
Boolean Function.
• Size of PLA is specified by,no of i/p(n), no of product
terms(k), no of o/p (m),
• No of Links=2nxk+kxm+m
• Types. a. Mask programmable b.Field Prog array
• Design PLA with 3i/p, 3 sop and 2 o/p for
F1=A,B,C,=(4,5,7) F2=(A,B,C)=(3,5,7)
PLA
• Example 5.6 P 194
• Designe PLA with 3 i/p,4 Product terms,and 2
o/p
USING XOR GATES INSTEAD
INVERTERS AND LINKS T=O/P
MEANS 2ND I/P OF XOR BE
CONNECTED TO 0 IF C THEN
CONNECT TO 1.
•END OF
TH
5
CHAPTER
Function implementation using 8x1multiplexer
F ( A, B, C, D)  (1,3,4,11,12,13,14,15)
1. Complete the truth table from the SOP.
2. The first n – 1 variables in the table are applied to the
selection inputs of the multiplexer.
3. For each combination of the selection variables, we evaluate
the output as a function of the last variable.
4. Apply these values to the data input in proper order.
Example: Gray to Binary Code
• Design a circuit to
convert a 3-bit Gray
code to a binary code
• The formulation gives
the truth table on the
right
• It is obvious from this
table that X = C and the
Y and Z are more complex
Gray
ABC
000
100
110
010
011
111
101
001
Binary
xyz
000
001
010
011
100
101
110
111
Function implementation using 8x1 MUX
note the order of input lines
Multiplexer Approach 1
Design:
– Complete the truth table.
– The first n – 1 variables in the table are applied to the selection
inputs of the multiplexer.
– For each combination of the selection variables, we evaluate
the output as a function of the last variable.
– Apply these values to the data input in proper order.
Gray to Binary (continued)
• Rearrange the table so that the input combinations are in
counting order, pair rows, and find elementary functions
Gray
ABC
Binary
xyz
000
000
001
111
010
011
011
100
100
001
101
110
110
010
111
101
Elementary
Functions of
C for y
Elementary
Functions of
C for z
F=C
F=C
F=C
F=C
F=C
F=C
F=C
F=C
Gray to Binary (continued)
• Assign the variables and functions to the multiplexer inputs:
C
C
X
C
C
C
D00
D01
D02
D03
A
B
S1
S0
C
C
C
D10
D11
D12
D13
A
B
S1
S0
C
Out
4-to-1
MUX
Y
Out
4-to-1
MUX
Z
Multiplexer Approach 2
• Implement m functions of n variables with:
– Sum-of-minterms expressions
– An m-wide 2n-to-1-line multiplexer
• Design:
– Find the truth table for the functions.
– In the order they appear in the truth table:
• Apply the function input variables to the multiplexer
inputs Sn - 1, … , S0
• Label the outputs of the multiplexer with the output
variables
– Value-fix the information inputs to the multiplexer
using the values from the truth table (for don’t
cares, apply either 0 or 1)
Gray to Binary (continued)
• Rearrange the table so
that the input combinations
are in counting order
Gray
Binary
ABC
xyz
000
000
001
111
010
011
011
100
• Functions y and z can
100
001
be implemented using
101
110
a dual 8-to-1-line
110
010
multiplexer by:
111
101
– connecting A, B, and C to the multiplexer select inputs
– placing y and z on the two multiplexer outputs
– connecting their respective truth table values to the
inputs
Gray to Binary (continued)
0
1
1
0
0
1
1
0
A
B
C
D00
D01
D02
D03
D04
Out
D05
D06
D07
S2
8-to-1
S1
S0 MUX
0
1
1
0
1
0
0
1
Y
A
B
C
D10
D11
D12
D13
D14
Out
D15
D16
D17
S2 8-to-1
S1
S0 MUX
Z
Three State Gates
A three-state gate is a digital circuit that exhibits three states: 0, 1
and a high-impedance (high z state). The high impedance state
behaves as an open circuit Output appears to be disconnected and circuit
has no significance.
Because of this feature (high z state), a large number of three-state
gate outputs can be connected to form a common line without
endangering load effects.
Multiplexers with Three State Gates
When EN = 0, decoder outputs are zero,
and the bus lines are in high z state.
When EN = 1, one of the three-state buffers
will be active depending on the binary value in
the select inputs of the decoder.
When Select is 0 upper buffer is
enabled, lower when Select is 1
• Control inputs to buffer
determine which input will
be connected to output
• No more than one buffer
may be in active state at any
given time
• When Enable 0 All four
outputs are 0’s and circuit in
high impedance
• When Enable 1 one of
the three state buffer will be
active