VLSI Design Lecture 4-b: Layout Extraction

Mohammad Arjomand CE Department Sharif Univ. of Tech.

Gate Layout

 Layout can be very time consuming  Design gates to fit together nicely  Build a library of standard cells  Must follow a technology rule  Standard cell design methodology  V DD and GND should abut (standard height)  Adjacent gates should satisfy design rules  nMOS at bottom and pMOS at top  All gates include well and substrate contacts Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 2 of 50

Example: Inverter

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 3 of 50

Layout using Electric

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 4 of 50

Example: NAND3

     Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32  by 40  Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 5 of 50

Example: NAND3

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 6 of 50

Stick Diagrams



Stick diagrams

help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 7 of 50

Stick Diagrams



Stick diagrams

help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers VDD Modern VLSI Design 4e: Chapter 2 Vin Vout GND Sharif University of Technology Slide 8 of 50

Wiring Tracks

 A

wiring track

 4  width, 4  is the space required for a wire spacing from neighbor = 8  pitch  Transistors also consume one wiring track Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 9 of 50

Well spacing

 Wells must surround transistors by 6   Implies 12  between opposite transistor flavors  Leaves room for one wire track Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 10 of 50

Area Estimation

 Estimate area by counting wiring tracks  Multiply by 8 to express in  Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 11 of 50

Example: O3AI

 Sketch a stick diagram for O3AI and estimate area 

Y

 (

A



B



C

) 

D

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 12 of 50

Example: O3AI

 Sketch a stick diagram for O3AI and estimate area 

Y

 (

A



B



C

) 

D

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 13 of 50

Example: O3AI

 Sketch a stick diagram for O3AI and estimate area 

Y

 (

A



B



C

) 

D

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 14 of 50