Transcript Chapter 6
CMOS Analog Design Using All-Region MOSFET Modeling Chapter 6 Current Sources and Voltage References CMOS Analog Design Using All-Region MOSFET Modeling 1 Simple MOS current source IREF is, in general, very sensitive to VDD, R, and M Low current requires high R (large silicon area) (a) A simple MOS current source (b) Current x voltage characteristic of the input transistor and load line. RI REF I REF I REF VDD VT 0 nt 1 2 ln 1 1 I I S S CMOS Analog Design Using All-Region MOSFET Modeling 2 Widlar current source Low current can be generated without large resistances N is also a design parameter (more important than RS) Input current IREF often high – not convenient for low-power design CMOS Analog Design Using All-Region MOSFET Modeling 3 Self-biased current source - 1 weak inversion I OUT TC WI t RS ln K 1 1 dRS T RS dT strong inversion I OUT RS I OUT t I OUT 1 1 I I I S1 1 OUT 1 OUT ln I S1 KI S 1 I 1 OUT 1 KI S 1 t 2 1 2 1 RS I S 1 K 2 2 1 1 RS2 nCox n W / L 1 K TC SI CMOS Analog Design Using All-Region MOSFET Modeling 1 dnn 2 dRS nn dT RS dT 4 2 Self-biased current source - 2 I2 I2=I1 Point A Current mirror M3-M4 Current mirror M1-M2-RS Point B I1 Start-up circuit: ensures that A is the solution; “wakes-up” current source ASAP after power-up CMOS Analog Design Using All-Region MOSFET Modeling 5 MOSFET-only self-biased current source 1 i 1 if 1 VS 2 f1 ln K 1 if 1 1 ln t K if 1 1 1 K VS 2 t , 1 if 7 I D6 I D5 1 i f 7 1 1 ir 7 ln 1 ir 7 1 S5 I D1 S4 if 7 if 6 I D6 IS 6 I D7 I S 7 (i f 7 ir 7 ) I D1 I S1i f 1 if 7 I OUT nCox n t2 2 S7 2 J 1 2 J ( J 1) S5 S1 if 1 S 4 S6 S S S S S S ir 7 1 4 6 i f 7 1 4 6 5 1 i f 1 S5 S 7 S5 S7 S4 S6 J=S5S7/S4S6 CMOS Analog Design Using All-Region MOSFET Modeling 6 Bandgap voltage reference – 1 VCC VBE Choose M such that ~ -2 mV/oC dVout dT I1 T t T0 dVBE dT M T0 k 0 q Vout VBE M t + VBE - t generator t M Mt The output voltage for zero temperature coefficient is close to the “extrapolated” band-gap voltage of Si (1.206 V) k/q=+ 86.19 V/oC T CMOS Analog Design Using All-Region MOSFET Modeling 7 Bandgap voltage reference – 2 VBE M kT constant q Mt dVout dT T0 dVBE dT M T0 k 0 q VBE T CMOS Analog Design Using All-Region MOSFET Modeling 8 Bandgap voltage reference – 3 VBE I1 I C I sat exp t I sat qAni2 nt GB EG n DT exp kT 2 i 3 EG: 1.206 eV, silicon bandgap extrapolated to 0 K. Assume the average mobility of electrons in the base region is Assume that GB WB 0 n n 0 T / T0 N Adx m I1 I C 0 T / T0 The temperature coefficient of the voltage reference is d VBE M t VBE k E (4 m ) G M dT T q kT M =0 at T=T0 VOUT VBE 0 E G (4 m ) kT0 / q kT0 EG kT T (4 m )(1 ln 0 ) q q T VOUT T T0 kT T T0 (4 m ) 2q T CMOS Analog Design Using All-Region MOSFET Modeling 2 9 CMOS-compatible bandgap reference - 1 Both M1 and M2 in weak inversion kT I1 W / L 2 VO VBE V1 V2 VBE n ln q I 2 W / L 1 Problem: n=n(T, VG) Minimum supply: VBE+V1+VDSsat (current source) CMOS Analog Design Using All-Region MOSFET Modeling 10 CMOS-compatible bandgap reference - 2 R2 S2 kT S3 S2 VO 1 1 ln R S q S1 S4 1 4 PTAT voltage generator. Transistors M1 and M3 are biased in weak inversion. CMOS Analog Design Using All-Region MOSFET Modeling 11 CMOS-compatible bandgap reference - 3 VCC VCC I1 I2 + + VBE1 VBE2 - VBE1 t ln I1 I t ln 1 I S1 J S A1 VBE 2 t ln I2 I t ln 2 IS 2 J S A2 VBE VBE1 VBE 2 I A t ln 1 2 I 2 A1 VR1 VE 2 VE1 kT ln N q R kT VREF VBE 2 1 2 ln N R1 q CMOS Analog Design Using All-Region MOSFET Modeling 12 CMOS-compatible bandgap reference - 4 Problems: Op amp offset voltage Poor performance of substrate pnp transistors ?? VREF VEB 2 R2 kT ln N R1 q CMOS Analog Design Using All-Region MOSFET Modeling 13 Exercise Vertical (substrate) pnp transistors Band-gap reference in n-well CMOS Exercise: Show that VOUT Source of error R2 VEB 2 1 VEB VOS R3 CMOS Analog Design Using All-Region MOSFET Modeling 14 CMOS-compatible bandgap reference - 5 VFCM VFCM: voltage following current mirror VREF R2 kT VEB 3 ln N R1 q CMOS Analog Design Using All-Region MOSFET Modeling 15 CMOS-compatible bandgap reference - 6 p-well CMOS process Eric A. Vittoz, MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology, IEEE JSSC, Vol. 18, no. 3, pp. 273-279, June 1983 CMOS Analog Design Using All-Region MOSFET Modeling 16 CMOS bandgap reference with sub-1-V operation VDD M2 M1 I1 I3 I2 + R2 M3 I1a R1 - VREF I2a R2 R3 I2b I1b N Q1 1 I1=I2=I3 Q2 CMOS Analog Design Using All-Region MOSFET Modeling 17 Design of a SBCS – 1 SELF-CASCODE MOSFET (SCM) I S 2i f 2 NI x Sat. I 2 NI x i f 2 ir1 I S 1 (i f 1 i f 2 ) ( N 1) I x S 1 i f 1 1 2 1 i f 2 i f 2 S1 N Applying UICM to both M1 & M2 Triode VX t VX t 1 i f 2 1 i f 2 1 NI X NI X 1 S 2 I SH S 2 I SH CMOS Analog Design Using All-Region MOSFET Modeling 1 i f 2 1 ln 1 i f 2 1 NI X 1 1 S I 2 SH ln NI X 1 1 S I 2 SH 18 Design of a SBCS – 2 VX / t IX S2 0.01 S1 0.01 IX 2IX SCM1,2 3 S 0.01 SCM3,4 18.7 S 1.13 IX I X / I SH S4 1.13 S3 10 IX 2IX VX t 1 IX I 1 X SI SH SI SH CMOS Analog Design Using All-Region MOSFET Modeling IX 1 1 SI SH ln IX 1 1 SI SH 19 Design of a SBCS – 3 VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1 Vref VS 9 t 1 JKi f 8 1 i f 8 1 JKi f 8 1 ln 1 i f 8 1 When both M8 & M9 operate in WI: Vref VS 9 t ln( JK ) CMOS Analog Design Using All-Region MOSFET Modeling 20 Design of a SBCS – 4 Vx VFCM Vx A self-biased current source CMOS Analog Design Using All-Region MOSFET Modeling 21 Design of a SBCS – 5 VX t 1 i f 2 1 i f 2 1 i f 2 1 ln 1 i f 2 1 Output current: Iref=10 nA ISHn-channel100 nA, ISHp-channel40 nA =1 Let us choose M1 &M2 in MI: if2 = 10 1 S2= S1, N = 1 =10 nA S2 1 1 1 1 1 3 S1 N 1 30 1 1 30 1 10 ln 2.93 t 1 10 1 VX VFCM M3 &M4 in WI: if3(4) <<1 VX t ln e2.93 18.7 18.7 1 S4 1 S4 8.85 1 S3 1 S3 I S 2i f 2 10 nA I S 2 1 nA S2 S1 0.01 Let us choose if3=0.187 i f 4 i f 3 / 1 2S4 / S3 0.01 S S3 4 1.13 8.85 I S 4i f 4 10 nA I S 4 1 A S4 10 CMOS Analog Design Using All-Region MOSFET Modeling 22 Design of a SBCS – 6 Summary =1 S if ir M1 0.01 10 0 M2 0.01 30 10 M3 1.13 0.187 0.01 M4 10 0.01 0 M8, M8(a) 1 0. 1 0 M9, M9(a) 1 0. 1 0 MP (all) 2.5 0.1 0 =10 nA S4 10 S2 0.01 VX 2.93t S1 0.01 VFCM CMOS Analog Design Using All-Region MOSFET Modeling VX 2.93t S3 1.13 23 Design of a SBCS – 7 CMOS Analog Design Using All-Region MOSFET Modeling 24