Transcript Cadence Opus course

Introduction to Cadence
Opus
Digital HDL design
Silicon Ensemble
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
PKS and Silicon Ensemble PKS
SE-PKS
PKS
Synthesis, Placement
Clock Tree Generation
Silicon Ensemble
DEF
HDL
Floorplanning
DEF
HDL
Floorplanning
refinement
Post Clock Tree Optimization
Global Routing and Optimization
SI Analysis and Repair
Delay Calculation
DEF
WDB
SPF
Final Routing
Parasitic Extraction
WRoute ECO
DEF
HDL
In-Place Optimization
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Verification
Main features
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Automatic time budgeting
Interactive floorplan editor
Special power net routing
Productive global and detail placement
One-pass test synthesis
Automatic clock tree synthesis
Productive global and detail routing
Productive design analysis and debug
Full incremental accurate timing analysis
Faster run times and larger design capacity
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Automatic time budgeting
• Automates bottom-up
placement and routing
• Enables design methodologies that require a bottomup approach.
• Automatically computes
lower-level constraints
from top constraints.
• Slack allocation is based
on logic compressibility.
• High capacity reduces the
number of partitions.
Cadence Opus
course
Constraint application
a
b
Automatic generation
c
d
e
h
f
i
g
j
k
l
m
n
Block i
Block h
6 ns
block target
10 ns
chip target
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
4 ns
block target
Interactive floorplan editor
• Creates the starting floorplan by
estimating the required layout
area (die size and aspect ratio)
• Adjusts the floorplan to
accommodate design
requirements
• Creates the global and detailed
routing grids
• Creates the I/ O rows
• Creates the core rows
• Creates sites for corner cells
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Special power net routing
• Automates creation of rings for common floorplans
(rings and stripes)
• Automates creation of stripes
over standard cell rows.
• Makes it easy to edit ring and
stripe wires (change width).
• Makes it easy to connect and
disconnect “everything” to
rings (blocks, stripes, rows,
I/O rings, and Power Pads).
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Global and detail placement
• Allows automatic grouping and initial placement of
macros, standard cells and IOs
• Determines legal placement locations and the site
requirements
• Anticipates routing requirements by considering the
resulting positions of sets of pins that represent nets
• Supports netlist-driven placement optimization
• Extracts estimated parasitic information for timing
critical designs
• Reports placement congestion map
• Uses same algorithms as PKS logic synthesizer
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
One-pass test synthesis
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Top-down and bottom-up scan insertion
Verilog/VHDL (RTL and/or structural netlists)
Multiple clock domains (on separate chains)
Multiple balanced scan chains
Scan/Nonscan register reporting
Single-pass test synthesis
Full register scan
Multiple scan styles
DFT rule checking
Test mode setup
Shared I/O for test pins
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Automatic clock tree synthesis
• Constructs an optimized
clock tree
• Minimizes skew and clock
tree insertion delay
• Controls user buffer or
inverter selection
Generates correct syntax
for the router
• Accepts a placed netlist
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Global and detail routing
• Creates a global routing plan
• Uses the routing grid, GCell grid, netlist view, and the
locations of pins and blockages of placed components to
create the plan
• Creates detail routing for nets, or parts of nets, that have
a global routing plan
• Uses the routing grid, GCell grid, global routing, and the
locations of pins and blockages of placed components to
create detail routing
• Supports timing-driven optimization
• Includes auto search and repair tool
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Productive analysis and debug
•Critical path analysis
•Accurate timing displayed on schematic
•Cross-correlation between reports and RTL
Timing histograms
•Design statistics
•Parasitic backannotation
•Clock skew analysis
•Floorplan verification
•Geometry verification
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Full incremental timing analysis
• Re-times only individual gate
• Performs only necessary updates
D Q
D Q
CLK
CLK
retime
critical path!
stale data okay
unchanged
D Q
CLK
U1
D Q
CLK
• Much larger design capacity and less memory usage
• Converging placement and routing results
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Available Documentation
• Documentation is available in HTML and PDF formats.
– Includes the complete documentation set (User Guides, Command
Reference and Application Notes). Netscape is shipped with all Cadence
synthesis tools
• Subscribe to http://sourcelink.cadence.com for best
online help with Cadence tools.
• There is a text help feature for sesi. At the sesi
prompt, enter:
help <command_name> or help <error_code>
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Prerequisites to start PKS
• Set the Unix environment variables (This solution is site specific!)
setenv CDS_INST_DIR /soft/opus/dsmse53
setenv CDS_INSTALL_DIR /soft/opus/dsmse53
setenv PATH $CDS_INST_DIR/tools/bin:$CDS_INST_DIR/tools/dfII/bin:
$CDS_INST_DIR/tools/dsm/bin:$PATH
setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib:$LD_LIBRARY_PATH
• Set Cadence license environment variable
setenv CDS_LIC_FILE license_file
• Check the special licenses!
ENVISIA_SE_SI_place_route
Clock_Tree_Generation
Silicon_Ensemble
Silicon_Ensemble_DSM
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Getting started with place-and-route
In the next few pages, you will become familiar with the
basic commands and acronyms needed to generate a
simple layout. The case study that follows lets you
experiment with the software.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
SE Place-and-Route Flow
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Cadence Opus
course
Read the physical library file
Read the timing library
Read the Verilog or DEF database
Read the constraints file
Initialize the floorplan area
Place I/O cells and macros
Initialize power planning
Place standard cells
Generate the clock tree
Route special nets (power, clock)
Generate and optimize routing
Verify timing goals have been met
Write out files for backannotation
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Login into the workstation
Login: cadence
Password: cadence
Guest user
with full rights
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Start up Silicon Ensemble
Middle click at an empty place
of the screen and the
Engineering Tools popup
window opens.
Make a left click on the
OPUS  Silicon Ensemble
This solution is site specific!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Start up Silicon Ensemble
The Silicon Ensemble
graphical user interface
opens.
main design window
object selection window
message window
command line
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Physical Library File (LEF)
A Library Exchange Format (LEF) file is an ASCII file that
contains library information for a class of designs:
•Library data in ASCII format
•Wire unit parasitic information
•Detailed cell size and pin location
•Routing level information
•Macro cell definitions
Timing Library File (TLF, CTLF)
The TLF or CTLF file is a timing library for the standard cells.
A timing library includes all of the timing information
associated with a particular manufacturing process.
Only a single timing library is required by the P&R flow.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Physical Design Exchange Library File (DEF and PDEF)
The DEF file contains physical design data such as placement
and bounding box data, routing grids, power grids, pre-routes
and rows. DEF can also include additional information such as
routing grids, power grids, pre-routes, and rows. This physical
data is an optional input that would typically be available if this
were a redesign of an existing device.
General Constraint Format File (GCF)
General Constraints Format (GCF) is the Cadence specification
for inputting System Level Constraints (SLC). GCF specifies
system-level and boundary timing constraints for a design.
General Constraint Format (GCF) file gives the path to the
CTLF file, which is then loaded automatically.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Standard Delay File (SDF)
After a generic netlist is read, Standard Delay Format (SDF)
data can also be loaded to include physical design constraints.
In addition, timing information is conventionally stored in a SDF
file. Individual net RC and design SDF timing information is
annotated to the design within the synthesis software to
provide an accurate timing and design rule violation view of the
design.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the physical library
Left click on the
File  Import  LEF...
Select the correct library exchange format file from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the timing library
Left click on the
File  Import  Timing Library...
Select the correct timing library file from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the Verilog database
Left click on the
File  Import  Verilog...
Read in the Verilog source files and libraries from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the physical database
Left click on the
File  Import  DEF...
Select the correct design exchange format file from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the constraints file
Left click on the File  Import  System Constraints… or
File  Import  SDF… depending on the constraint type
Select the correct constraints file from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Save the current state
Left click on the
File  Save As…
Set the correct
Design Name value
Click on OK
.
Switch on Keep Editing Current Design to leave the
original design database opened.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Initialize the floorplan area
Left click on the Floorplan  Initialize Floorplan...
Fill out the form
Switch on Abut Rows
and Flip Every Other
Row if physical library
enables it
Click on Calculate
and check the result
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generated floorplan view
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place I/O cells automatically
Left click on the
Place  IOs...
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place I/O cells from file
Left click on the
Place  IOs…
Select I/O Constraint
File On the Placement
Mode tab
Click on Write
Click on Edit and
modify the I/O order
Save the file
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Fill out the I/O gaps
Left click on the
File  Execute…
Select fillperi.mac
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generated I/O placement view
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place macro cells
Check on the visibility and selectivity of the
Cell in the Object Selection Window.
Left click on Sl column
Select one of the soft blocks near the lower
left corner of the design
Left click on the block
Move the block to the corner of the core area
Left click on the Move icon
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place macro cells
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Cut rows around macros
Left click on the Floorplan  Update Core Rows...
Set Global Block Halo
to the correct value
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Initialize power planning
Left click on the
Route  Plan Power…
yellow dotted line around the
core shows the global topology
Leave the toolbox opened!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Add power rings
Left click on the Add Rings… on the Plan Power toolbox
Fill out the signed fields and click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Add power stripes
Left click on the Add Stripes… on the Plan Power toolbox
Fill out the signed fields and click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generated power plan
Click on Close on the Plan Power toolbox to stop the command
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place standard cells
Left click on the Place  Cells…
Click on Options
Set Extra Sites for
Clock Buffers to 0.6
(this reserves place for
clock tree generator)
Click OK in the Place
Cells Options form
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generated placement view
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Fill out the cell gaps
Left click on the
File  Execute…
Select fillcore.mac
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Save the current state
Left click on the
File  Save As…
Set the correct
Design Name value
placed
Click on OK
.
Switch on Keep Editing Current Design to leave the
original design database opened.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Route power nets
Left click on the
Route  Connect Ring...
Switch off IO Ring
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Route power nets
Left click on the Route 
Route Power  Follow Pins…
Set Primary Layer Name to MET1
and Width to 2.0
Set the correct Area and Core Area
values
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generate global and detail routing
Left click on the Route  Wroute…
Click on Options and select
Optimize Wire Length
Click OK in the WRoute
Option form
Click OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Detail routing view
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Save the current state
Left click on the
File  Save As…
Set the correct
Design Name value
routed
Click on OK
.
Switch on Keep Editing Current Design to leave the
original design database opened.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Verify connectivity
Left click on the
Verify  Connectivity…
Correct the violations
manually or with Route 
Search And Repair…
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Report RC parasitics
Left click on the
Report  RC…
Set the correct value
for Report Filename
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Report design delay
Left click on the
Report  Delay…
Set the correct value
for Filename and
Use RSPF
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Write out DEF file
Left click on the
Export  DEF…
Set the correct value
for DEF File Name
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Write out GDS2 file
Left click on the
Export  GDS II…
Set the correct value
for GDS-II File and
Map File
Set Structure Name
to your_top_cell_name
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Break!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study I
Arithmetical Logical Unit (ALU)
The center core of a central processing unit, performs a set
of arithmetic and logic micro operations
Generate a behavior Verilog description of ALU
Sel[4:0]
Sel[1:0]
A[7:0]
B[7:0]
Sel[2]
Logic
Unit
Logic Unit [7:0]
MUX
ALU_noShift[7:0]
Arith Unit [7:0]
Carryin
Cadence Opus
course
Sel[4:3]
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Shifter
Case study I
Arithmetical Logical Unit (ALU)
It has n encoded inputs for selecting which operation to perform
S4
0
0
0
0
0
0
0
0
S3
0
0
0
0
0
0
0
0
S2
0
0
0
0
0
0
0
0
S1
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Cadence Opus
course
Operation
Y <= A
Y <= A + 1
Y <= A + B
Y <= A +B + 1
Y <= A + Bbar
Y <= A + Bbar + 1
Y <= A - 1
Y <= A
Function
Transfer A
Increment A
Addition
Add with carry
A plus 1's complement of B
Subtraction
Decrement A
Transfer A
0
0
0
0
Y <= A and B
Y <= A or B
Y <= A xor B
Y <= Abar
AND
OR
XOR
Complement A
Logic Unit
Logic Unit
Logic Unit
Logic Unit
0
0
0
0
Y <= A
Y <= shl A
Y <= shr A
Y <= 0
Transfer A
Shift left A
Shift right A
Transfer 0's
Shifter Unit
Shifter Unit
Shifter Unit
Shifter Unit
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Implementation block
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Case study I
You can find the verilog source in the lab1 directory. The
technology and timing library are in the lib directory under
your SE home directory.
In this exercise you have to do these steps:
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Load database (.lef, .gcf and .v | .def) files
Load the constraints (.gcf | .sdf)
Create initial floorplan
Initialize power planning
Place standard cells and optimize placement
Route power nets
Generate and optimize routing
Verify timing goals (timing path) and connectivity
Write out files (.def, .lef, GDSII, …)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
Central Processor Unit (CPU)
The design of a processor is a complex scenario. Multimillion
instruction processors (MIPS), complex instruction set
processors (CISC), reduced instruction set processors (RISC)
are all models that are used in different applications.
The HDL description you will be working with is a simple
processor that does 4 simple mathematical functions.
The circuit implements addition, incrementing, complementing
and XOR.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
The schematic of CPU
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
The operation of the CPU
The CPU begins to operate on the positive edge of the reset.
At all positive edge of the clock signal the operation state of the
CPU changes. There are 8 states of the operation / cycle period
On reset signal the counter of the CPU resets, and set pcout
(address of instructions) to 00h – this is the address of the first
instruction. The value of the PC register is incremented per each
cycle
The ALU executes an instruction (which one is determined by
opcode) when ena is enabled.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
You can find the verilog source in the lab2 directory. The
technology and timing library are in the lib directory under
your SE home directory.
In this exercise you have to do these steps:
•
Load database (.lef, .gcf and .v | .def) files
•
Load the constraints (.gcf | .sdf)
•
Create initial floorplan
•
Place I/O cells and macros
•
Initialize power planning
•
Place standard cells and optimize placement
•
Route power nets
•
Generate and optimize routing
•
Verify timing goals (timing path) and connectivity
•
Write out files (.def, .lef, GDSII, …)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study III
You can find the PKS generated files in the lab3 directory.
The technology and timing library are in the lib directory
under your SE home directory.
In this exercise you have to do these steps:
•
Load database (.lef, .gcf and .def) files
•
Load the constraints (.sdf)
•
Create initial floorplan
•
Place I/O cells and macros
•
Initialize power planning
•
Optimize placement
•
Route power nets
•
Load .wdb file and optimize routing
•
Verify timing goals (timing path) and connectivity
•
Write out files (.def, .lef, GDSII, …)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Full Break!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory