Transcript 3. Seville workshop 9-14-2010

ITRS workshop on Emerging
Spin and Carbon Based
Emerging Logic Devices
George Bourianoff, Intel
Jim Hutchby, SRC
Barcelo Renacimiento Hotel
Conference Room D2
Sept 17, 2010 (8:00 – 18:30)
Seville, Spain
Outline
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ERD charter
Background
Meeting Objectives
Next steps, timeline
Agenda
Charter of ERD Chapter
On behalf of the 2011 ITRS, develop an
Emerging Research Devices chapter to -Critically assess new approaches to Information
Processing technology beyond ultimate CMOS
 Identify most promising approach(es) to Information
Processing technology to be implemented by 2024

To offer substantive guidance to –
Global research community
 Relevant government agencies
 Technology managers
 Suppliers

3 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting
Work in Progress --- Not for Publication
Scope of ERD Chapter
Integrated emerging research memory, logic and
new architecture technologies enabled by
supporting -Materials and process technologies
 Modeling and simulation
 Metrologies

Selection of specific technical approaches shall be


Guided by fundamental requirements
Bounded by ERD’s topic selection criteria
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Scope of ERD Chapter
Criteria for Including Technology Entries
Devices and Architectures –



Published by 2 or more groups in archival literature and peer
reviewed conferences, or
Published extensively by 1 group in archival literature and peer
reviewed conferences
Technology Entry (by itself or integrated with CMOS) must
address a major electronics market.
Materials and Fabrication Technologies –


Materials and processes that address the specific material needs
defined by emerging research device technology entries
Supporting disciplines – specify for crosscut TWGs
 Metrologies
 Modeling & simulation
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Emerging Research Devices Working Group
Meeting Objectives

Review ERD/ERM 2010 Workshops (cont’d)

Logic Devices
Summary of VLSI Tech Workshop on III-V MOSFETs
 Assessment of III-V compound & Ge MOSFET technology
 Carbon-based nanoelectronic devices
 Spin Transfer Torque logic devices
 Review plans for ERD Device workshop in Seville, Spain on Sept. 17


Emerging Research Architectures (Logic device benchmarking)
Current status
 Plans for 2010 – 2011



Summary of potential changes in 2011 ERD Chapter
Summary of potential changes in 2011 ERM Chapter
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Background
• ITRS rewritten on a 2 year cycle
– Information gathering workshops and chapter
writing done on alternate years
– 2010 is devoted to workshops
– Previous Emerging Logic Workshop was held
in Tsukuba, Japan 2008 focusing on spin and
graphene devices
• This workshop will review significant
accomplishments in those areas in the
intervening 2 years
Meeting objectives
• Review significant new research initiatives
in spin based logic
• Review significant research programs and
accomplishments in graphene based logic
• Hold brief business meeting
– Discuss 2011 ERD Logic Table structure and
en tries
– Discuss potential writing assignments
Morning AGENDA
Progress, status and research needs for spin based
logic elements – Sept, 17, 2010
8:00
Welcome and Introductions
G. Bourianoff
8:15
Overview of DARPA Spin Logic Program
D. Shenoy
8:50
Nano-magnetic Logic
S. Hu
9:25
All Spin Logic
B. Bhin-Aein
10:00
Break
10:15
Magnetic FPGA Spin in Logic
T. Hanyu
10:50
"TIMARIS" Linear dynamic deposition technology
W. Maass
for production of spintronic devices
11:25
Wrap-up and Discussion
12:00
Lunch
9 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting
G. Bourianoff
Work in Progress --- Not for Publication
Afternoon AGENDA
Progress, status and research needs for graphene
based logic elements – Sept. 17, 2010
13:15
Graphene Logic Devices
P. Kim
13:50
Analog & RF Graphene – based FETs
C.Y. Sung
14:20
GRAND Perspectives on Graphene Electronics
H. Kurz
15:00
Break
15:15
Gate induced Bandgap for Graphene Devices
15:50
Graphene Research at CEA
S. Roche
16:25
Wrap-up and Discussion
J. Hutchby
17:00
Break
17:30
ITRS Business Meeting
18:30
Adjourn
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T. Tsukagoshi
J. Hutchby
Work in Progress --- Not for Publication
Business meeting
Emerging Research Logic Device
business meeting
• Review table structure and make
recommendations
– 2009 had 3 tables plus transition table
– Table 1 MOSFETS: Extending the channel to the End
of the Roadmap
– Table 2 Charge based Beyond CMOS: NonConventional FETs and other Charge-based
information carrier devices
– Table 3 Alternative Information Processing Devices
• Review table entries and make
recommendations
New Logic Technology Tables
Table 1 – MOSFETs
Extending the Channel
of MOSFETs to the
End of the roadmap
_____________
CNT FETs
Graphene nanoribbons
III-V Channel MOSFETs
Ge Channel MOSFETs
Nanowire FETs
Non conventional
geometry devices
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Table 2- Unconventional
FETS, Charge-based
Extended CMOS
Devices
_______________
Table 3 - Non-FET, Non
Charge-based ‘Beyond
CMOS’ devices
Tunnel FET
I-MOS
Spin FET
SET
NEMS switch
Negative Cg MOSFET
Collective Magnetic Devices
Moving domain wall devices
Atomic Switch
Molecular Switch
Pseudo-spintronic Devices
Nanomagnetic (M:QCA)
_______________
2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009
2009 Logic Transition table
Technology
Status
Reason
RTD
out
No viable
logic
functionality
Bi-layer
tunneling
devices
In
Significant
theoretical
work in NRI
Band to band In
tunneling
devices
NEMS
In
RSFQ
Possible
future device
Comment
Has been
tracked for
multiple
revisions
Table ERD7b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices
Device
FET [A]
Tunnel FET
Typical example devices
Si CMOS
All Si tunnel FET
Strained Ge or III-V
Projected
100 nm
20 nm [A]
Demonstrated
590 nm
Demonstrated: 70
nm, 100nm [B,C]
Negative Cg FET
Spin Transistor
I-MOS
Ferroelectric FET
[H], [I]
100 nm
100 nm [same as
CMOS]
Spin FET [K]
Spin MOSFET
100 nm
for spin MOSFET
[L]
bCell Size
(spatial pitch) [B]
Density
(device/cm 2 )
Projected
1.00E+10
Not known:
channel length
scalable down to
20nm [D]
Demonstrated
2.80E+08
~1E10
Projected
12 THz
Not known
Demonstrated
1.5 THz
Si/Ge/InAs tunneling
source:
1GHz/1THz/3THz
[A]
Switch Speed
Projected
61 GHz
Not known
Demonstrated
5.6 GHz
will depend on the
source material used
Projected
3.00E-18
Not known
1.00E-16
Si/Ge/InAs tunneling
source:
90/90/3000E-18
J/um at VDD=0.5V,
L=20nm [A]
Circuit Speed
Demonstrated
GBit/ns/cm
2
2000 nm
1.00E+10
1E10[same as
CMOS] [I]
2.50E+07
Unknown
Unknown Limited by
the ferroelectric
Identical to
response time,
CMOSFET- with Ge,
depends on the
SiGe [E],[F],[G]
ferroelectric material
not known
MEMS
40 nm [O]
100 nm [X}
~200 nm [P,Q]
900 nm
for spin MOSFET
[L]
6.00E+10
1.00E+10
Not investigated
~2E9
1 /cm**2 W2
10 THz [R]
1 GHz [Y]
2 THz [S]
0.18 GHz [Z]
for spin MOSFET
[M]
2 GHz [O]
1 GHz
Not investigated
1 MHz [T]
.18 GHz
1E-17-1E-18
1×10–18 [O]
for spin MOSFET
[M]]
[>1.5×10–17 ] [U]
~1mm (channel
length)
for Spin FET[M]
~1E10
~10 THz or less
for spin MOSFET
[N]]
30GHz
N/A
for Spin FET[M]
Identical to
CMOSFET- with Ge,
SiGe [E],[F],[G]
Unknown Limited by
the ferroelectric
response time,
depends on the
~10GHz or less
Not known:
Switching Energy, J
Binary Throughput,
Unknown
Single Electron
Transistor
Projected
238
Not known
not known
Identical to
CMOSFET- with Ge,
SiGe [E],[F],[G]
N/A
unknown
5E -17 J
[A1,A2]
8×10–17 [V]
N/A
Not investigated
[>1.3×10–14] [W]
Not known
~200
10
not known
not known
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Table ERD7c
Alternative Information Processing Devices
Collective spin devices Moving Domain wall
State Variable
Spin
Response Function
Sinusoidal, various
Class—Example
Spin Wave Mach
Zender
Architecture
Morphic
Application
Signal Processing
Comments
Status
Material Issues
Demonstrated
High propagation loss,
slow propagation
velocity
Atomic switch
Molecular
Pseudospintronc
Charge distribution
metal cations / atoms
symmetry in two
layers
Gate controlled
Non linear
Non-linear
Nonlinear, NDR
NDR
Bilayer Pseudospin
Ferromagnetic wire
Combinatorial logic
Programable logic
Field Effent
devices
circuits
Transistor
Morphic
Morphic, cross bar
Morphic
Morphic
Low power,
Combinatorial logic General purpose
Non volitale logic
reconfigurable logic
circuits
logic
Low resistance, low
Extremely low
power
power
Simulated
Demonstrated
Simulated
Simulated, theory
Polarization,
magnetization
High permeability
material required
Molecular
configuration
Low defect bilayer
graphene, contacts
Nano magnetic
Magneric
polarization
patterns
Non linear
MQCA majority
gate
Morphic
General purpose
logic
Low power, high
density
Demonstrated
Issues and Decisions for 2011 Chapter - Logic
Logic (Baltimore):
The following questions were addressed:
1. Is the new organization (e.g. 3 subsections) an effective taxonomy of
logic devices?
2. Are the technology entries the best candidates pursed by the research
community?
3. Any technology entries in the logic chapter to move to the transition
table? Potential
candidates for 2011?
4. Right level of details? Mission accomplished concerning current status and
critical paths?
Refer to Adrian Ionescu’s presentation for his thoughtful answers to these
questions (attached to this file).
• In the Logic Transition Table, the IN/OUT entries for Ge FET, Spin
MOSFET, Collective Spin Devices, Pseudomorphic, and Nanomagnetic
Devices should be move into the Comment column to the right. Entries in the
IN/OUT column might better be technical in nature. (being considered &
discussed)
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Work in Progress --- Not for Publication
Issues and Decisions for 2011 Chapter - Logic
• Areas for improvements (suggested by Adrian Ionescu):
– Introduction of energy efficiency criteria? Important (being
considered/discussed)
– Role of other functionality than digital of beyond CMOS: image
processing, analog, RF, etc. (being considered/discussed)
– Convergence of beyond CMOS and More than Moore technology entries?
MEMS/NEMS already in (being considered/discussed)
– More interaction with emerging architectures needed. (Decided)
• Transfer to PIDS in 2011
– Alternate channel materials , Ge and III-V Semiconductors (keep CNT and
GNR FETs) (Decided)
– Unconventional FET s, Tri-Gate, FinFET, GAA FETs, etc. (Decided)
Logic (Hsinchu):
• Transfer to PIDS in 2011
– Alternate channel materials , Ge and III-V Semiconductors (keep CNT and
GNR FETs) (Decided)
• Unconventional FET s, Tri-Gate, FinFET, GAA FETs, etc. (Decided)
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Memory Technology Entries
Resistive Memories
Nanoelectromechanical
Spin Transfer Torque MRAM
Macromolecular (Polymer)
Molecular Memory
Electronic Effects Memory
− Charge trapping
− Metal-Insulator Transition
− FE barrier effects
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Nanothermal
–Thermochemical FUSE/Anti-FUSE
− Nanowire PCM
 Nanoionic Memory
(Electrochemical)
− Cation migration
− Anion migration
Capacitive Memory
FeFET Memory
2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009
Issues and Decisions for 2011 Chapter - Memory
Memory (Baltimore):
• In the Memory Section, we need to discuss fabrication
and issues related to the select device, either a diode or a
transistor, for the storage elements in a cross-bar array.
• We will include emerging research solid state Storage
Class Memory technologies, but not include SCM
based on mechanical or magnetic disc storage. The
driving issue is to minimize the cost per bit – this is very
important.
Memory (Hsinchu): No decisions
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Proposed changes to the ERD
Memory section

To take out the “electronic effect memories” entry from
the ERD memory table

The FTJ memory could be covered along with FeFET as
a subcategory

Mott Memory could form a stand-alone entry if the ERD
group decides, there is a sufficient critical mass of works
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