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EE 5301 – VLSI Design Automation I Part I: Introduction Fall 2008 EE 5301 - VLSI Design Automation I 1 Administrative issues • Class Time and venue: MW 12:20pm – 1:35pm, ME 108 Web page: o http://www.ece.umn.edu/class/EE5301 Textbook: Sadiq M. Sait, Habib Youssef, "VLSI Physical Design Automation: Theory and Practice", World Scientific Publishing Company,1999. • Grades 30% homework (~5 homeworks) 20% each, two midterms o Tentative dates: Mon Oct 22, Wed Nov 26 30% mini-projects (~2 mini-projects) o Includes oral presentation for the second Programming required! Fall 2008 EE 5301 - VLSI Design Automation I 2 Administrative issues (contd.) • Personnel Instructor: Sachin Sapatnekar o Email: [email protected] o Phone: (612) 625-0025 o Office: 4-153 EE/CSci o Office hours: MW 11am-noon, or by appointment TA: TBD o Email: [email protected] o Phone: (612) 62x xxxx o Office: x-xxx EE/CSci o Office hours: TBD, or by appointment Fall 2008 EE 5301 - VLSI Design Automation I 3 Administrative issues (cont.) • Policies Electronic submission of homework preferred o Must be received by the due date o If you submit a hardcopy, it must be in before class starts o You will lose 10% of the total score for each day or part thereof • Example: If the HW is graded out of 100 and you are 30 hours late, you automatically lose 20 points Zero tolerance for cheating Collaboration OK, copying NOT OK No extra work for extra credit Check class web pages regularly, students are responsible for checking discussion threads and announcements regularly Subscribe to the class mailing list (instructions on the web page) Fall 2008 EE 5301 - VLSI Design Automation I 4 Online slides • Slides are posted on the web Handouts posted as .pdf files Powerpoint slides provided too o NOTE: some slides are animated (like this one) o Click on the slide to see the animation o Click once more. o Some slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see) This is a sample text, not printed, but animated Fall 2008 EE 5301 - VLSI Design Automation I 5 What is this course all about? • Prerequisite C / C++ programming experience • What is covered? Basic algorithms, complexity theory Integrated circuit (IC) Design flow Computer Aided Design (CAD) tool development for Very Large Scale Integration (VLSI) Lots of programming! • Next slides: Overview of IC design steps Related courses at U of M Outline of this course Fall 2008 EE 5301 - VLSI Design Automation I 6 The overall IC industry Fall 2008 EE 5301 - VLSI Design Automation I 7 IC products • Processors CPU, DSP, Controllers • Memory chips RAM, ROM, EEPROM • Analog Mobile communication, audio/video processing • Programmable PLA, FPGA • Embedded systems Used in cars, factories Network cards • System-on-chip (SoC) Boom! Fall 2008 EE 5301 - VLSI Design Automation I 8 The inverted pyramid Electronic Systems > $1 Trillion Semiconductor > $220 B CAD $4 B Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 9 Semiconductor industry growth rates Source: http://www.icinsight.com/ (McClean Report) Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 10 More demand for EDA CAE = Computer Aided Engineering Source: http://www.edat.com/edac Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 11 Growth in system size CAGR = Compound Annual Growth Rate Source: http://www.edat.com/edac Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 12 Evolution of the transistor Transistor Early IC http://www.nobel.se/physics/educational /poster/2000/kilby.html Vacuum tube (http://www.pbs.org/transistor/teach/ teacherguide_html/lesson1.html) Fall 2008 EE 5301 - VLSI Design Automation I Modern IC 13 Acronyms, acronyms everywhere.. • • • • • SSI (small scale integration) MSI (medium scale integration) LSI (large scale integration) VLSI (very large scale integration) … Fall 2008 EE 5301 - VLSI Design Automation I 14 Example: Intel processor sizes Silicon Process 1.5m Technology 1.0m 0.8m 0.6m 0.35m 0.25m Intel386TM DX Processor Intel486TM DX Processor Pentium® Processor Pentium® Pro & Pentium® II Processors Source: http://www.intel.com/ Fall 2008 EE 5301 - VLSI Design Automation I 15 Moore’s law [intel.com] Fall 2008 EE 5301 - VLSI Design Automation I 16 The Moore’s law article Electronics, Vol. 38, No. 8, Apr 19, 1965 Fall 2008 EE 5301 - VLSI Design Automation I 17 Feature size trends • Recent history 0.8mm0.5mm0.35mm0.25mm0.18mm0.13mm90nm 65nm45nm • Projected technologies 32nm22nm16nm • 0.7x per generation, 0.5x every two generations [R. Saleh] Fall 2008 EE 5301 - VLSI Design Automation I 18 Starting up a technology node Fall 2008 EE 5301 - VLSI Design Automation I 19 The International Technology Roadmap for Semiconductors (ITRS) [public.itrs.org] Fall 2008 Year Tech Node (nm) Num of Tran Num Wire Level 2001 2003 2005 2007 2010 2013 2016 130 100 80 65 45 32 22 97M 153M 243M 386M 773M 1.55G 3.09G 8 8 10 10 10 11 11 f (MHz) Vdd (V) Power (W) 1.7 3.1 5.2 6.7 11.5 19.3 28.8 1.2 1.0 0.9 0.7 0.6 0.5 0.4 130 150 170 190 218 251 288 EE 5301 - VLSI Design Automation I 20 ITRS: Chip frequencies Clock speed GHz 11 9 7 5 3 1 0 1997 1999 2001 2003 2006 2009 2012 On-chip, local clock, high performance On-chip, global clock, high performance Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 21 The role of design automation Fall 2008 EE 5301 - VLSI Design Automation I 22 Tera-scale integration effects • Exponential increase in device complexity Increasing with Moore's law (or faster)! • More complex system contexts • Require exponential increases in design productivity Complexity System contexts in which devices are deployed (e.g. cellular radio) are increasing in complexity We have exponentially more transistors! Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 23 Nanometer-scale effects Crosscoupled capacitances Signal integrity Wire resistance effects Wire inductance effects Increased leakage Quantum effects Reliability problems… DSM Effects • Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: Design of each transistor is getting more difficult! Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 24 Heterogeneity on chip • Greater diversity of onchip elements Processors Software Memory Analog Heterogeneity • “more than Moore” technologies More transistors doing different things! Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 25 Stronger market pressures • Decreasing design window • Lower tolerance for design revisions Time-to-market Exponentially more complex, greater design risk, greater variety, and a smaller design window! Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 26 A QuadrupleWhammy Tera-scale integration Time-to-market Heterogeneity Nanometer-scale Effects Fall 2008 EE 5301 - VLSI Design Automation I [©Keutzer] 27 How are we doing? 10,000,000 1,000,000 100,000 10,000 1,000 100,000 Productivity gap 10,000 1,000 100 2005 2001 1997 1989 1981 1993 100 21% / Yr. compound productivity growth rate 10 10 Role of EDA: close the productivity gap Fall 2008 Productivity Trans. / Staff . Month 58% / Yr. compound complexity growth rate EE 5301 - VLSI Design Automation I 2009 1,000,000 100,000,000 1985 Logic transistors per chip (K) 10,000,000 Source: SEMATECH [©Keutzer] 28 Evolution of the EDA industry Results (design productivity) What’s next? Synthesis – Cadence, Synopsys Schematic entry – Daisy, Mentor, Valid Transistor entry – Calma, Computervision, Magic McKinsey S-Curve Fall 2008 EE 5301 - VLSI Design Automation I Effort (EDA tool effort) [©Keutzer] 29 The IC design cycle Fall 2008 EE 5301 - VLSI Design Automation I 30 IC design steps (cont.) Specifications Fall 2008 High-level Description Functional Description Behavioral VHDL, C Structural VHDL EE 5301 - VLSI Design Automation I Figs. [©Sherwani] 31 IC design steps (contd.) High-level Description Specifications Physical Design Placed & Routed Design Packaging Fall 2008 Functional Description Synthesis Technology Mapping Gate-level Design Fabrication EE 5301 - VLSI Design Automation I Logic Description X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani] 32 The big picture: IC design methods Design Methods Cost / Development Time Quality # Companies involved Full Custom Standard Cell Library Design ASIC – Standard Cell Design RTL-Level Design Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 33 Optimization: Levels of abstraction • Algorithmic Reduce fan-out, capacitance Gate duplication, buffer insertion • Layout / Physical-Design Move cells/gates around to shorten wires on critical paths Abut rows to share power / ground lines Fall 2008 EE 5301 - VLSI Design Automation I Level of detail • Gate-level Effectiveness Encoding data, computation scheduling, balancing delays of components, etc. [©Bazargan] 34 Full custom design Structural/RTL Description Component Design Ctrl Mem Reg File Comp. Unit Place & Route I/O ... PLA comp RAM A/D Floorplan [©Sherwani] Layouts [© Prentice Hall] Fall 2008 EE 5301 - VLSI Design Automation I 35 Full custom design example (simplified) I/O Pad Via comp PLA I/O Metal2 Metal1 Macro cell design RAM A/D Glue logic (standard cell design) [©Sherwani] Fall 2008 EE 5301 - VLSI Design Automation I 36 ASIC design HDL Programming Structural/ RTL Description P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0'; Ctrl Mem Reg File Comp. Unit add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o); Mult_i1 <= sum_o(7 downto 0); D C A D C Fall 2008 C C C C B C D C B B Cell library A C EE 5301 - VLSI Design Automation I B D Floorplan [©Sherwani] 37 ASIC (Standard Cell) design example (simplified) VDD Metal1 D GND Metal2 C C C A Cell library B C B A C Cell D D C C C D C B B Placement [©Sherwani] Fall 2008 EE 5301 - VLSI Design Automation I 38 How does this course fit into the curriculum? • VLSI related courses: VLSI CAD EE 5301 VLSI Design EE 5323 VLSI Design Automation I VLSI Design I EE 5302 EE 5324 VLSI Design Automation II VLSI Design II EE 5333 Analog Integrated Circuit Design Fall 2008 EE 5301 - VLSI Design Automation I Others EE 4301 Digital Design With Programmable Logic EE 5329 VLSI Digital Signal Processing Systems EE 5549 Digital Signal Processing Structures for VLSI 39 Course outline • Basic algorithms and complexity theory Circuit representations Classes of problems (P, NP) Classes of algorithms (dynamic programming, network flow, greedy, linear programming, etc.) Graph algorithms Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 40 Course outline (contd.) • Global / detailed routing Maze routing, line-search, Steiner trees, etc. • Partitioning FM, KL, hMetis algorithms • Floorplanning Slicing, non-slicing floorplans Simulated annealing floorplanning algorithms • Placement / Packing Force-directed Simulated annealing Quadratic placement Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 41 To Probe Further... • International Technology Roadmap for Semiconductors (ITRS) http://public.itrs.net/ • SEMATECH http://www.sematech.org/ • Textbook Chapter 1 Fall 2008 EE 5301 - VLSI Design Automation I [©Bazargan] 42