PathFinding Methodology for Interposer and 3D Die Stacking

Sherry Xiaoxia Wu*, Ravi Varadarajan † , Navneet Mohindru † , Durodami Lisk*, Riko Radojcic* *Qualcomm Inc.

† Atrenta Inc.

Outline

 Motivation of PathFinding Methodology  PathFinding Methodology Flow  Demonstrations using an Example  Conclusion

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Typical 3D Design Options

2.5D

Side by side die stacked on a passive interposer that includes TSVs

3D

Memory Multiple DRAM die stacked standalone or on an active interposer

3D

Memory on Logic One or More DRAM die stacked directly on logic die (M-o-L)

3D

Logic on Logic Multiple logic die stacked on top of each other (L-o-L)

3D +

Interposer Mix of side by side and stacked schemes with a passive/active interposer

Courtesy: Si2

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Motivation of PathFinding Methodology

Concept Architecture Concept Technology   Navigating many choices ….

 Cost, power, performance… Co-optimize process & design

Partitioning Choices u-Arch u-Arch Choices PD Choices Choices Choices Choices Orientation Choices TSV TSV Choices Fill Choices Choices Assembly Choices

 Need a structured design exploration methodology     Past experience not applicable to disruptive technologies Not tie to legacy design Quick and flexible High fidelity/low accuracy ???

Form Factor, Yield, Power, Performance

Need methodology to make the selections

PathFinding

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PathFinding Methodology

Design Architecture RTL, Blackbox, Netlist, Top level SDC/DEF/IO Constr, Interfaces, Tier/die config .

Early Design Planning Many more challenges in 3D: - IP/tier assignment - Intra/inter die floorplan - Power & thermal - Timing across dies - TSV & stack configuration - TSV/bump alignment Tier/ Die 1 Physical Units Handoff 1 Logical, Physical, Timing Backend Implementation 1 … Physical Units Handoff N Logical, Physical, Timing … Backend Implementation N Tier/ Die N 5

PathFinding Methodology

Create logical partitions for each die 3D stack XML file Modify partitions Are interconnectivity and TSV reports for all dies acceptable?

Y Commit logical partitions in to 3D physical partitions N Physical prototyping on each die partition Are all dies physically feasible?

Y Backside RDL/ Interposer routing N Is Backside RDL routing/Interposer feasible?

Y 1. Handoff 3D stack XML file with partitions 2. Handoff DEF file for every partition N Modify TSV cluster/locations Modify number of RDL layers/bump locations 6

3D Format - XML

 XML: Ongoing Standardization Two Dies on a Passive Interposer  Interposer and 3D die stacking Two Stacked Dies

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Logic Partition

Block in bottom die Bottom die front-side net TSV Bottom die backside net Bottom die backside ubump Dummy net Top die frontside ubump Top die frontside net Block in top die

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Floorplan Constraints and An Example

TSV/ubmp size, XML Create/mark TSV/ubump clusters Assign TSVs/ubump to clusters Set cluster utilization/aspect ratio FP constraints: guide/region

 Floorplan constraints      Blackbox locations Die utilization: block area/die area Number of TSV clusters: 2, 4, 8 TSV size/pitch/location ubump size/pitch/location

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Floorplan Options for a LoL Case

2 TSV clusters 4 TSV clusters 8 TSV clusters TSV cluster guide T S V     Number of TSV clusters TSV cluster guide TSV cluster aspect ratio TSV pitch TSV aspect ratio

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Frontside Routing Analysis

   Vary bottom and top routing layer Vary macro routing layer Vary routing porosity in a window for PDN/DFT consideration

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Backside Routing Analysis

 Explore BRDL options when TSV and ubumps are not aligned  Vary number of BRDL layers and pitch

Foundry OSAT Above 2 BRDL layers, more complicated and expensive process

ubump group 2

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2.5D Interposer

 Interposer Floorplan, Interposer Routing and Congestion 2 interposer routing layers, pitch = 5um 2 interposer routing layers, pitch = 2um 2 interposer routing layers, pitch = 1um

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Conclusion

 A physical PathFinding methodology for interposer and 3D die stacking is presented  The results show that with this methodology, users are able to explore different process and design options for early estimation of their designs to reduce expensive backend iterations  This methodology is a general flow, it also works for mixed interposer and 3D die stacking

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