Transcript 幻灯片1 - Linac

Overview of SINAP Timing System
Electronics Group
Beam Diagnostics & Control Division
SINAP
Outline
•
•
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•
•
•
v1 timing system structure
v1 hardware
v1 performance
v1 in PLS-II
v2 timing system structure
v2 hardware
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SINAP v1 timing system structure
EVG
OM3 fiber
FANOUT
O/E
is single mode O/E
O/E
is multimode O/E
OM3 fiber
FANOUT
FANOUT
OM3 fiber
OM3 fiber
OM3 fiber
EVR
EVR
EVR
EVR
E/O
TTB
E/O
TTB
Plastic fiiber
Short coaxial
cable
Plastic fiiber
O/E
O/E
Short coaxial
cable
Device
Device
Beam
Devices
O/E
Short coaxial cable
Device
FANOUT
Short coaxial
cable
Beam
Devices
EVR
Multimode
fiber
O/E
O/E
Short coaxial
cable
Device
Device
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Hardware List
• SINAP v1 timing system:
EVG
EVR
FANOUT
TTL VME Transition Board
Plastic fiber VME Transition Board
Multimode fiber O/E
Plastic fiber O/E
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EVG
VME 6U module; A16D32 addressing
Input: 1ch RF clock (0 – 10 dBm)
1ch AC line (3Vp-p typical)
Output: 1ch multi-mode fiber
1ch Sequence RAM trigger
(TTL)
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EVR
VME 6U module; A16D32 addressing
Input: 1ch multi-mode fiber
1ch interlock input (TTL)
Output: 3ch TTL trigger/clock
3ch LVPECL trigger/clock
1ch CML RF recovery clock
2ch Multi-mode fiber trigger
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FANOUT
VME 6U module
Input : 1ch multimode fiber
Output: 12ch multimode fiber
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TTL VME Transition Board
VME transition board
Output: 14ch TTL trigger
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Plastic Fiber VME Transition Board
VME transition board;
Output: 14ch optic trigger
(Agilent HFBR-1528)
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Multi-mode Fiber O/E
Standalone module
Input: 1ch multi-mode fiber
1ch power supply (24V/1A)
Output: 1ch TTL (50ohm)
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Plastic Fiber O/E
Standalone module
Input: 1ch multi-mode fiber
1ch power supply (24V/1A)
Output: 1ch TTL
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Performance Testing
• Stability
coding-decoding error
counter
EVR
EVG
fiber
VME
chassis
RF clock
AC line
EVR output
EVG output
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Performance Testing
• Jitter
EVR TTL output
< 6ps
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Performance Testing
• Jitter
Multi-mode O/E output
< 10ps
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MRF Jitter Performance
•
EVR TTL output > 18ps
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Performance Testing
• Phase Shift
Phase shift with temperature changing (35ps/℃)
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v1 in PLS-II
in LINAC control room
in RF station (EVG)
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v1 in PLS-II
in Klystron & Modulator
in E-gun
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V1 in PLS-II
in Storage Ring
in Kicker station
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SINAP v2 timing system structure
master clock
VME-EVO (EVG)
PLC-EVR
PLC-EVR
VME-EVO (FANOUT)
master clock
VME-EVO (EVG)
VME-EVO
(EVR)
VME-EVO
(EVR)
VME-EVO (FANOUT)
VME-EVE
STD-OE
PLC-EVR
STD-OE
VME-EVE
VME-EVE
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System Design
• Synchronization
Broadcasting mode
Switch
master clock
encoding
divider
8B10B
transistor
event
parallel to
serial
Fiber
reference
clock
receiver
serial to
parallel
clock
extraction
8B10B
recovery
clock
decoding
trigger
divider
clock
EVR
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System Design
• Deterministic Data Transfer
Switching mode
receiver
address &
data
serial to
parallel
8B10B
decoding
transistor
Switch
EVR
address &
data
parallel to
serial
8B10B
encoding
EVR
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System Design
• Frame Format
1 byte for trigger code
1 byte for data frame
1 byte
1 byte
trigger
data frame
K28.5
data frame
K28.5
data frame
K28.5
data frame
trigger
data frame
K28.5
data frame
...
...
The minimum interval of trigger is 8ns (2.5Gbps).
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System Design
• Data Frame Format
1 byte
4 byte
K28.3
address
8 byte
data
4 bytes for address; 8 bytes for data; 1 byte for K28.3
The maximum data transfer rate is 76.9MB/s (2.5Gbps)
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Hardware list
• SINAP v2 timing system:
VME-EVO
VME-EVE
PLC-EVR
STD-OE
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VME-EVO
Configured to EVG, EVR and FANOUT by software
VME 6U module, A16D32 addressing
Input: 1 RF clock (0 – 10dBm)
1 interlock / AC-line (TTL)
1 fiber (SFP module)
Output: 8 fiber (SFP module)
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VME-EVO
• Configure to EVG
uplink
SFP
event FIFO
AC line
RF clock
EVG logic
downlink
Recovery clock
GTX
data FIFO
data Switching
GTX0
GTX1
……
GTX7
SFP0
SFP1
……
SFP7
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VME-EVO
• Configure to FANOUT
Recovery clock
uplink
SFP
GTX
data
switching
downlink
GTX0
GTX1
……
GTX7
SFP0
SFP1
……
SFP7
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VME-EVO
• Configure to EVR
Recovery clock
uplink
SFP
GTX
EVR logic
data logic
GTX0
GTX1
……
GTX7
SFP0
SFP1
……
SFP7
STD-OE
STD-OE
……
STD-OE
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VME-EVE
Configured to EVR
VME 6U module, A16D32 addressing
Input: 1 interlock (TTL)
1 fiber (SFP module)
Output: 8 outputs (TTL)
1 RF recovery clock
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VME-EVE
Recovery clock
uplink
SFP
GTX
EVR logic
data logic
GTX8
GTX0
GTX1
……
GTX7
RF
transformer
fine
delay
fine
delay
……
fine
delay
RF
TTL
TTL
……
TTL
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VME-EVE
• RF recovery clock
event clock
X20
20-bit data
parallel to
serial
GTX
RF
transformer
0x003ff -> event clock
0x03c1f -> 2x event clock
0x18c63 -> 4x event clock
…
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VME-EVE
• RF delay
event clock
OTP(n)
X20
01 falling-edge
parallel to
serial
SRC & SRC_D
dbus(n)
GTX
00 low
10 rising-edge
CML to TTL
11 high
(0,0,0xfffff,0xfffff) -> (0,0x1,0xffffe,0xfffff)
1/20 event clock delay
(Synchronized with RF clock)
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PLC-EVR
Yokogawa FAM3 series, 1-slot module
Input/Output register mode
external 5V/3A DC power supply is required
Input: 1 fiber (SFP module)
Output: 4 outputs (TTL)
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STD-OE
19 inches 1U standard chassis
110/220V 50-60Hz AC power supply
Input: 4 fiber (SFP module)
Output: 4 outputs (TTL)
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Electronics Group, Beam Instrumentation & Control Division