Transcript System clock, bus cycles - Michael J. Geiger, Ph.D.

16.317: Microprocessor
System Design I
Instructor: Dr. Michael Geiger
Spring 2012
Lecture 25: Interfacing (cont.)
Lecture outline
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Announcements/reminders
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Exam 2: next Wednesday
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Lecture outline
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4/13/2015
Once again, allowed 1 8.5” x 11” sheet of notes
I’ll provide you with a list of instructions—will post
to the web page shortly
Practice problems to be posted today
Review: microprocessor interfaces
More on 80386 interfaces
Microprocessors I: Lecture 25
2
Review: 80386 Interfaces (Fig
9.3, p. 376)
A2-A31
DMA
interface
HOLD
HLDA
BE0-BE3
D0-D31
INTR
Interrupt
interface
NMI
W/R
RESET
D/C
M/IO
ADS
PEREQ
Coprocessor
interface
Memory/
IO interface
READY
BUSY
NA
ERROR
LOCK
BS16
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Microprocessors I: Lecture 25
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Additional Memory/IO signals
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LOCK: used in multiprocessor systems
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One processor must claim bus control to
execute transaction
BS16: Change buses to 16-bit mode
Microprocessors I: Lecture 25
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Interrupt Interface
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Signals:
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INTR: interrupt
NMI: Nonmaskable interrupt request
RESET: system reset
Interrupt request/interrupt-acknowledge signal
handshake
IF can disable INTR; NMI cannot be disabled
RESET: initialize internal registers, execute
reset service routine
Microprocessors I: Lecture 25
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DMA and Coprocessor
Interfaces
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DMA
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Coprocessor Interface
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Two signals: HOLD and HLDA
HOLD: bus hold request by DMA controller
80386DX goes into hold state, its bus signals are in
high-impedance state
HLDA: acknowledge from 80386DX to give up
control of bus
PEREQ: coprocessor request for data transfer
BUSY: coprocessor busy; no new calculation
ERROR: coprocessor error occurred
Microprocessors I: Lecture 25
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System clock
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Used to synchronize both internal and external
operations
Generated by external oscillator
Specified in terms of frequency or cycle time
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80386 specifics
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Cycle time = 1 / frequency
E.g. 20 MHz clock  cycle time = 1 / 20x106 = 50 ns
External pin CLK2: clock input
Internal clock: ½ frequency of CLK2
Valid internal frequencies for different 80386
models: 16, 20, 25, 33 MHz
One (internal) cycle: 1 “T state”
Microprocessors I: Lecture 25
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Bus Cycles
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Activity performed when
accessing information in memory
or I/O devices
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Nonpipelined vs pipelined
Nonpipelined bus cycle (Figure
9.10)
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T1 : outputs the address on
address bus, a bus cycle indication
code, control signal
T2: external device accept data, or
provide data to data bus
address is still available on
address bus while data transfer
Each bus cycle has two T states (=
4 CLK2 cycles = 100ns for 20MHz
80386)
Microprocessors I: Lecture 25
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Pipelined Bus Cycle
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Pipelining : Addressing for the next
busy cycle is overlapped with data
transfer of prior bus cycle (Fig 9.11)
Address, bus cycle indication code
and control signals are output in T2 of
the prior cycle, instead of the T1 that
follows
Compare Figure 9.10 with 9.11
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Address-access time: amount of time that
address is stable prior to read/write of data
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Fig. 9.11: Address n becomes valid in T2
of prior bus cycle
Fig. 9.11: while data transfer n occurs,
address n+1 is output on address bus
80386 begins accessing the next storage
location while it is still performing
read/write of data for the previous
location
Pipelined mode has longer effective
address-access time
Given fixed address-access time (equal
speed memory design), pipelined bus
cycle will have a shorter duration than
nonpipelined busy cycle
I.e. pipelined bus can operate at a higher
clock rate than nonpipelined bus cycle.
Microprocessors I: Lecture 25
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Idle State and Wait State
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Idle state
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no need to access memory
Next bus cycle is not
initiated immediately
Wait state (Tw)
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Request by an event in
external hardware
READY signal (input signal)
sampled in the later part of
T2
As long as READY is 1,
read/write data transfer
does not take place and T2
becomes Tw
Bus cycle is not completed
until READY back to 0
Microprocessors I: Lecture 25
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Read Bus Cycle Timing
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Nonpipelined Read Cycle Timing (Figure 9.14)
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T1 and T2, each has two phases (1, 2)
1 of T1 :
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1 of T2 :
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BS16 signal made valid
2 of T2 :
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Address, BE, ADS (signal a valid address is on address
bus)
Bus indication signals (M/IO, D/C, W/R) are made valid
READY input is tested
Data is ready on data bus, if READY = 0
Bus cycle extended to Wait state, if READY = 1
Microprocessors I: Lecture 25
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Microprocessors I: Lecture 25
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Write Bus Cycle Timing
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Nonpipelined Write Cycle Timing (Figure 9.16)
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1 of T1 :
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2 of T1 :
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READY input is tested
Wait State
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BS16 signal made valid
2 of T2 :
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Outputs the data to be written to memory onto data bus
data made valid until the end of the bus cycle
1 of T2 :
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Address, BE, ADS (signal a valid address is on address bus)
Bus indication signals (M/IO, D/C, W/R) are made valid
Inserted with READY input signal
Duration of Tw = T2
Microprocessors I: Lecture 25
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Microprocessors I: Lecture 25
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Next time
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Exam 2 Review
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4/13/2015
Look for review slides soon—be prepared
with questions on Monday!
Microprocessors I: Lecture 25
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