Transcript PPT

Basics of State Machine Design
Finite-State Machines (FSMs)
b Controller
 Want sequential circuit with
x
laser
clk
particular behavior over time
patient
 Example: Laser timer
 Push button: x=1 for 3 clock cycles
 How? Let’s try three flip-flops
 b=1 gets stored in first D flip-flop
 Then 2nd flip-flop on next cycle, then 3rd
flip-flop on next
 OR the three flip-flop outputs, so x should
be 1 for three cycles
b
D
Q
D
Q
D
Q
clk
x
Need a Better Way to Design
Sequential Circuits

Trial and error is not a good design method
 Will we be able to “guess” a circuit that works for other desired
behavior?

How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10
cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input?
 And, a circuit built by guessing may have undesired behavior
 Laser timer: What if press button again while x=1? x then stays one another
3 cycles. Is that what we want?

Combinational circuit design process had two important things:
1. A formal way to describe desired circuit behavior
 Boolean equation, or truth table
2. A well-defined process to convert that behavior to a circuit

We need those things for sequential circuit design
Describing the Behavior of a
Sequential Circuit: FSMOutputs: x
 Finite-State Machine (FSM)
 A way to describe desired
behavior of sequential circuit
 Akin to Boolean equations for
combinational behavior
x=0
clk^
Off
x=1
On
clk^
 List states, and transitions among
states
 Example: Make x change toggle (0 to
1, or 1 to 0) every clock cycle
 Two states: “Off ” (x=0), and “On”
(x=1)
 Transition from Off to On, or On to
Off, on rising clock edge
 Arrow with no starting state points to
initial state (when circuit first starts)
4
FSM Example: 0,1,1,1,repeat
Outputs: x
 Want 0, 1, 1, 1, 0, 1, 1, 1, ...
 Each value for one clock cycle
x=0
Off
clk^
x=1
clk^
On1
 Can describe as FSM
x=1
clk^
On2
x=1
On3
clk^
 Four states
 Transition on rising clock edge
to next state
clk
State Off On1On2On3 Off On1On2 On3 Off
Outputs:
x
5
Extend FSM to Three-Cycle Laser Timer
 Four states
 Wait in “Off ” state while b is 0 (b’)
 When b is 1 (and rising clock
edge), transition to On1
 Sets x=1
 On next two clock edges,
Inputs: b; Outputs: x
x=0
Off
clk^
b’*clk^
b*clk^
x=1 clk^
x=1
On1
On2
clk^
x=1
On3
transition to On2, then On3,
which also set x=1
 So x=1 for three cycles after
button pressed
 Description is explicit about what
happens in “repeat input” case!
6
FSM Simplification: Rising Clock Edges Implicit
Inputs: b; Outputs: x
 Showing rising clock on every
x=0
transition: cluttered
Off
 Make implicit -- assume every edge
has rising clock, even if not shown
clk^
b’ *clk^
b*clk ^
x=1 clk^
x=1
On1
On2
clk^
x=1
On3
 What if we wanted a transition
without a rising edge
 We don’t consider such asynchronous
FSMs -- less common, and advanced
topic
 Only consider synchronous FSMs -rising edge on every transition
Inputs: b; Outputs: x
x=0
Off
b’
b
x=1
x=1
x=1
On1
On2
On3
Note: Transition with no associated condition thus
7 cycle
transistions to next state on next clock
FSM Definition
 FSM consists of
 Set of states
 Ex: {Off, On1, On2, On3}
 Set of inputs, set of outputs
 Ex: Inputs: {b}, Outputs: {x}
 Initial state
 Ex: “Off ”
 Set of transitions
 Describes next states
 Ex: Has 5 transitions
 Set of actions
 Sets outputs while in states
 Ex: x=0, x=1, x=1, and x=1
Inputs: b; Outputs: x
x=0
Off
b’
b
x=1
x=1
x=1
On1
On2
On3
We often draw FSM graphically,
known as state diagram
Can also use table (state table), or
textual languages
8
FSM Example: Secure Car Key
 Many new car keys include tiny
computer chip
 When car starts, car’s computer
(under engine hood) requests
identifier from key
 Key transmits identifier
 4-bits, one bit at a time
 If not, computer shuts off car
 FSM
 Wait until computer requests ID
Inputs: a; Outputs: r
Wait
r=0
a
a’
K1
K2
K3
K4
r=1
r=1
r=0
r=1
(a=1)
 Transmit ID (in this case, 1101)
9
FSM Example: Secure Car Key (cont.)
Inputs: a; Outputs: r
 Nice feature of FSM
 Can evaluate output behavior for
different input sequence
 Timing diagrams show states and
output values for different input
waveforms
clk
Outputs
r
r=0
a
a’
K1
K2
K3
K4
r=1
r=1
r=0
r=1
Q: Determine states and r value for
given input waveform:
clk
Inputs
a
Inputs
a
State
Wait
Wait Wait
K1
K2
K3
K4 Wait Wait
State
Wait Wait
K1
K2
K3
K4 Wait K1
Output
r
10
FSM Example: Code Detector
 Unlock door (u=1) only when buttons
s
Start
pressed in sequence:
u
r
g
b
a
Red
Green
Blue
 start, then red, blue, green, red
 Input from each button: s, r, g, b
 Also, output a indicates that some colored
Door
lock
Code
detector
button is being pressed
Inputs: s,r,g,b,a;
Outputs: u
 FSM
 Wait for start (s=1) in “Wait”
 Once started (“Start”)
 If see red, go to “Red1”
 Then, if see blue, go to “Blue”
 Then, if see green, go to “Green”
 Then, if see red, go to “Red2”

In that state, open the door (u=1)
 Wrong button at any step, return to “Wait”,
without opening door
Wait
u=0 s
Start
u=0
s’
ar’
ab’
ag’
ar’
a’
ar
Red1
u=0
ab
a’
Blue
u=0
ag
a’
Green
ar
a’
u=0
Red2
u=1
Q: Can you trick this FSM to open the door,
without knowing the code?
A: Yes, hold all buttons simultaneously
11
Improve FSM for Code Detector
Wait
u=0 s
Start
u=0
Inputs: s,r,g,b,a;
Outputs: u
s’
ar’ ab’ ag’
ar’
a’
ar
Red1
u=0
ab
a’
Blue
u=0
ag
a’
Green
u=0
ar
a’
Red2
u=1
Note: small problem still
remains; we’ll discuss later
 New transition conditions detect if wrong button pressed, returns to “Wait”
 FSM provides formal, concrete means to accurately define desired behavior
12
Common Pitfalls Regarding Transition
Properties
a
 Only one condition should be
true
b
ab=11 –
next state?
 For all transitions leaving a state
 Else, which one?
 One condition must be true
a
a’b
 For all transitions leaving a state
 Else, where go?
13
Verifying Correct Transition Properties
 Can verify using Boolean algebra
 Only one condition true: AND of each condition pair (for
transitions leaving a state) should equal 0  proves pair can
never simultaneously be true
 One condition true: OR of all conditions of transitions
leaving a state) should equal 1  proves at least one
condition must be true
 Example
a
a’b
Answer:
a * a’b
= (a * a’) * b
=0*b
=0
OK!
a + a’b
= a*(1+b) + a’b
= a + ab + a’b
= a + (a+a’)b
=a+b
Fails! Might not
be 1 (i.e., a=0,
b=0)
Q: For shown transitions, prove whether:
* Only one condition true (AND of each pair is always 0)
* One condition true (OR of all transitions is always 1)
14
Evidence that Pitfall is Common
 Recall code detector FSM
 We “fixed” a problem with the
transition conditions
 Do the transitions obey the two
required transition properties?
 Consider transitions of state Start,
and the “only one true” property
ar * a’
a’ * a(r’+b+g)
= (a*a’)r = 0*r
=0
=0
Wait
u=0 s
Start
u=0 ar
Red1
u=0
s’
a’
ab
a’
Blue
u=0
ag
a’
Green
u=0
ar
a’
Red2
u=1
ar * a(r’+b+g)
Intuitively: press red and blue
= (a’*a)*(r’+b+g) = 0*(r’+b+g)
buttons at same time: conditions
= (a*a)*r*(r’+b+g) = a*r*(r’+b+g)
ar, and a(r’+b+g) will both be
true. Which one should be
= arr’+arb+arg
taken?
= 0 + arb+arg
Q: How to solve?
= arb + arg
= ar(b+g)
A: ar should be arb’g’
Fails! Means that two of Start’s (likewise for ab, ag, ar)
transitions could be true
Note: As evidence the pitfall is common, the author of
this example admitted the mistake was not intentional
– A reviewer of his book caught it. 15
Design Process using FSMs
1.
Determine what needs to be remembered

What will be stored in memory?
2.
Encode the inputs and outputs in binary (if necessary)
3.
Construct a state diagram of the behavior of the desired device

Optionally – minimize the number of states needed
4.
Assign each state a binary number (code)
5.
Choose a flip-flop type to use

6.
Derive the flip-flop input maps
Produce the combinational logic equations and draw the
schematic from them
Example Design 1

Design a circuit that has input w and output z


All changes are on the positive edge of the clock
The output z = 1 only if w = 1 for both of the two
preceding clock cycles

Note: z does not depend on the current w

Sample timing:
cycle:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
0
1
0
0
1
1
0
Steps 1 & 2

What needs to be remembered?

Previous two input values
If both are 1, then z = 1 at next positive clock edge

Possible “states” are





A: seen 10 or 00  output z = 0
B: seen 01  output z = 0, but we’re almost there!
C: seen 11  output z = 1
Step 2 is trivial since the inputs and outputs are already in
binary
Step 3

Corresponding state diagram
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
Step 4

Assign binary numbers to states
Since there are 3 states, we need 2 bits
2 bits  2 flip-flops



Many assignments are possible
One obvious one is to use:




A: 00 (or 10 instead)
B: 01
C: 11
This choice may not be “optimal”


State assignment is a complex topic all to itself!
State Diagram / State Table
w = 1
w = 0
00z = 0
01z = 0
w = 0
w = 1
w = 0
11z = 1
w = 1
next state
current state
w=0
w=1
Q2 Q1
Q2 Q1
Q2 Q1
z
0
0
0 0
0 1
0
0
1
0 0
1 1
0
1
0
x x
x x
x
1
1
0 0
1 1
1
General Form of Design

A 2 flip-flop design now has the form
w
Combinational
circuit
Clock
Combinational
circuit
z
Step 5

Choose a flip-flop type
The choice DOES impact the cost of the circuit
The choice need not be the same for each flip-flop



Regardless of type of flip-flop chosen
Need to derive combinational logic for each flip-flop input in
terms of w and current state


Need to derive combinational logic for z in terms of w and
current state



Use K-maps for minimum SOP for each
Use K-map for this also
Suppose we choose D type …
D Flip-Flop Input Maps
next state
current state
w=0
w=1
Q2 Q1
Q2 Q1
Q2 Q1
z
0
0
0 0
0 1
0
0
1
0 0
1 1
0
1
0
x x
x x
x
1
1
0 0
1 1
1
Q2Q1
w
00
01
11
10
0
0
0
1
x
1
0
0
1
x
z = Q2
Q2Q1
w
00
01
11
10
0
0
0
0
x
1
0
1
1
x
D2 = w Q1
Q2Q1
w
00
01
11
10
0
0
0
0
x
1
1
1
1
x
D1 = w
D Flip-Flop Implementation
A Different State Assignment
w = 1
w = 0
00z = 0
01z = 0
Different state assignments
can have quite an effect on
the resulting
implementation cost
w = 0
w = 1
w = 0
10z = 1
w = 1
next state
current state
w=0
w=1
Q2 Q1
Q2 Q1
Q2 Q1
z
0
0
0 0
0 1
0
0
1
0 0
1 0
0
1
0
0 0
1 0
1
1
1
x x
x x
x
Resulting D Flip-Flop Input Maps
Q2Q1
w
next state
current state
Q2 Q1
w=0
w=1
Q2 Q1
Q2 Q1
z
0
0
0 0
0 1
0
0
1
0 0
1 0
0
1
0
0 0
1 0
1
1
1
x x
x x
x
00
01
11
10
0
0
0
x
0
1
0
1
x
1
D2 = w Q1 + w Q2
= w (Q1+Q2)
Q2Q1
w
00
01
11
10
0
0
0
x
0
1
1
0
x
0
D1 = w Q2' Q1'
New D Flip-Flop Implementation

Cost increases due to extra combinational logic
Moore FSM

A finite state machine in which the outputs do not directly
depend on the input variables is called a Moore machine


Outputs are usually associated with the state, since they do not
depend on the input values
Also note that the choice of flip-flop does not change the
output logic

Only one K-map need be done regardless of the choice of flipflop type
Mealy FSM

If the output does depend on the input, then the machine
is a Mealy machine

This is more general than a Moore machine
If required, then Mealy machine.
If not required, then Moore machine.
W
Clock
Combinational
circuit
Flip-flops
Q
Combinational
circuit
Z
Mealy Design Example 1

Redesign the “sequence of two 1's” example so that the
output z = 1 in the same cycle as the second 1

Compare the Moore and Mealy model outputs:

Moore model
cycle:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
0
1
0
0
1
1
0

Mealy model
cycle:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
1
0
0
1
1
0
0
Mealy FSM

Mealy machines have outputs associated with the
transitions

Moore machines have outputs associated with the states –
that's why the output does not depend on the input
w = 1 z = 0
w = 0 z = 0
A
B
w = 0 z = 0
w = 1 z = 1
State Table

Only 2 states needed, so only 1 flip-flop required


State A: 0
State B: 1
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
next state
output
current
state
w=0
w=1
w=0
w=1
Q
Q
Q
z
z
0
0
1
0
0
1
0
1
0
1
Output Logic
The outputs still do not depend on the choice of flipflops, but they do depend on the inputs

next state
output
current
state
w=0
w=1
w=0
w=1
Q
Q
Q
z
z
0
0
1
0
0
1
0
1
0
1
Q
Q
0
1
0
0
0
1
1
1
w
0
1
0
0
0
1
0
1
w
z=wQ
D=w
D Flip-Flop Implementation
z = 1since w = 1 on both sides
of posedge clock
z = 0 since w = 0 even though no
posedge clock has occurred –
level sensitive output!
Converting Mealy to Moore

Mealy machines often require fewer flip-flops and/or less
combinational logic


But output is level sensitive
To modify a Mealy design to behave like a Moore design,
just insert a D flip-flop to synchronize the output
Modified Mealy  Moore Design
Verilog for FSM
CAD Automation of Design

As usual, CAD tools can automate much of the design
process, but not all of it

Deriving the state diagram is still an art and requires
human effort

Obviously, we could design everything and then just
implement the design using schematic capture

Or … we can use Verilog to represent the FSM and then
allow the CAD tool to convert that FSM into an
implementation

Automates state assignment, flip-flop selection, logic
minimization, and target device implementation
Repeat of Design Principles

The design process is about determining the two
combinational circuits below and linking them by flipflops
next state
current state
Y
y
w
Combinational
circuit
Combinational
circuit
Y
Clock
y
z
Verilog for Moore Style FSMs
ResetN=0
state transition logic
w=1
w=0
A z = 0
B z = 0
w=0
w=1
w=0
flip-flops required
Cz = 1
w=1
z = 1 if previous two consecutive w inputs
were 1 – Moore machine style
output logic
Coding Style

The Verilog coding style is very important
You need to code in such a way that the Verilog compiler
can effectively use FSM techniques to create good designs
Use of the parameter statement or `define is a must for
detecting FSM specifications



Also, note that testing whether your design is correct can
be a challenge
The two faces of CAD: synthesis and verification
How much testing is enough testing?
What does “testing” look like?




Use input test vectors and check the outputs for correctness
An Alternate Moore Coding Style

Same example,
but only one
always block

Both approaches
work well in CAD
tools
Register Swap Controller
A
Enable=0
Enable=1
B
Rout2=1
Rin3=1
Enable=0,1
C
Rout1=1
Rin2=1
Enable=0,1
D
Rout3=1
Rin1=1
Done=1
Enable=0,1
Bus Controller

Bus controller receives requests for access to a shared bus


Controller grants request via a one-asserted output


4 separate grant lines G0, G1, G2, G3: one asserted
Priority given to lowest numbered device


Requests on separate lines: R0, R1, R2, R3
device 0 > device 1 > device 2 > device 3
No interrupts allowed

Device uses bus until it relinquishes it
Bus Controller FSM

5 states





A: bus idle
B: device 0 using the bus
C: device 1 using the bus
D: device 2 using the bus
E: device 3 using the bus
R[0:3] = 0000
0000
A / G[0:3] = 0000
A/0000
notation used
Complete FSM for Bus Controller
0000
A/0000
1xxx
01xx
0xxx
x0xx
001x
C/0100
B/1000
1xxx
xxx0
x1xx
xx0x 0001
E/0001
D/0010
xx1x
xxx1
Idle Cycle in Design

Note that when a device de-asserts its request line, a
cycle is wasted in returning to the idle state (A)

If another request were pending at that time, why can't
the bus controller simply transfer control to that device?


It can, but we need a more complex FSM for that
Same number of states, just many more transitions
Permitting Preemption

Once a device is granted access, it controls the bus until it
relinquishes control


Can we change the behavior so that high priority devices
can preempt lower priority devices and take over control?


Higher priority devices must wait
Of course!
Can we combine preemption with the removal of the idle
cycle?

Yes ….
Complete FSM for Bus Controller
0000
A/0000
1xxx
01xx
0xxx
x0xx
001x
C/0100
B/1000
1xxx
xxx0
x1xx
xx0x 0001
E/0001
D/0010
xx1x
xxx1
Preemption Without the Idle Cycle
0000
A/0000
1xxx
01xx
0000
0000
0000
001x
0000 0001
01xx
B/1000
1xxx
001x
C/0100
D/0010
001x
01xx
1xxx
01xx
0001
01xx
0001
1xxx
E/0001
0001
1xxx
001x
001x
0001
Vending Machine

Deliver one pack of gum for 15 cents


One slot for all coins



So it’s cheap gum. So what! Maybe it's just one stick.
Can detect nickels and dimes separately
We’ll assume that you can’t insert BOTH a nickel and a dime in the
same clock cycle
No change given!
nickel detected
dime detected
clock
vending
machine
controller
release gum
Verilog for Mealy Style FSMs
w = 1 z = 0
w = 0 z = 0
A
B
w = 0 z = 0
w = 1 z = 1
Mealy outputs are associated
with the transitions