Transcript CPLD 講義

CPLD 簡介
2011/01/16 v1.0
By Johnson Chang
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What is CPLD
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Complex Programmable Logic Device
Your own ASIC
( Application Specified Integrated Circuit)
Logic Design  Implementation with
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Standard TTL / COMS
CPLD / FPGA
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Why CPLD?
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Large Digital Logic Design is possible
Minimize PCB size
High Speed ( 3/4/5 nS vs 18nS )
Security
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CPLD
TTL
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How to design CPLD
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Xilinx / Altera
Altera Quartus / Maxplux II (phase out)
Block Diagram Schematic ( bdf ) / VHDL /
Verilog
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Study Sequence
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Quartus Installation
Example Demonstration
Introduction of Terasic CPLD Kit
Programming Example
Implement 74LS138 with 3 SW input
Implement 74LS138 with 2Hz input
Design a 7-Segment decoder
Design a 4*7 7-Segment decoder
Design a 4-byte RAM
Design a counter 1,3,5,7,1,3,5,7、、、
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Learning Material
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陳慶逸的教學網站
CPLD/FPGA數位電路教學與設計資源
張正賢教學網站
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