Transcript 1 - NTU EDA
Novel Wire Density Driven Full-Chip
Routing for CMP Variation Control
Huang-Yu Chen†, Szu-Jui Chou†,
Sheng-Lung Wang‡, and Yao-Wen Chang†
†National Taiwan University, Taiwan
‡Synopsys, Inc, Taiwan
Outline
CMP Introduction
Previous Work
Wire-Density Driven Two-Pass Top-Down Routing
Experimental Results
Conclusion
2
Outline
CMP Introduction
Previous Work
Wire-Density Driven Two-Pass Top-Down Routing
Experimental Results
Conclusion
3
Cu Damascene Process
The Cu metallization (Damascene) contains two main
steps: electroplating (ECP) and chemical-mechanical
polishing (CMP)
ECP: deposits Cu on the trenches
CMP: removes Cu that overfills the trenches
Great interconnect performance and systematic yield
loss are observed after CMP
Open trenches
ECP
CMP
4
CMP Process
CMP contains both chemical and mechanical parts
Chemically: abrasive slurry dissolves the wafer layer
Mechanically: a dynamic polishing head presses pad and wafer
Polishing head
Slurry
Polishing pad
Wafer
Schematic diagram of CMP polisher
5
Layout-Dependent Thickness Variations
Post-CMP topography strongly depends on underlying
layout pattern density
slurry
polishing pad
metal
dielectric
Oxide
Pre-CMP
Post-CMP
Uneven layout density leads to metal dishing and
dielectric erosion after CMP
dishing
erosion
dielectric
metal
6
Layout Pattern Density Control
Foundries have set density rules and filled dummy
features to improve CMP quality
wire
dummy
Disadvantages of dummy fills:
1. Changes coupling capacitance of interconnects
2. Leads to explosion of mask data, putting heavy burdens to
following time-consuming RETs
Routing considering uniform wire density helps control
the layout pattern density
Avoid aggressive post-routing dummy fills
7
Outline
CMP Introduction
Previous Work
Wire-Density Driven Two-Pass Top-Down Routing
Experimental Results
Conclusion
8
Minimum Pin Density Global Routing
Cho et al. [ICCAD’06] selected paths with minimum pin
density to reduce maximum wire density in global tiles
Paths with lower pin density tend to have lower wire
density and can get much benefit from optimization
p1
T
p1
S
p2
S
2 possible 1-bend ST paths
T
Select
p1 withdensity
lower
Path
a path
with lower
pin density
9
Wire Density-Driven Cost Function
Li et al. [TCAD’07] set the cost function of a global tile t
to guide a wire density-driven global router:
1
[( ct / )dt ]
cost(t ) 2
1
ct
: capacity of t
dt
: demand of t
cost(t )
dt (ct / )
dt (ct / )
1
ct
dt
: parameter of target density (=4 for 25% target density)
10
Limitations
Both approaches only consider the wire density inside a
routing tile
It may incur larger inter-tile density difference
results in irregular post-CMP thickness variations
Density = 0.4 Density = 0.1
Post-CMP Thickness
Need to minimize the density
difference among global tiles
11
Outline
CMP Introduction
Previous Work
Wire-Density Driven Two-Pass Top-Down Routing
Experimental Results
Conclusion
12
Multilevel Routing
A modern chip may contain billions of transistors and
millions of nets
Multilevel routing has been proposed to handle largescale designs
To-be-routed net
‧global routing
‧detailed routing
Already-routed net
‧failed nets rerouting
‧refinement
coarsening
uncoarsening
Λ-shaped multilevel routing
13
Two-Pass Top-Down Routing Framework
To-be-routed net
Already-routed net
G2
G2
uncoarsening
uncoarsening
G1
G1
G0
G0
high
low
Prerouting Stage
Voronoi-diagram
based density
critical area
analysis (CAA)
1st Pass Stage
Intermediate Stage
PlanarizationDensity-driven layer
aware top-down assignment and
global routing
Delaunay-triangulation
track assignment
2nd Pass Stage
Top-down
detailed routing
and refinement
14
Top-Down Routing Approach
1. Planarity is a long-range effect
2. Longer nets shall be planned first
greater impacts/determination for density
usually hard to predict paths
G2
G1
G0
3. Bottom-up routing easily falls into local optima
over density may occur among subregions
?
?
?
?
Bottom-up routing
Over density
among subregions
15
Density Analysis Prerouting
To-be-routed net
Already-routed net
G2
G2
uncoarsening
uncoarsening
G1
G1
G0
G0
high
low
Prerouting Stage
Voronoi-diagram
based density
critical area
analysis (CAA)
1st Pass Stage
Intermediate Stage
PlanarizationDensity-driven layer
aware top-down assignment and
global routing
Delaunay-triangulation
track assignment
2nd Pass Stage
Top-down
detailed routing
and refinement
16
Density Critical Area Analysis (CAA)
Performs density analysis to guide following routing
Given a routing instance, we predict density hot spots
based on the pin distribution by Voronoi diagrams
17
Voronoi Diagram
The Voronoi diagram of a point set decomposes space
into non-overlapping Voronoi cells
If a point q lies in the Voronoi cell of p, then q would be close to p
than other points
p
q
18
Observation of Voronoi Diagrams
Non-uniform distribution leads to large area variation
among Voronoi cells
Non-uniform distribution
Uniform distribution
19
Density Hot Spots Identification
If the Voronoi cell of a pin has more adjacent cells,
density hot spots may occur around it
Define pin density of a pin p as # of adjacent Voronoi
cells completely sitting inside a range from p
pin density = 3
p
20
Global Tile Predicted Density
Map pin density to global tiles to guide global routing
The predicted density of a global tile t:
= max{ pin density | pin locates within t }
1
2
2
1
2
1
2
2
0
3
1
0
1
0
1
3
2
1
1
1
Pin density
Predicted density of global tile
21
1st Pass Top-Down Global Routing
To-be-routed net
Already-routed net
G2
G2
uncoarsening
uncoarsening
G1
G1
G0
G0
high
low
Prerouting Stage
Voronoi-diagram
based density
critical area
analysis (CAA)
1st Pass Stage
Intermediate Stage
PlanarizationDensity-driven layer
aware top-down assignment and
global routing
Delaunay-triangulation
track assignment
2nd Pass Stage
Top-down
detailed routing
and refinement
22
Planarization-Aware Global Routing
Objectives:
1. Encourage each global tile to satisfy density upper- and
lower-bound rules
2. Minimize the density difference among global tiles
0.1
0.3
0.2
0.2
0.5
0.1
0.4
0.2
0.3
Density = 0.5 Density = 0.1
Wire density map
Density = 0.2
Post-CMP Thickness
23
Planarization-Aware Cost Function
Planarization-aware cost of global tile t with density dt:
dt
dt (2 1) (dt dt )2
if dt upper bound
if lower bound dt upper bound
if dt lower bound
: predicted density of t (prerouting density CAA)
: positive penalty (> 0)
: negative reward (< 0)
dt : average density of tiles around t
: user-define parameter
24
Intermediate Layer/Track Assignment
To-be-routed net
Already-routed net
G2
G2
uncoarsening
uncoarsening
G1
G1
G0
G0
high
low
Prerouting Stage
Voronoi-diagram
based density
critical area
analysis (CAA)
1st Pass Stage
Intermediate Stage
PlanarizationDensity-driven layer
aware top-down assignment and
global routing
Delaunay-triangulation
track assignment
2nd Pass Stage
Top-down
detailed routing
and refinement
25
Density-Driven Layer Assignment
Goal: to evenly distribute segments to layers
Minimizes the panel density while balancing the local
density of each layer
local density: # of segments and obstacles in a column
panel density: maximum local density among all columns
s1
s4
s6
s2
s5
s3
Chip layout
(aerial view)
1
2
3
4
Column c1
Local density 1
Segment
o2
o1
c2
c3
c4
c5
c6
c7
c8
c9
2
3
2
2
2
3
2
4
Layer 1 obstacle
c10 c11
4
Layer 3 obstacle
2
26
Density-Driven Layer Partitioning
Builds horizontal constraint graph HCG(V,E)
Node: segment and obstacle
Cost of an edge (vi, vj): maximum local density of overlapping
columns between vi and vj
Partitions layer groups by max-cut, k-coloring algorithms
s1
s4
s6
s2
s5
s3
1
2
3
4
Column c1
Local density 1
s6
o2
c3
c4
c5
c6
c7
c8
c9
2
3
2
2
2
3
2
4
4
1
4
4
o1 3
c10 c11
1
1
4
c2
s2
3
2
4
o1
s1
3
3
3
4
3
s5
1
4
3
3
o2
s3
3
s4
2
27
Minimum-Impact Repair Procedure
For the fixed-layer obstacle which is not assigned to the
correct layer
Exchanges its layer with the layer of a connected
segment whose edge cost is the maximum
s6
s1
s2
s1
s2
1
1
1
1
2
1
4
o1 3
3
3
o2
s6
3
3
o2
o1 1
1
s3
3
4
1
3
s5
4
3
s4
3
s3
3
s5
3
s4
Exchange layer of obstacle O1 with that of S6
28
Density-Driven Layer Assignment Result
s1
s4
s6
s2
s5
s3
1
2
3
4
Segment
o2
o1
Column c1
Local density 1
c2
c3
c4
c5
c6
c7
c8
c9
2
3
2
2
2
3
2
4
s1
1
2
3
4
1
2
3
4
s3
o1
s2
mn
c1
c2
c3
c4
c5
c6
c7
c8
c9
ity
1
1
2
1
1
1
1
1
2
Layer 1
c10
c10 c11
4
Layer 3 obstacle
2
s6
o2
s4
Segment
s5
cColumn
c1 1 cobstacle
c3
11
2
Layer
2
0density
Local
Layer 1 obstacle
0
1
1
c4
c5
c6
c7
c8
c9
c10
c11
1
1
1
2
1
2
2
2
Layer 3
29
Density-Driven Track Assignment
Goal: to keep segments spatially separated in a panel
Uses good properties of Delaunay Triangulation (DT)
Represents each segment by three points, two end points and
one center point, and analyzes the DT
Non-uniform segment distribution large area difference
among triangles in DT
Non-uniform distribution
Uniform distribution
30
Artificial Segment
Model the density distribution of each neighboring panel
into an artificial segment lying on the boundary
Au
Ab
u1
1
2
3
4
1
2
A
3
4
1
2
3
4
Length: the average occupied length per track
Center: the center of gravity of all segments and obstacles
u3
u2
u4
s1
s3
o1
s2
Au
1
2
A
3
4
b1
b3
b2
Segment
Ab
u1
1
2
3
4
1
2
3
4
Artificial segment
u3
u2
u4
su
s1
s3
o1
s2
b1
sb
b3
b2
Layer 1 obstacle
31
Delaunay-Triangulation Track Assignment
Define flexibility of a segment si, ( si ) ti
ti: number of assignable tracks for si
li: length of si
1
li
Insert segments in the non-decreasing order of flexibility
Each segment is assigned to the track that minimizes the
area difference among all triangles of DT
s1
1
2
3
4
s2
s3
su
ξ(s1) = 4+1/2 = 4.5
o1
sb
ξ(s2) = 4+1/1 = 5
ξ(s3) = 3+1/8 = 3.125
32
A Density-Driven Track Assignment Example
1
2
3
4
s3
1
2
3
4
s3
ξ(s1) = 4.5
o1
o1
ξ(s1) = 4.5
s2
su
1
2
3
4
ξ(s2) = 4
Segment
s3
s1
Artificial segment
o1
s2
sb
Layer 1 obstacle
33
Outline
CMP Introduction
Previous Work
Wire-Density Driven Two-Pass Top-Down Routing
Experimental Results
Conclusion
34
Experimental Setting
C++ language with LEDA library on a 1.2 GHz Sun
Blade-2000 with 8GB memory
Compared our two-pass, top-down routing system (TTR)
with MROR [Li et al., TCAD’07]
Λ-shaped multilevel router considering balanced density
Compared the density-CAA guided global routing of TTR
with CMP-aware minimum pin-density global routing
[Cho et al., ICCAD’06]
Minimum pin-density global routing + TTR detailed routing
35
Routing Benchmarks
Academic: eleven MCNC benchmarks
Industrial: five Faraday benchmarks
Circuit #Layer #Connection
#Pin
Mcc1
4
1693
3101
Mcc2
4
7541
25024
Struct
3
3551
5471
Primary1
3
2037
2941
DMA
6
36162
73982
Primary2
3
8197
11226
DSP1
6
63495
144872
S5378
3
3124
4818
DSP2
6
36686
144703
S9234
3
2774
4260
RISC1
6
95106
196677
RISC2
6
95099
196670
S13207
3
6995
10776
S15850
3
8321
12793
S38417
3
21035
32344
S38584
3
28177
42931
Circuit #Layer #Connection
#Pin
Faraday benchmarks
MCNC benchmarks
36
Comparison Metric
Comparison is based on the same metric used in the
work of MROR [TCAD’07]
#Netmax: maximum # of nets crossing a tile
#Netavg_h: average # of nets horizontally crossing a tile
#Netavg_v: average # of nets vertically crossing a tile
σh: standard deviation of # of nets horizontally crossing a tile
σv: standard deviation of # of nets vertically crossing a tile
Reflects the wire density distribution for a routing result
37
Experimental Results (MCNC)
All three routers achieved 100% routability
TTR reduced
#Netmax by 43% than TCAD’07 and 11% than ICCAD’06
#Netavg_v by 34% than TCAD’07 and 5% than ICCAD’06
#Netavg_h by 36% than TCAD’07 and 11% than ICCAD’06
MROR (TCAD'07)
Circuit
#Netmax #Netavg_v #Netavg_h
GR (ICCAD'06) + TTR framework
Time
(sec)
#Netmax #Netavg_v #Netavg_h
Time
(sec)
TTR (Ours)
#Netmax #Netavg_v #Netavg_h
Time
(sec)
Mcc1
45
9.9
11.3
77.4
41
10.3
11.1
36.1
30
10.3
11.0
33.4
Mcc2
96
18.7
20.9
2714.9
119
20.6
22.2
798.0
87
20.5
22.2
645.0
Struct
7
1.4
1.4
61.4
5
1.2
0.8
66.8
6
1.1
0.8
58.2
Primary1
15
0.7
0.6
69.1
12
0.8
0.7
27.0
6
0.7
0.3
24.3
Primary2
25
2.1
1.9
322.2
22
2.5
1.9
144.0
8
1.8
0.9
131.0
S5378
15
4.4
3.5
4.5
8
2.5
2.4
8.1
9
2.5
2.4
8.2
S9234
14
4.0
2.6
3.2
7
1.7
1.6
5.2
9
1.7
1.6
5.4
S13207
27
9.3
5.9
15.8
13
3.4
3.0
24.8
11
3.3
3.0
24.2
S15850
26
10.3
7.4
23.8
12
4.0
3.8
34.2
13
3.9
3.8
33.5
S38417
23
7.3
4.3
54.2
10
3.0
2.4
62.5
11
2.9
2.4
62.4
S38584
29
9.1
5.8
137.7
16
3.3
3.1
112.0
15
3.3
3.1
112.0
Comp.
1.00
1.00
1.00
1.00
0.68
0.71
0.75
1.01
0.57
0.66
0.64
0.98
38
Vertical Wire Crossing of S13207
30
25
MROR
[TCAD’07]
20
15
10
5
0
30
25
GR [ICCAD’06]
+TTR framework
20
15
10
5
0
30
25
TTR (Ours)
20
15
10
5
0
39
Experimental Results (Faraday)
MROR [TCAD’07] cannot run designs where pins are
distributed between layers 1 and 3
TTR reduced
#Netmax by 25% than ICCAD’06
#Netavg_v by 2% than ICCAD’06
#Netavg_h by 2% than ICCAD’06
GR (ICCAD'06) + TTR framework
Circuit
DMA
Rout. #Netmax #Netavg_v #Netavg_h
σv
σh
TTR (Ours)
Time
(sec)
Rout. #Netmax #Netavg_v #Netavg_h
σv
σh
Time
(sec)
99.19%
14
3.14
2.77
1.70 1.77
48.8
99.29%
10
3.08
2.70
1.75
1.64
47.0
DSP1 99.11%
11
2.91
2.50
1.95 1.89
124.2
99.18%
10
2.85
2.44
2.24
1.95
117.3
DSP2 99.10%
14
2.78
2.78
1.71 1.92
87.2
99.06%
10
2.72
2.70
1.90
1.91
82.3
RISC1 99.16%
21
3.63
3.79
2.95 3.78
355.3
99.16%
17
3.59
3.73
3.08
3.29
333.4
RISC2 99.23%
21
3.64
3.70
2.55 3.08
297.4
99.19%
13
3.59
3.62
2.77
2.89
280.0
Comp. 99.16%
1.00
1.00
1.00
1.00 1.00
1.00
99.16%
0.75
0.98
0.98
1.08
0.95
0.95
40
Horizontal Wire Crossing of RISC1
GR [ICCAD’06]
+TTR detailed routing
TTR (Ours)
41
Outline
CMP Introduction
Previous Work
Wire-Density Driven Two-Pass Top-Down Routing
Experimental Results
Conclusion
42
Conclusion
Proposed a new full-chip density-driven routing system
for CMP variation control
1. Voronoi-diagram based density CAA prerouting
2. Planarization-aware top-down global routing
3. Density-driven layer assignment + Delaunay-triangulation
based track assignment
4. Top-down detailed routing
Reduced 43% and 11% maximum wire crossing on
density tiles and achieved more balanced wire
distribution than state-of-the-art previous works
43
Q&A
Thanks for your attention!
44