STAR Pixel Detector

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Transcript STAR Pixel Detector

STAR
STAR Pixel Detector
A MAPS based vertex detector for STAR
Short description of the detector and why we need test beam
LBNL
Leo Greiner, Eric Anderssen, Howard Matis,
Thorsten Stezelberger, Joe Silber, Xiangming
Sun, Michal Szelezniak, Chinh Vu,
Howard Wieman
UTA
Jo Schambach
IPHC Strasburg
Marc Winter CMOS group
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Vertex Detector Motivation
Direct Topological
reconstruction of Charm
Detect charm decays with
small c, including D0  K 
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Method: Resolve displaced
vertices (100-150 microns)
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Inner Detector Upgrades
STAR
TPC – Time Projection Chamber
(main tracking detector in STAR)
HFT – Heavy Flavor Tracker
 SSD – Silicon Strip Detector
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IST – Inner Silicon Tracker
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r = 22 cm
r = 14 cm
PXL – Pixel Detector
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r = 2.5, 8 cm
We track inward from the TPC with graded resolution:
TPC
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~1mm
SSD
~300µm
IST
~250µm
PXL
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<30µm
vertex
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PXL Detector Mechanical Design
Cabling and cooling
infrastructure
Mechanical support with kinematic
mounts (insertion side)
carbon fiber sector tubes (~ 200um
thick)
Insertion from one side
2 layers
5 sectors / half (10 sectors total)
4 ladders/sector
Ladder with 10 MAPS sensors
(~ 2×2 cm each)
RDO
buffers/
drivers
MAPS
4-layer kapton
cable with
aluminium
traces
Aluminum
conductor
Ladder
Flex Cable
20 cm
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Detector Characteristics
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Pointing resolution
(12  19GeV/pc) m
Layers
Layer 1 at 2.5 cm radius
Layer 2 at 8 cm radius
Pixel size
20.7 m X 20.7 m
Hit resolution
6 m
Position stability
6 m rms (20 m envelope)
Radiation length per layer
X/X0 = 0.37%
Number of pixels
356 M
Integration time (affects
pileup)
185.6 s
Radiation requirement
20 to 90 kRad
2*1011 to 1012 1MeV n eq/cm2
Rapid detector
replacement
< 8 Hours
356 M pixels on ~0.16 m2 of Silicon
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Test Beam use
MAPS sensor characteristics:
Column parallel RDO with in-chip CDS, discriminators and zero-suppression.
2011
• Characterize pre-production prototype sensors in a
beam telescope configuration to check efficiency and
resolution as a function of bias and discriminator settings
for MIPS.
2012
• Prototype sector and detector tests. Test tracking with
MIPs through 4 layers of detector. Track stability with
cooling air flowing.
2013
• Production sector and detector tests. As above.
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Parameters required for Beam Tests
Beam parameters
Value
Particle Type
MIP
Energy
MIP
Rep Rate
NA
Charge per pulse
Low / diffuse 1k / spill
Energy Spread
NA
Bunch length rms
NA
Beam spot size, x-y
Comments
MIPs
Minimum 3cm x 3cm
Others (emittance, …)
Logistics
Requirements
Space requirements (H x W x L)
2011 – 3’ x 3’ x 1’ for telescope
2012/2013 – 2’ x 6’ x 2’ + blower
Duration of Test and Shift
Utilization
1 shift – setup
3 shifts data taking
Desired Calendar Dates
Spring/summer 2011, 2012, 2013
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Beam Test Packages
Beam Telescope
Sector and detector
apparatus with air cooling
housing and blower
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backup
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PXL Detector Basic Unit (RDO)
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6 m (24 AWG TP)
2 m (42 AWG TP)
Clk, config, data
Clk, config, data, power
Mass Termination Board + latch-up
protected power daughter-card
100 m (fiber optic)
PXL built events
RDO PC with DDL link to RDO board
RDO motherboard
w/ Xilinx Virtex-5 FPGA
Highly parallel system
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4 ladders per sector
1 Mass Termination Board (MTB) per sector
1 sector per RDO board
10 RDO boards in the PXL system
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Monolithic Active Pixel Sensors
MAPS pixel cross-section (not to scale)
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Standard commercial CMOS technology
Room temperature operation
Sensor and signal processing are integrated in the same silicon wafer
Signal is created in the low-doped epitaxial layer (typically ~10-15 μm) → MIP
signal is limited to <1000 electrons
Charge collection is mainly through thermal diffusion (~100 ns), reflective
boundaries at p-well and substrate → cluster size is about ~10 pixels (20-30 μm
pitch)
100% fill-factor
Fast readout
Proven thinning to 50 micron
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Mimosa-26 Efficiency vs. threshold
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Mimosa-26HR eff vs. fake hit rate
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RDO System Design – Physical Layout
Sensors / Ladders / Sectors
(interaction point)
1-2 m
Low mass twisted pair
Platform
Power
Supplies
Control
PCs
30 m
LU Protected Regulators,
Mass cable termination
6 m - twisted pair
30 m
30 m
RDO Boards
(Low Rad Area)
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100 m - Fiber optic
DAQ Room
DAQ PCs
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PXL RDO Architecture (1 sector)
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Ladder x 4
RDO board x 1
LU prot. power
FPGA
MTB x 1
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SIU
ADC
USB
SRAM
Power
Supplies
i/o
Control
PCs
Trigger
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fiber
DAQ
RDO PCs
Unified Development Platform
Sensor testing
Probe testing
Black – cfg, ctl, clk. path
Blue – data path
Red – power / gnd path
Green – testing path
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