Transcript ppt - UCSD VLSI CAD Laboratory

Assessing Chip-Level Impact of Double
Patterning Lithography
Kwangok Jeong*, Andrew B. Kahng*,**, and Rasit O. Topaloglu***
http://vlsicad.ucsd.edu/
* ECE Dept., UC San Diego
** CSE Dept., UC San Diego
*** GlobalFoundries, Inc.
Outline
• Double Patterning Lithography (DPL)
• Traditional Interconnect Analysis
• Additional Variability in DPL
• Misalignment in Double Patterning
• Analysis in Different DPL Options
• Experiments
• Conclusion
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Outline
• Double Patterning Lithography (DPL)
• Traditional Interconnect Analysis
• Additional Variability in DPL
• Misalignment in Double Patterning
• Analysis in Different DPL Options
• Experiments
• Conclusion
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Double Patterning Lithography (DPL)
• Pattern-doubling:
• ‘2X-resolution’ lithography with ‘1X-resolution’ equipment
Resist
Target layer
Resist
Target layer
1X
Mask1
1st Exposure
Mask
1X
Mask2
2nd Exposure
1X-resolution
2X-resolution
• Taxonomy
• Resist type: positive /negative
• Methods: double exposure (DE) / double patterning (DP) /
spacer double patterning (SDP)
• Printed feature: line / space
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Traditional Interconnect Analysis
• Designers use capacitance
tables from foundries
• 2D/3D field solver with
variations  Capacitance
tables
• Major sources of variation:
• Metal/dielectric densitydependent systematic variation
• Random process variation
• Results of variation
• Width (W) variation
• Metal height (H) variation
• Dielectric thickness (D)
variation, etc.
• Traditional interconnect
variation analysis
1. for (i = -3 ; i  3 ; i=i+1) {
2. for (j = -3 ; j  3 ; j=j+1) {
3. for (k = -3 ; k  3 ; k=k+1) {
4.
W=Wnom + iW
5.
H= Hnom + jH
6.
D= Dnom + kD
7.
run field solver over
parameterized structure}}}
8. Find nominal and worst-case
capacitance
M+1
W H
M
D
M-1
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Additional Variability in DPL
• Overlay error
• Alignment metric
• Causes:
• mask misalignment
• material stress-impacted
deformations
• litho-/etch-impacted
topography
• lens aberration, etc.
• Impacts on DPL
• Width variation
• Space (or pitch) variation
Cc
S
S
S
S
Indirect
Alignment (IA)
Direct
Alignment (DA)
• Indirect:
• Two DPL masks aligned to
a reference layer
• Error: 2S
• Direct:
Cg
 Capacitance variation
• Second DPL mask aligned
to the first DPL mask
• Error: S
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Outline
• Double Patterning Lithography (DPL)
• Traditional Interconnect Analysis
• Additional Variability in DPL
• Misalignment in Double Patterning
• Analysis in Different DPL Options
• Experiments
• Conclusion
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Misalignment in Positive DE/DP
mask1
mask2 (misaligned to left)
Positive photoresist
Dielectric
After exposure + etch
Cu filling
S
1
Space on one side increases
Space on the other side decreases
S
2
1
W
W
2
1
Required design of experiments
foreach S  (-3 ~ 3)
mask1  shift by +S/2
mask2  shift by –S/2
end
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Misalignment in Negative DE/DP
mask1
mask2 (misaligned to left)
Negative photoresist
Dielectric
After exposure + etch
After filling Cu
S
1
S
2
1
W’’
W’
P
2
P
1
S/2
Width of one increases
Width of the other decreases
Required design of experiments
foreach S  (-3 ~ 3)
mask1  change W by +S
 shift by S/2
mask2  change W by –S
 shift by S/2
end
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Spacer Thickness Variation in Positive SDP
Primary patterns
Spacers (act as if masks)
(kind of) Positive photoresist
Dielectric
After exposure + etch
After filling Cu
Cu
S S
1
2
1
W’’
W
P
2
P
1
Width and space change
Required design of experiments
foreach S  (-3 ~ 3)
mask1  change W by 0
mask2  change W by +S
end
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Spacer Thickness Variation in Negative SDP
Primary patterns
Spacers (act as if masks)
(kind of ) Negative photoresist
Dielectric
After exposure + etch
After filling Cu
Cu
S S
1
2
1
W’
W’
P’’
2
P’
1
Width and space change
Required design of experiments
foreach S  (-3 ~ 3)
mask1  change W by +S/2
 shift by +S/4
mask2  change W by +S/2
 shift by –S/4
end
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Outline
• Double Patterning Lithography (DPL)
• Traditional Interconnect Analysis
• Misalignment in Double Patterning
• Analysis in Different DPL Options
• Experiments
• Conclusion
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Experiments: Scenarios
• We examine impact of misalignment and linewidth
variation across various DPL options
Parallel
5-Interconnect
Structure
(TCAD tool)
Alignment
Photoresist
Process
Indirect
Positive
DE
Direct
Negative
DP
SDP
Direct
Interconnects
in a full-chip
(Signoff RCX)
Positive
DE
Negative
DP
SDP
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TCAD-Based BEOL Analysis Results
• Capacitance variation due to • Capacitance variation in
misalignment in DE/DP
different DPL options
215
210
205
200
195
190
185
180
175
Min
DA
Nom
IA
Positive
Resist
Max
DA
• SDP has larger variation
• Negative resist processes have
larger variation
Capacitance (aF/um)
Capacitance (aF/um)
• IA shows larger variation than DA
• Negative resist processes have
larger variation
IA
Negative
Resist
210
205
200
195
190
185
180
175
Min
DE/DP
SDP
Positive
Resist
Nom
Max
DE/DP
SDP
Negative
Resist
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Design-Level Analysis - Flow
• Overlay-aware extraction flow
1. Design GDS
AES core with
NanGate 45nm Tech.
Initial GDS
2. Split GDS
ILP-based min cost coloring
(Kahng et al. ICCAD08)
Non-DPL layers DPL layers
Base GDS
Sub-GDS1
Sub-GDS2
SUB1.GDS
SUB2.GDS
3. Pattern
Decomposition
Sub-GDS1-1
Sub-GDS1-2
Sub-GDS2-1
4. Shift and Merge
(Cadence Virtuoso)
TOP.GDS
Sub-GDS2-2
5. Resize and Extraction
(Synopsys Hercules, Star-RCXT)
Coloring and Splitting
TOP.GDS
SUB1  (x1, y1)
TOP.GDS
SUB2  (x2, y2)
Shifting and Merging
TOP.GDS
Resizing
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Design-Level Capacitance Variation
15
10
5
0
-5
M3
M3
N-SDP
P-DE/DP
M4
M4
P-SDP
Max decrease
N-DE/DP
Mean
N-SDP
N-DE/DP
P-DE/DP
P-SDP
N-DE/DP
P-DE/DP
N-SDP
P-SDP
N-DE/DP
M2
M2
N-SDP
Max increase
-15
P-SDP
-10
P-DE/DP
Capacitance Variation (%)
• Overlay error can cause more than +/- 10%
capacitance variation within a die, for all DPL options
 Large on-chip variation
 Increase of timing optimization difficulty
M5
M5
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Maximum Crosstalk-Induced Delay
• A net having maximum crosstalk delay (17um long)
Variation (%)
Variation
Delay Delay
Crosstalk
Crosstalk
(%)
• SDP shows more sensitivity  tighten overlay spec
• P-DE/DP shows least sensitivity  lessen overlay spec
10%
P-DE/DP
12%
P-DE/DP
N-DE/DP
P-SDP
N-SDP
8%
N-DE/DP
10%
M4
6% 8%
P-SDP
N-SDP
4% 6%
2% 4%
0% 2%
0%
-2%
1 2 3 1 2 3 1 2 3 1 2 3
|S|
|S|/2
|S|/2
|S|/2
-4%
M2
M4 P-SDP M2
M4
P-DE/DP
N-DE/DP
N-SDP
-6%
M4
M2
M2
M4
(Space on
(Width)
-3
-2
-1
w/o fill
one side) w/o metal fill
(Spaces on
(Space & width)
0
1 w/o fill
2
3
both sides) w/ metal fill
Overlay Error (S)
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Total Negative Slack Variation
• SDP, especially for lower layer (smaller feature),
shows more sensitivity  tighter overlay spec
12%
TNS Variation (%)
TNS Variation (%)
TNS
Normalized
1.5
10%
1.4
1.3
8%
1.2
6%
1.1
4%
1.0
0.9
2%
0.8
0%
N-SDP
P-DE/DPP-SDP
N-DE/DP
P-SDP
N-SDP
M2
1
M3
M4
M5
2
M2
M4
M2
M3
M4
3
M5
w/oOverlay
metal error
fill S variationw/(sigma)
metal fill
P-DE/DP M2
N-DE/DP M2
P-SDP M2
N-SDP M2
P-DE/DP M3
N-DE/DP M3
P-SDP M3
N-SDP M3
P-DE/DP M4
N-DE/DP M4
P-SDP M4
N-SDP M4
P-DE/DP M5
N-DE/DP M5
P-SDP M5
N-SDP M5
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Outline
• Double Patterning Lithography (DPL)
• Traditional Interconnect Analysis
• Misalignment in Double Patterning
• Analysis in Different DPL Options
• Experiments
• Conclusion
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Summary of Observations
• Overlay error with indirect alignment (IA) results in higher
capacitance variations compared to direct alignment (DA)
• Capacitance can vary > 10% due to misalignment
 Large OCV  increase timing optimization difficulty
• Timing can be degraded significantly, e.g., > 10% worse TNS
• P-DE/DP may be the most favorable option for BEOL DPL
• With the same 3 overlay control, the variation in P-DE/DP is
50% of N-DE/DP or P-SDP, and 25% of N-SDP   Overlay
control spec for P-DE/DP can be relaxed by 2X compared to
others
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Conclusion and Ongoing Work
• We provide a variational interconnect analysis
framework for double patterning lithography
• We analyze mechanisms of interconnect variations due to
misalignment and spacer thickness variation in DPL
• We provide both interconnect and design-level RCextraction framework reflecting interconnect variation in a
45nm DPL process
• We compare the impact of overlay error in different DPL
options
• Ongoing work
• Development of timing analysis and optimization
methodology considering interconnect variation in DPL
• Incorporation of statistical techniques to target pessimism
reduction
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Thank You!
Impact of Misalignment on FEOL
• Standard cell decomposition
Original
P1
P2
M
C
BASE
• Experimental setup
• 10nm 3 misalignment is assumed between layers
• Design of experiments (all permutation: 3*3*3*3 = 81 cases)
• P1: -10nm (L) / 0nm (C) / +10nm (R)
• P2: -10nm (L) / 0nm (C) / +10nm (R)
• M:
-10nm (L) / 0nm (C) / +10nm (R)
• C:
-10nm (L) / 0nm (C) / +0nm (R)
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Experimental Results on FEOL
• Measured Delay Variation (%)
• Flow
Tr-level RC-Extraction
P1
STAR-RCXT
Circuit Simulation
P2
L
L
C
HSPICE
R
• Impact of misalignment
on cell delay is
negligibly small (< 2%)
L
C
• Capacitance variation due
to misalignment << gate
capacitance
C
R
L
R
C
R
M
L
C
R
L
C
R
L
C
R
L
C
R
L
C
R
L
C
R
L
C
R
L
C
R
L
C
R
L
0.91
0.89
0.87
0.06
0.04
0.04
-1.45
-1.47
-1.47
0.72
0.7
0.68
-0.15
-0.15
-0.17
-1.68
-1.68
-1.7
0.51
0.49
0.47
-0.38
-0.38
-0.4
-1.94
-1.94
-1.96
C
C
1.19
1.15
1.13
0.23
0.19
0.17
-0.68
-0.72
-0.74
1.02
0.98
0.96
0.04
0
-0.02
-0.89
-0.94
-0.96
0.85
0.81
0.79
-0.15
-0.19
-0.21
-1.11
-1.15
-1.15
R
0.89
0.87
0.83
0.45
0.4
0.38
-0.64
-0.66
-0.7
0.7
0.68
0.64
0.23
0.21
0.17
-0.87
-0.89
-0.91
0.51
0.49
0.47
0.02
0
-0.02
-1.09
-1.11
-1.13
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DPL Options
• Double Exposure
• Double Patterning
Resist
Hardmask
Target layer
Resist
Target layer
Mask1
Resist
Hardmask
Buffer oxide
Hardmask
Target
layer
Target layer
Mask1
1st
Mask2
2nd
Exposure
2nd
Spacer formation
1st Litho-etch
Oxide depo. CMP
Litho-etch
Spacer removal
• Printed Feature
• Photoresist
mask
2nd etch
mask
positive resist
negative resist
Dielectric
positive resist
Dielectric
Poly
After exposure
& etch
Cu interconnect
After exposure
& etch
Cu interconnect
After Cu filling
(a) Positive-tone
Mask
1st
Litho-etch
Exposure
Mask2
• Spacer-DP
Poly
(b) Negative-tone
(a) Spaces (Trench-First)
(b) Lines
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Mask Coloring and Layout Examples in DPL
• Mechanism of misalignment-induced variation
2 4
2 4
6
1
6
1
3 5
4
Original
patterns
1
Coloring
S
6
5
3 5
S
2
Patterns 1
3
Patterns 2
(a) DE and DP Process
Dummy for
pattern 6
2 4
2 4
6
1
3 5
Original
patterns
Spacer (gray) Narrow space
a b
W
1
W”
35 6
Coloring
Spacer formation
(Large spacer)
Trim & repair
(dark gray)
(b) SDP Process
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Design-Level Analysis - DOE
• Design of Experiments for DE/DP with DA
1. foreach layer  { M2, M3, M4, M5 }
2.
decompose layer into layermask1 and layermask2
3.
foreach S { -3/2, -2/2, -/2, 0, /2, 2/2, 3/2}
4.
shift layermask1 by S
5.
shift layermask2 by –S
6.
end
7.
layer  layermask1 + layermask2
8.
foreach W { -3/2, -2/2, -/2, 0, /2, 2/2, 3/2}
9.
resize layer by W
10.
end
11.
merge with other layers
12.
RC-Extraction and Timing Analysis
13. end
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Impact on Capacitance Variation
• Total interconnect capacitance: maximum C(%)
• Among top 20% high capacitance nets
• Impact of overlay < impact of width
Overlay
Width
Min
-7.7%
-22.2%
-3
Avg
1.4%
4.7%
Max
9.2%
7.1%
Min
-7.3%
-3.6%
+3
Avg
1.4%
5.3%
Max
9.7%
28.6%
• Sum of capacitance in the most critical path
• Critical path has short interconnects  impact of BEOL
variation significantly reduces
• Impact of overlay < impact of width
Overlay
Width
Interconnect only
Min
Max
-0.08%
0.47%
-1.87%
2.59%
Interconnect + Gate
Min
Max
-0.04%
0.25%
-0.99%
1.38%
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Impact on Crosstalk-Induced Delay
• Maximum coupling induced delay change
• PrimeTime-SI (Synopsys) is used to find a net that is
mostly affected due to crosstalk
• Temporal/functional filtering is performed
• Selected net structure
M2 segment:
1.604um
M3 segment:
0.78um
M4 segment:
14.788um
• A net with relatively small length (~17um) can have >10%
delay changes due to overlay error
Overlay
Width
Cc (pF)
Cg (pF)
@Min @Max @Min @Max
1.842 1.863 1.089 1.053
1.840 1.906 1.089 1.120
Delay
Min
Max
-0.47%
13.1%
-0.82%
15.4%
Capacitance when Delay is maximum
Capacitance when Delay is minimum
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Impact on Timing
• Longest path and total negative slack (TNS)
• Impact of overlay << impact of width
• Longest path delay changes negligibly
• However, overall timing (TNS) can change significantly
Longest path delay
Min
Max
-0.06%
0.98%
-1.22%
2.00%
Total Negative Slack (ns)
Overlay
Width
TNS
Min
3.2%
-34.3%
Max
3.8%
49.4%
-60
-50
-40
-30
-20
Overlay
Width
-10
0
-3s
-2s
-1s
0s
1s
2s
3s
Interconnect varaition
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