Design of an 8-bit Carry-Skip Adder Using Reversible Gates Vinothini Velusamy, Advisor: Prof. Xingguo Xiong Department of Electrical Engineering, University of Bridgeport, Bridgeport, CT 06604 Abstract

Reversible logic circuits are of great interests to power minimization in digital VLSI design. They have found broad applications in low power CMOS design, optical information processing, DNA computing, bioinformatics and quantum computing. In this poster we implemented an 8-bit carry-skip adder using reversible gate in PSPICE, and simulated its power consumption for the given input pattern sequence. In order for comparison, an 8-bit carry-skip adder based on traditional CMOS technology is also designed and simulated. PSPICE simulation result shows that the reversible-gate based adder leads to faster speed compared to traditional CMOS design. Further, PSPICE power simulation is used to extract the power consumption of both circuits for the same given pattern sequence. Simulation results demonstrate effective power savings of the reversible-gate based adder compared to traditional CMOS adder for the given input pattern sequence. This verifies the effectiveness of the reversible-gate based adder design in both performance and power consumption.

Circuit Design

In recent years, reversible logic circuits have attracted tremendous interests in low power VLSI design. In a traditional CMOS gate, input states are lost because generally there are less number of outputs than inputs. That is, less information is present in the outputs than that was present at the input. This loss of information leads to the loss of energy as heat dissipation to the surrounding environment. That's the reason why a CMOS circuit consumes power during state switching. However, in a reversible gate, there are same amount of inputs and outputs, and the state of reversible gate is reversible. That is, one can trace the outputs uniquely to the inputs. A reversible gate only moves the states around, and no information is lost. As a result, energy is conserved, which leads to significant power savings. In this project we implemented an 8-bit carry-skip adder using both CMOS logic and reversible gates, and compared their power consumption. The block diagram of original 8-bit carry-skip CMOS adder is shown in Fig. 1.

Figure 5. PSPICE schematic design of 8-bit carry skip adder (CMOS logic)

2. Reversible Circuit Design

Figure 6. Simulated power curve of 8-bit carry skip adder (CMOS logic) Reversible gate has distinct output pattern corresponding to each distinct input assignment. Thus Reversible logic gate must have the same number of inputs and outputs. Complementary Pass-transistor Logic (CPL) is used for designing the reversible gate based 8-bit carry skip full adder. The Complementary Pass transistor logic uses only NMOS transistors, and a dedicated power supply (V cc ) is not needed because an output is directly connected to input to get logic “1” and “0” as needed.

The Reversible logic is implemented using so-called New Full Adder (NFA) block. The New Full adder consists of Full adder designed by complementary Full adder and XOR gate for the parity generator. Both AND gate and OR gate can be easily implemented using the reversible logic gate. The PSPICE schematic design of the 8 bit carry skip full adder based on reversible gate logic is shown in Fig. 7. Its simulated power curve for the same given input pattern sequence as that fed to the previous CMOS adder is shown in Fig. 8. As we can see, the average power (t=0~800ns) of the 8-bit carry skip adder based on reversible logic is: P reverse (T)=368.934

µW.

Figure 1.The original 8-bit carry skip adder circuit An 8-bit carry skip adder can be constructed with eight carry-propagate compatible full adders. The propagate signals p0, p1, p2, p3, p4, p5, p6 and p7 generated by each adder are AND-ed. The resulting output is AND-ed with carry input c i . The corresponding output is OR-ed with carry output of the fourth full adder to get the final carry output. The same implementation is also used for the implementation of reversible logic gate and the power is compared.

Figure 2. Reversible gate R Table 1: Truth Table of Reversible gate R Figure 3. Logic diagram of reversible gate R Figure 7. PSPICE schematic of 8-bit carry skip adder (reversible logic) Figure 8. Simulated power curve of 8-bit carry skip adder (reversible logic) A comparison of power consumption (by PSPICE power simulation) between original CMOS circuit and reversible circuit is shown in Table 2. From the result, it shows that the reversible logic leads to an effective power saving of 28.66% compared to the original CMOS circuit for the same given input pattern sequence.

In addition to the power consumption, we also compare the worst-case delay for both circuits. The simulated waveforms of carry-out signal of both traditional CMOS full adder and the reversible full adder are shown below in Figure 9 and 10 separately. As shown in the figures, the delay of reversible adder is less than that of the traditional CMOS adder. Thus the Reversible logic also leads to improved speed. The delay comparison is also shown in Table 2.

Figure 4: Reversible gate R in PSPICE Schematic Reversible gate has distinct output for each distinct input assignment. The inputs to reversible gates can be uniquely determined from its outputs. A reversible logic gate must have same number of inputs and outputs as shown in figure 2. A reversible gate is balanced, i.e. the outputs are 1s for exactly half of the inputs. It is proposed with three inputs and three outputs as shown in figure 3. The truth table of the gate is shown in Table 1. It can be verified from the truth table that the input pattern corresponding to a particular output pattern can be uniquely determined. The gate can be used to invert a signal and also duplicate a signal. The signal duplication function can be obtained by setting input b=0. AND function is obtained by connecting the input c to 0, the output is obtained at the third terminal. OR function is obtained by connecting two reversible gates with input c=0 for a and c=1 for next reversible gate which is shown in Figure 4.

Results and Discussion 1. Original CMOS Circuit

The PSPICE schematic design of the original 8-bit carry skip adder circuit based on CMOS technology is shown in Fig. 5. We selected 8 random input patterns for power estimation, each lasts for 100ns. The PSPICE power simulation curve of the original circuit is shown in Fig. 6. The average power consumption of the CMOS circuit for the given input pattern sequence (t=0~800ns) is found to be: P orig (T)=517.140

µW.

Figure 9: Carry out of the original circuit Figure 10: Carry out of the Reversible circuit Table 2. Power and delay comparison of CMOS and reversible full adders

Average Power Consumption (t=0~800ns)

517.140 µV

Power saving compared to original design Delay (ns) Delay improvement compared to original circuit

CMOS adder 3 Reversible adder 368.934 µV 28.66% 1 66.7%

Conclusions and Future Work

In this poster, we implemented an 8-bit carry skip full adder based on reversible logic.

In order for comparison, original 8-bit CMOS carry skip full adder is also designed.

PSPICE power simulation shows effective power saving of the reversible adder compared to the traditional CMOS adder for the same giving input pattern sequence.

Simulation result also shows the reversible full adder leads to improved speed compared to traditional CMOS full adder. In our future work, we will further extend the reversible logic design for other CMOS circuit design as well, such as multiplier, ALU and memory circuitry.