Transcript Unit 13-1 SPI

ECE 371 Unit 13 - Part 1
Serial Peripheral Interface (SPI)
Serial Peripheral Interface
• Synchronous Serial Interface
• Widely used to interface Peripheral Chips
with Microcontrollers
• Much faster bit rate than asynchronous
SCI method.
• SPI system consist of one Master Device and one or more Slave Devices
• Master Device sends out a Serial Shift Clock signal (SCK) to all slaves, to
serve as timing reference for the serial data transfer.
• No Start Bits or Stop Bits as used in SCI (asynchronous serial I/O method)
• 3 SPI Channels on MC9S12Dp256B Microcontroller
• 4 Pins Associated with Each SPI Channel
- MISO (Serial input data for a Master, serial output data
for a Slave)
- MOSI ((Serial output data for a Master, serial input data
for a Slave)
- SCK (Serial data clock)
- SS (Slave select; for a system with a single slave, SS = 0
selects the Slave and SS = 1 selects the Master.
Master/Slave SPI Interface
Parallel-to-Serial and Serial to Parallel-to-Serial Registers are
needed to interface a peripheral device to the microcontroller
using the SPI protocol.
• 74HC 595 - Serial-to-Parallel Converter Register
- Serial Input
- Parallel Output
- (Also serial output)
• 74HC 597 - Parallel-to Serial Converter Register
- Parallel Input
- Serial Output
- (Also Serial Input)
74HC595 8-bit Shift Register
(Serial to parallel converter)
Serial
input
Serial
output
Parallel output
74HC595 8-bit Shift Register and 8-bit Storage
Serial input
Serial Output
Parallel
Output
SPI Connections between the Microcontroller
and a 74HC595 Register to implement an Output
Port
Microcontroller signal
74HC595 pin
MOSI
DS (Serial Data Input for 74HC595)
SCK
SH_CP (“Shift” Clock Pulse)
SS
ST_CP (Store Shift Register Data into Latch)
OE = “0” (Enable Latch Output Bus Drivers)
MR = “1” -- (Master Reset not active)
74HC595 8-bit Shift Register
with Output Latches
Clock Latches
SYNC or SS
SCLK
D7
D6
D5
D4
D3
D2
D1
MOSI – Shifted into Shift Register
D0
SPI Overview
Shift Data into
Shift Register
Shift Data into
Shift Register
SYNC PULSE
Transfer Shift Register Data to Data Latches when SYNC Pulse occurs
Set Flag to Signal that there is Received Data in Data Latches
Slave – 74HC595
74HC597 – 8 bit Parallel In
Serial Out
Load
Reset Serial Data In
Parallel
Input
Serial
Data
Out
SS SCLK
SP Slave – 74HC597
LCLK = Load Parallel FF
SPI1 and SPI2 can be implemented on Port P or Port H
SPI1 signals
If MODRR[5]=0
SPI2 signals
If MODRR[6]=0
SPI1 signals
If MODRR[5]=1
SPI2 signals
If
MODRR[6]=1
SPI0 can be implemented on Port M or Port S
SPI0 signals if
MODRR[4]=0
SPI0 signals if
MODRR[4]=1
Module Routing Register
SPI Channel 0 Routing
SPI Channel 1 and 2 Routing
Use MODRR[5] = 0 and MODRR[6] = 0
SPI Channel 1
• If SPI pin is output, then DDRx must set
pin as out.
• SPI1 uses Port P on our System:
– PP0 – MISO1 – In
– PP1 – MOSI1 – Out
– PP2 – SCK1 – Out
– PP3 - SS1 – Out
SPI Register Designations
• SPI1CR1, SPI1CR2, SPI1SR, SPI1DR,
SPI1BR, DDRM, PTM, DDRP, PTP
• Laboratory
– Port M is Used to Select 1 of 8 SPI Serial
Devices on Project Board
– Port S Shares Pins with SPI Channel 0
Project Board Laboratory
• 8 SPI Devices on Project Board
• Port M [6:4] Selects SPI Device
– PM[4] = SS0
– PM[5] = SS1
– PM[6] = SS2
• D/A Converter is Device 5,
(SS2 SS1 SS0 = 1 0 1)
• SPI Slaves Implemented with 74HC595
Slave Selection – 8 Slaves on
Project Board
PM[4] => SS0
PM[5] => SS1
PM[6] => SS2
SS = PP[3]
SS => S5
SER_DIS = “1”
Connected to gnd by jumper
SPI Channel 1 – SPI1
•
•
•
•
Port P[0] = MISO
Port P[1] = MOSI
Port P[2] = SCK
Port P[3] = SS
SPI Channel 1 Definitions
#define SPI1CR1
#define SPI1CR2
#define SPI1BR
#define SPI1SR
#define SPI1DR
_P(0xF0)
_P(0xF1)
_P(0xF2)
_P(0xF3)
_P(0xF5)
SPI Data Register
SPI Baud Rate Register
Baud = BusClock/BaudRateDivisor = 2000000/BaudRateDivisor
SPI Control Register 1
SPI Control Register 1
SPI Control Register 1
SPI Control Register 2