IC Layout

Adapted from Digital Integrated Circuits, 2nd Ed.

1

Contents   Software overview Design Rules and Design rules check (DRC)  Layers  N-well  Active  Metals  Poly  Interconnects  R, L, C  Propagation speed of signals in lines Adapted from Digital Integrated Circuits, 2nd Ed. 2

Design Software L-Edit Circuit at the mask (layout) level S-Edit Circuit at the Schematics level LVS consistency mask = schematic ?

Simulation: T-Spice or any Spice based engine Adapted from Digital Integrated Circuits, 2nd Ed. 3

Design Software L-Edit Circuit at the mask (layout) level 4 S-Edit Circuit at the Schematics level 5 LVS consistency mask = schematic ?

3 2 1 Simulation: T-Spice or any Spice based engine Adapted from Digital Integrated Circuits, 2nd Ed. 4

Process Layers Adapted from Digital Integrated Circuits, 2nd Ed. 5

The N-Well     Assuming a p-type wafer, n channel transistors are fabricated directly in the wafer; p-channel are fabricated in an “n-well” Processes with n-well over p substrates are called n-well processes Substrate is also known as bulk or body N-well forms a diode (normally reverse biased) with the substrate Adapted from Digital Integrated Circuits, 2nd Ed. 6

N-Well: Design rules    Every layer has certain rules to satisfy in order to be safely built MOSIS webpage data for AMI 0.5 R(N_Well) = 810Ω/□ Exercise: Layout and extract a resistor (minimum width) of 8K Adapted from Digital Integrated Circuits, 2nd Ed. 7

N-well diode capacitance  When the diode is reverse-biased (typical situation)

C j



C j

0

m

 1

v d

 0  Two components: bottom capacitance and sidewall capacitance  0 

V T

ln  

N A N D n i

2  

C j

0 

C j

0

b



C j

0

s C j

0

b



C j

0

s

 Capacitance per area × bottom area Capacitance per area × depth of well × perimeter Adapted from Digital Integrated Circuits, 2nd Ed. 8

N-well diode capacitance   From MOSIS data, we know:

C j

0  Our resistor has a bottom capacitance 40

aF

/ 

m

2

C j

0   12    119    40

aF

/ 

m

2  3 .

6 

m

 35 .

7 

m

 40

aF

/ 

m

2  5 .

1

fF

 And no more data …  Approximate worst case RC   40

ps

Adapted from Digital Integrated Circuits, 2nd Ed. 9

Active Layer Adapted from Digital Integrated Circuits, 2nd Ed. 10

Active Layer    Active layers, both n+ and p+ are used to make the source and drain of MOSFET’s Active defines the oxide mask where doping will take place: Regions outside Active have FOX (LOCOS) N select and P select define the doping mask Adapted from Digital Integrated Circuits, 2nd Ed. 11

Act Design Rules Adapted from Digital Integrated Circuits, 2nd Ed. 12

N+ and P+ rules Adapted from Digital Integrated Circuits, 2nd Ed. 13

Act contact rules  In this case, there is a special contact to join metal and active Adapted from Digital Integrated Circuits, 2nd Ed. 14

Poly Adapted from Digital Integrated Circuits, 2nd Ed. 15

Poly Layer   Polysilicon is made up of small crystalline regions of silicon Poly is used for the gates of MOS transistors  They can make resistors and local connections for transistors Adapted from Digital Integrated Circuits, 2nd Ed. 16

Poly rules Adapted from Digital Integrated Circuits, 2nd Ed. 17

Poly contact rules Adapted from Digital Integrated Circuits, 2nd Ed. 18

Metal Layers Adapted from Digital Integrated Circuits, 2nd Ed. 19

The Metal layers    Metal layers are used to interconnect devices (transistors, resistors, inductors and capacitors) Vias are used to interconnect the different metal layers Example: AMI 0.5 (three metals) Adapted from Digital Integrated Circuits, 2nd Ed. 20

Metal Design rules  Metals 1, 2 and 3 rules  Spacing rules  Overlap rules  Vias 1 and 2 rules  In general, higher metal layers require bigger dimensions and spacing Adapted from Digital Integrated Circuits, 2nd Ed. 21

Metal 1 Design Rules: Separation Adapted from Digital Integrated Circuits, 2nd Ed. 22

Metal 1 Design Rules: Cnt Overlap Adapted from Digital Integrated Circuits, 2nd Ed. 23

Metal 2 rules: Separation Adapted from Digital Integrated Circuits, 2nd Ed. 24

Metal 2 Design Rules: via1 Overlap Adapted from Digital Integrated Circuits, 2nd Ed. 25

Metal 3 rules: Separation Adapted from Digital Integrated Circuits, 2nd Ed. 26

Metal 3 Design Rules: via2 Overlap Adapted from Digital Integrated Circuits, 2nd Ed. 27

Via 1 rules Adapted from Digital Integrated Circuits, 2nd Ed. 28

Via 2 rules Adapted from Digital Integrated Circuits, 2nd Ed. 29

Interconnects Adapted from Digital Integrated Circuits, 2nd Ed. 30

The Wire transmitters

schematics

receivers

physical

Adapted from Digital Integrated Circuits, 2nd Ed. 31

Interconnect Impact on Chip Adapted from Digital Integrated Circuits, 2nd Ed. 32

Wire Models All-inclusive model Capacitance-only Adapted from Digital Integrated Circuits, 2nd Ed. 33

Impact of Interconnect Parasitics   Interconnect parasitics  reduce reliability  affect performance and power consumption Classes of parasitics  Capacitive  Resistive  Inductive Adapted from Digital Integrated Circuits, 2nd Ed. 34

Nature of Interconnect

Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II Global Interconnect S Global = S Die S Local = S Technology 10 100 1,000 Length (u) 10,000

Adapted from Digital Integrated Circuits, 2nd Ed.

100,000

35

INTERCONNECT: Capacitance Adapted from Digital Integrated Circuits, 2nd Ed. 36

Capacitance of Wire Interconnect

V in C gd

12

V DD M

2

C db

2

V out C g

4

M

1

C db

1

C w

Interconnect

C g

3

V DD M M

4 3

V out

2 Fanout

Simplified Model

V in V out C L

Adapted from Digital Integrated Circuits, 2nd Ed. 37

Capacitance: The Parallel Plate Model Current flow

L

Electrical-field lines

W H t d i

Dielectric Substrat e

c int

 

di WL t di S Cwire



S S



S L

Adapted from Digital Integrated Circuits, 2nd Ed.  1

S L

38

Permittivity Adapted from Digital Integrated Circuits, 2nd Ed. 39

Fringing Capacitance

H (a) + W - H/2 (b)

Adapted from Digital Integrated Circuits, 2nd Ed. 40

Fringing versus Parallel Plate Adapted from Digital Integrated Circuits, 2nd Ed. (from [Bakoglu89]) 41

Interwire Capacitance fringing parallel Adapted from Digital Integrated Circuits, 2nd Ed. 42

Impact of Interwire Capacitance Adapted from Digital Integrated Circuits, 2nd Ed. (from [Bakoglu89]) 43

Wiring Capacitances (0.25 mm CMOS) Adapted from Digital Integrated Circuits, 2nd Ed. 44

AMI 0.5

µm process capacitances  Area capacitance (all values in aF/  m 2 ) substrate M1 32 M1 M2  Fringe capacitances (all values in aF/  m) M2 16 31 substrate M1 76 M1 M2 Adapted from Digital Integrated Circuits, 2nd Ed. M2 59 51 M3 10 13 31 M3 39 33 52 45

INTERCONNECT: Resistance Adapted from Digital Integrated Circuits, 2nd Ed. 46

Wire Resistance

H W L

R 1

R =



L H W

Sheet Resistance R o R 2 Adapted from Digital Integrated Circuits, 2nd Ed. 47

Interconnect Resistance Adapted from Digital Integrated Circuits, 2nd Ed. 48

Dealing with Resistance  

Selective Technology Scaling Use Better Interconnect Materials

 reduce average wire-length  e.g. copper, silicides 

More Interconnect Layers

 reduce average wire-length Adapted from Digital Integrated Circuits, 2nd Ed. 49

Polycide Gate MOSFET

n + p

Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

Silicide PolySilicon SiO 2 n +

Adapted from Digital Integrated Circuits, 2nd Ed. 50

Sheet Resistance Adapted from Digital Integrated Circuits, 2nd Ed. 51

Modern Interconnect Adapted from Digital Integrated Circuits, 2nd Ed. 52

Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric Adapted from Digital Integrated Circuits, 2nd Ed. 53

Resistance in AMI 0.5

µm process  Resistance M1 M2 M3 Rs 0.09Ω/□ 0.09 Ω/□ 0.05 Ω/□  A line of minimum width and 1mm long (1100 and 666 □ long, resp.) Rs M1 100 Ω M2 100 Ω M3 33 Ω Adapted from Digital Integrated Circuits, 2nd Ed. 54

Vias parasitics  Vias exhibit a contact resistance given by the process M2 M3 P+ Contact R [Ω] 126 N+ 57.5

Poly M1 16 □ 0.82

0.79

 They also have a current limitation given by the electromigration phenomenom. Typically, 0.5mA/cnt Adapted from Digital Integrated Circuits, 2nd Ed. 55

Metal Current Capacity  

Due to Electromigration

, wire can be damaged For Aluminum, the maximum current density (rule of thumb) is: 1   

mA



m

   Adapted from Digital Integrated Circuits, 2nd Ed. 56

INTERCONNECT: Inductance Adapted from Digital Integrated Circuits, 2nd Ed. 57

Metal Parasitics: L  A metal line exhibits an inductance that can be estimated as:

L

 1 .

25

w

 1 .

393  0 .

667

h

ln 

w h

1 .

44   (

nH

/

mm

)  Assumption: w > h  L is proportional to

w

and inversely prop. to

h

Adapted from Digital Integrated Circuits, 2nd Ed. 58

Metal Parasitics: L    Ground bounce: The dI/dt along power lines actually produce a voltage drop due to the inductance Increase the width of the conductors supplying current Increase the capacitance of the conductors supplying current Adapted from Digital Integrated Circuits, 2nd Ed. 59

Interconnect Modeling

Adapted from Digital Integrated Circuits, 2nd Ed. 60

The Lumped Model Driver

V in R driver V out C lumped

Adapted from Digital Integrated Circuits, 2nd Ed.

V o ut c wi re

61

The Lumped RC-Model: Elmore Delay Adapted from Digital Integrated Circuits, 2nd Ed. 62

The Ellmore Delay: RC Chain Adapted from Digital Integrated Circuits, 2nd Ed. 63

Wire Model Assume: Wire modeled by N equal-length segments For large values of N: Adapted from Digital Integrated Circuits, 2nd Ed. 64

The Distributed RC-line Adapted from Digital Integrated Circuits, 2nd Ed. 65

Step-response of RC wire as a function of time and space 2.5

x= L/10 2 x = L/4 1.5

x = L/2 1 x= L 0.5

0 0 0.5

1 1.5

2 2.5

time (nsec) 3 3.5

4 4.5

5 Adapted from Digital Integrated Circuits, 2nd Ed. 66

RC-Models Adapted from Digital Integrated Circuits, 2nd Ed. 67

Driving an RC-line

R s

(

r w ,c w ,L

)

V out V in

Adapted from Digital Integrated Circuits, 2nd Ed. 68

Design Rules of Thumb  rc delays should only be considered when

t

pRC gate Lcrit >> 

t

pgate >>

t

pgate /0.38rc

of the driving  rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line 

t

rise < RC when not met, the change in the signal is slower than the propagation delay of the wire © MJIrwin, PSU, 2000 Adapted from Digital Integrated Circuits, 2nd Ed. 69

Appendix Adapted from Digital Integrated Circuits, 2nd Ed. 70

AMI 0.5 typical parameters (T36s) Adapted from Digital Integrated Circuits, 2nd Ed. 71

Appendix  Poly resistor layout Adapted from Digital Integrated Circuits, 2nd Ed. 72

Poly: Resistor Design   MOSIS webpage data for AMI 0.5 R(N_Well) = 22Ω/□ Exercise: Layout and extract a resistor (minimum width) of 1K. Try to make a square design    Number of squares to achieve the desired resistance = 1000/22 □ = 45.5

Setting W = 2  then L = 91  Run DRC, extract and verify Adapted from Digital Integrated Circuits, 2nd Ed. 73

Folded Resistor Design:   Folding the resistor leads to compact designs Squares and corners contribute partially to the material resistance Adapted from Digital Integrated Circuits, 2nd Ed. 74

Folded Resistor Design:  Calculation for a square layout  Assume Ns segments of width Ws, length Ls and spacing Wg  The number of squares is:

N

  2 ( 0 .

8 )  2

Ls

 2

Ws Ws

 (

Ns

 2 )

Ls Ws

 (

Ns

 1 ) 2 ( 0 .

56 ) 

Wg Ws

 For a square design:

Ls

 2

Ws

 (

Ns

 1 )(

Ws



Wg

) 

Ws

Adapted from Digital Integrated Circuits, 2nd Ed. 75

Folded Resistor Design:  For the 1K resistor,  N□ = 45.5

 Ns=5.1

 Ls=4.53

Adapted from Digital Integrated Circuits, 2nd Ed. 76