Transcript MS Powerpoint

The Use of Microcontrollers
Using ATMEL’s ATmega168
as an example
1
Programming a Microcontroller
What’s Needed?
$7.50
$34.00
Computer
•Software
•Write Code
•Simulate
•AVR Studio 4
•Port
•Serial
•Parallel
•USB
Programmer
•Development Board
•JTAG/ICE
•ISP
•Programmer
•Bit-Bang
•ADAFruit
•ISP
•AVRISP Mk II
Microcontroller
•Connection
•DIP
•SOIC
•QFN
•Capability
•ADC/DAC
•PWM
•USB
2
Why Atmel’s AVR Microcontroller?
1.
RISC architecture with mostly fixed-length instruction, load-store memory access,
and 32 general-purpose registers.
2. A two-stage instruction pipeline that speeds up execution.
3. Majority of instructions take one clock cycle
4. Up to 20-MHz clock operation
5. Wide variety of on-chip peripherals, including digital I/O, ADC, EEPROM,
Timer, UART, RTC timer, pulse width modulator (PWM), etc
6. Internal program and data memory
7. In-system programmable
8. Available in 8-pin to 64-pin package size to suit wide variety of applications
9. Up to 12 times performance speedup over conventional CISC controllers.
10. Wide operating voltage from 2.7 V to 6.0 V.
11. A simple architecture offers a small learning curve to the uninitated.
3
Scalability
4
ATtiny25 Block Diagram
5
ATtiny2313 Block Diagram
6
ATmega168 Block diagram
7
ATmega16 Block diagram
8
Different Types of AVR Controllers
9
ATmega168 Pins
PDIP
(PCINT14/RESET) PC6
(PCINT16/RXT) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
PCINT0/CLK0/ICP1) PB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
10
Memory
•
Flash Code Memory
– 16-bit words starting at 0x0000
– Size dependent on AVR microcontroller
– Non-volatile
– Read-only memory (writing is external to code)
•
Data Memory
– General Purpose Registers
• 32 8-bit registers
– I/O Registers
• Two 8-bit registers for each I/O line
– SRAM
• 8-bit memory with size dependent on AVR microcontroller
•
EEPROM Memory
– Typically reserved for variables that must retain their value in the event of a
shutdown (e.g., system calibration data unique to each board)
• Slow speed writing (1 millisecond for 1 byte of memory)
• Limited number of write cycles
11
AVR Risk Architecture
• The Register File
– 32 8-bit registers
12
I/O Memory Registers
•
SREG: Status Register
•
EEDR: EEPROM Data Register
•
SP: Stack Pointer Register
•
EECR: EEPROM Control Register
•
GIMSK: General Interrupt Mask Register
•
PORTB: PortB Data Register
•
GIFR: General Interrupt Flag Register
•
DDRB: PortB Data Direction Register
•
MCUCR: MCU General Control Register
•
PINB: Input Pins on PortB
•
MCUSR: MCU Status Register
•
PORTD: PortD Data Register
•
TCNTO: Timer/Counter 0 Register
•
DDRD: PortD Data Direction Register
•
TCCR0A: Timer/Counter 0 Control Register A
•
PIND: Input Pins on PortD
•
TCCR0B: Timer/Counter 0 Control Register B
•
SPI I/O Data Register
•
OCR0A: Timer/Counter 0 Output Compare
Register A
•
SPI Status Register
•
•
SPI Control Register
OCR0B: Timer/Counter 0 Output Compare
Register B
•
UART I/O Data Register
•
TIMSK0: Timer/Counter 0 Interrupt Mask
Register
•
UART Status Register
•
UART Control Register
•
TIFR0: Timer/Counter 0 Interrupt Flag Register
•
UART Baud Rate Register
•
EEAR: EEPROM Address Register
•
ACSR: Analog Comparator Control and
Status Register
13
Port Registers
PORTB: PortB Data Register
Bit
7
6
5
4
3
2
1
0
DDRB: PortB Data Direction Register
Bit
7
6
5
4
3
2
1
0
5
4
3
2
1
0
PINB: Input Pins on PortB
Bit
7
6
Similar for Ports C and D.
14
Parallel I/O Ports
•
•
Most general-purpose I/O devices
Each I/O Port has 3 associated registers
1.
DDRx (where “x” is A, B, C…)
•
Data Direction Register Port x
•
Determines which bits of the port are input and which are output
DDRB = 0x02; /* sets the second lowest of port B to output” */
2.
PORTx
•
Port Driver Register
PORTB = 0x02; /* sets the second bit of port B and clears the others */
3.
PINx
•
Port Pins Registers
•
Returns the status of all 8 port B pins.
unsigned int x;
x = PINB; /* Places the status of port B into variable x */
15
Input/Output Ports
• All ports initially set to input
• Must declare all output pins using DDRx
(Data Direction Registry Port x)
• The default for input port pins is floating. Can supply a
pull-up resistor by writing logic 1 to the corresponding bit
of the port driver register
DDRA = 0xC0; /* upper 2 bits are output, lower 6 bits are input*/
PORTA = 0x03; /enable internal pull-ups on lowest 2 bits*/
• Port pins in output mode are typically capable of sinking
20 mA, but source much less.
16
Bytes
Decimal
Binary
Hexadecimal
0
0000
0x0
1
0001
0x1
2
0010
0x2
3
0011
0x3
4
0100
0x4
5
0101
0x5
6
0110
0x6
7
0111
0x7
8
1000
0x8
9
1001
0x9
10
1010
0xA
11
1011
0xB
12
1100
0xC
13
1101
0xD
14
1110
0xE
15
1111
0xF
17
Output Port
Sink vs Source
• When does the LED light for
the Sink? Source?
• Which gives the brighter light?
PORTBx set to 1
5V
5V
PORTBx set to 0
5V
Source
5V
5V
5V
PORTBx set to 1
PORTBx set to 0
Sink
18
To Drive an LED
#include <avr/io.h>
#include <avr/delay.h>
int main(void)
{
DDRB = (1<<DDRB4);
PORTB = (1<<PORTB4);
while(1)
{
_delay_ms( 3000);
PORTB = 0b00000000;
_delay_ms( 3000);
PORTB = 0b00010000;
}
}
VCC
VCC
VCC
(PCINT4/XTAL2) PB4
GND
Is LED on when PB4 is zero or one?
*To find definitions like PORTB4, open the m168def.inc file under
C:\Program Files\Atmel\AVR Tools\AvrAssembler\Appnotes
19
m168def.inc
;***** SPECIFY DEVICE ******************************************************
.device ATmega168
;***** MEMORY MAPPED I/O REGISTER DEFINITIONS (&FF-$60) ********************
.equ TCNT1H =$85
.equ TCNT1L =$84
.equ TCCR1C =$82
.equ TCCR1B =$81
.equ TCCR1A =$80
.equ DIDR1
=$7F
.equ DIDR0
=$7E
.equ
.equ
.equ
.equ
.equ
TIMSK1 =$6F
TIMSK0 =$6E
PCMSK2 =$6D
PCMSK1 =$6C
PCMSK0 =$6B
;***** I/O REGISTER DEFINITIONS ($3F-$00) **********************************
.equ SREG
=$3F
.equ SPH
=$3E
.equ SPL
=$3D
.equ SPCR
=$2c
.equ GPIOR2 =$2B
.equ GPIOR1 =$2A
.equ OCR0B
=$28
.equ OCR0A
=$27
.equ TCNT0
=$26
.equ TCCR0B =$25
.equ TCCR0A =$24
.equ PORTD
=$0B
.equ DDRD
=$0A
.equ PIND
=$09
.equ PORTC
=$08
.equ DDRC
=$07
.equ PINC
=$06
.equ PORTB
=$05
.equ DDRB
=$04
.equ PINB
=$03
*C:\Program Files\Atmel\AVR Tools\AvrAssembler\Appnotes
;*****************************************************************************
; Bit Definitions
;*****************************************************************************
; - Port B .equ PORTB7 = 7
; PORTB
.equ PORTB6 = 6
.equ PORTB5 = 5
.equ PORTB4 = 4
.equ PORTB3 = 3
.equ PORTB2 = 2
.equ PORTB1 = 1
.equ PORTB0 = 0
.equ DDB7
.equ DDB6
.equ DDB5
.equ DDB4
.equ DDB3
.equ DDB2
.equ DDB1
.equ DDB0
=7
=6
=5
=4
=3
=2
=1
=0
; DDRB
.equ PINB7
.equ PINB6
.equ PINB5
.equ PINB4
.equ PINB3
.equ PINB2
.equ PINB1
.equ PINB0
=7
=6
=5
=4
=3
=2
=1
=0
; PINB
;**********TIMER_COUNTER_0************
;TCCR0A:
.equ COM0A1 =7
.equ COM0A0 =6
.equ COM0B1 =5
.equ COM0B0 =4
.equ WGM01
=1
.equ WGM00
=0
20
Limited Agenda for Microprocessor
• External Interrupts
– INT (Not covered)
– PCINT (24 different interrupts)
• Internal Interrupts
• Timers / Counters (8-bit)
– Timer (sec)
– Pulse Width Modulation
• Setup of Software / Hardware Tools
21
Interrupts
• Interrupts vs Polling
• Interrupts may lead to serious problems
– Disable interrupts before reading variables
• External Interrupts
– External Interrupt Request (INT0)
– Pin Change Interrupt (PCINT0)
• Internal Interrupts
22
Key Registers: PCINT external interrupts
1. PCMSK# (were # is either 0, 1 or 2)
Bit
7
6
5
4
3
2
1
0
PCMSK2
PCINT 23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
PCMSK1
-
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
2. PCICR
Bit
7
6
5
4
3
2
1
0
0x68
-
-
-
-
-
PCIE2
PCIE1
PCIE0
3. SREG
Bit
7
6
5
4
3
2
1
0
0x3f
I
T
H
S
V
N
Z
C
23
ATmega168 Pins
PDIP
(PCINT14) PC6
(PCINT16)
(PCINT17)
(PCINT18)
(PCINT19)
(PCINT20)
(PCINT6)
(PCINT7)
(PCINT21)
(PCINT22)
(PCINT23)
(PCINT0)
PD0
PD1
PD2
PD3
PD4
VCC
GND
PB6
PB7
PD5
PD6
PD7
PB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5
PC4
PC3
PC2
PC1
PC0
GND
AREF
AVCC
PB5
PB4
PB3
PB2
PB1
(PCINT13)
(PCINT12)
(PCINT11)
(PCINT10)
(PCINT9)
(PCINT8)
(PCINT5)
(PCINT4)
(PCINT3)
(PCINT2)
(PCINT1)
24
1. PCMSK# – Pin Change Mask
Register #
Bit
7
6
5
4
3
2
1
0
PCMSK2
PCINT 23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
PCMSK1
-
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – 0: Pin Change Enable Mask
• Each PCINT# bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT# is cleared, the pin change interrupt on the corresponding I/O pin is
disabled.
If you decided to test for a change on Pin 2, the first thing to do is check the Pin Layout to determine what
PCINT# corresponds to that pin – PCINT16 in this case. Checking the list of registers above, note that
PCINT16 falls on the PCMSK2 register. Enabling a Pin Change interrupt on Pin 2 would consist of:
PCMSK2 = 1<<PCINT16 ;
25
2. PCICR – Pin Change Interrupt
Control Register
Bit
7
6
5
4
3
2
1
0
0x68
-
-
-
-
-
PCIE2
PCIE1
PCIE0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit # – PCIE#: Pin Change Interrupt Enable # where (# is 2, 1, or 0)
• Whet the PCIE# bit is set (one) and the I-bit in the Status Register (SEG) is set (one), pin change
interrupt # is enabled.
• Any change on any enabled pin will cause an interrupt.
• The corresponding interrupt on Pin Change Interrupt Request is executed from the PCI1 interrupt
Vector.
–
–
–
PCIE2 enables PCINT 23 .. 16 pins and are enabled individually by the PCMSK2 register
PCIE1 enables PCINT 14 .. 8 pins and are enabled individually by the PCMSK1 register
PCIE0 enables PCINT 7 .. 0 pins and are enabled individually by the PCMSK0 register
Since you just set register PCMSK2, you now have to enable that register by setting PCIE2 to 1.
PCICR = 1<<PCIE2;
26
3. SREG – AVR Status Register
Bit
7
6
5
4
3
2
1
0
0x3f
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – I: Global Interrupt Enable
• The Global Interrupt Enable bit must be set for the interrupts to be enabled.
• The individual interrupt enable control is then performed in separate control registers.
• If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled
independent of the individual interrupt enable settings.
Finally, you must set the I bit in SREG enabling internal and external interrupts that have been set to
operate. To stop all interrupts, just set SREG_I to 0.
SREG = 1<<SREG_I ;
27
Enabling External Interrupts
The following code enables interrupts on the PCINT16 pin (e.g., pin 2)
SREG = 1<<SREG_I ;
PCICR = 1<<PCIE2;
PCMSK2 = 1<<PCINT16 ;
What do you want to happen after an interrupt is detected?
28
In AVR Studio, select Help -> avr-libc Reference Manual
29
Defining an Interrupt Routines
Vector name
PCINT0_vect
PCINT1_vect
PCINT2_vect
Description
Pin Change Interrupt Request 0
Pin Change Interrupt Request 1
Pin Change Interrupt Request 2
Applicable for device
ATmega162, ATmega165, ATmega165P, ATmega168P, ATmega169,
ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P,
ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406,
ATmega48P, ATmega645, ATmega6450, ATmega649, ATmega6490,
ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640,
ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P,
ATmega164P, ATmega644P, ATmega644, ATtiny13, ATtiny43U, ATtiny48,
ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, AT90USB162,
AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
ATmega162, ATmega165, ATmega165P, ATmega168P, ATmega169,
ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P,
ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406,
ATmega48P, ATmega645, ATmega6450, ATmega649, ATmega6490,
ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640,
ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P,
ATmega164P, ATmega644P, ATmega644, ATtiny43U, ATtiny48, ATtiny24,
ATtiny44, ATtiny84, AT90USB162, AT90USB82
ATmega3250, ATmega3250P, ATmega328P, ATmega3290, ATmega3290P,
ATmega48P, ATmega6450, ATmega6490, ATmega88P, ATmega168,
ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281,
ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P,
ATmega644, ATtiny48
ISR(PCINT2_vect)
{
...
// Code to handle the event.
}
Note that this routine is called whenever pins
PCINT23..16 have logical changes. How do you
determine which pin actually changed?
(Harder than you would think!)
30
Example of External Interrupt
#include <avr/io.h>
#include <avr/interrupt.h>
ISR( PCINT2_vect )
/* Code to execute when external interrupt on PCINT23 .. 16 is triggered by a logic change*/
{
PORTB = PORTB ^ 0x02;
}
int main(void)
{
// Setup for External Interrupt PCINT16 (uses pin 2 or PD0)
SREG = ( 1<<SREG_I );
PCICR = ( 1<<PCIE2 );
PCMSK2 = ( 1<<PCINT16 );
// Enables global interrupts
// Enables vector interrupts on PCINT23 .. 16
// Enables individual interrupt PCINT16 only
DDRB = 1 << PORTB1;
while(1)
;
}
31
Internal Interrupts
VectorNo. Program Address (2) Source
Interrupt Definition
1
0x0000(1)
RESET
External Pin, Power-on Reset, Brown-out
Reset and Watchdog System Reset
2
0x0002
INT0
Externa l Interrupt Reques t 0
3
0x0004
INT1
Externa l Interrupt Reques t 1
4
0x0006
PCINT0
Pi n Cha nge Interrupt Reques t 0
5
0x0008
PCINT1
Pi n Cha nge Interrupt Reques t 1
6
0x000A
PCINT2
Pi n Cha nge Interrupt Reques t 2
7
0x000C
WDT
Wa tchdog Ti me-out Interrupt
8
0x000E
TIMER2 COMPA Ti mer/Counter2 Compa re Ma tch A
9
0x0010
TIMER2 COMPB Ti mer/Counter2 Compa re Ma tch B
10
0x0012
TIMER2 OVF
Ti mer/Counter2 Overfl ow
11
0x0014
TIMER1 CAPT
Ti mer/Counter1 Ca pture Event
12
0x0016
TIMER1 COMPA Ti mer/Counter1 Compa re Ma tch A
13
0x0018
TIMER1 COMPB Ti mer/Coutner1 Compa re Ma tch B
14
0x001A
TIMER1 OVF
15
0x001C
TIMER0 COMPA Ti mer/Counter0 Compa re Ma tch A
16
0x001E
TIMER0 COMPB Ti mer/Counter0 Compa re Ma tch B
17
0x0020
TIMER0 OVF
Timer/Counter0 Overflow
18
0x0022
SPI, STC
SPI Seri a l Tra ns fer Compl ete
19
0x0024
USART, RX
USART Rx Compl ete
20
0x0026
USART, UDRE
USART, Da ta Regi s ter Empty
21
0x0028
USART, TX
USART, Tx Compl ete
22
0x002A
ADC
ADC Convers i on Compl ete
23
0x002C
EE READY
EEPROM Rea dy
24
0x002E
ANALOG COMP
Ana l og Compa ra tor
25
0x0030
TWI
2-wi re Seri a l Interfa ce
26
0x0032
SPM READY
Store Progra m Memory Rea dy
Ti mer/Counter1 Overfl ow
32
Timers/Counter
• Most commonly used complex peripherals
• Think of them as binary up-counters
– In timing mode, count time periods
– In counting mode, counting events or pulses
• 8-bit and 16-bit Timers available
– ATmega168
• Timer/Counter 0
– 8-bit Timer/Counter with Prescaler
– Two PWM Channels
• Timer/Counter 1
– 16-bit High Speed Timer/Counter with Separate Prescaler
– 2 High Frequency PWM Outputs
• Timer/Counter 2
– 8-bit Timer/Counter with Prescaler
– Two PWM Channels
33
Normal Mode
• High Frequency
• Single Slope
• Counter Counts only
from Bottom to Top
Top (0xFF)
Timer/Counter
Register n
(TCNTn)
Bottom (0x00)
Trips Timer/Counter Overflow Flag
34
Key Registers to enable Timer
1. TCCR0A
Bit
0x24
2. TCCR0B
Bit
0x25
3. TIMSK0
Bit
0x25
4. TIFR0
– Timer/Counter0 Control Register A
7
6
5
4
COM0A1 COM0A0 COM0B1 COM0B0
3
2
-
-
1
0
WGM01 WGM00
– Timer/Counter0 Control Register B
7
6
FOC0A FOC0B
5
4
-
-
3
2
WGM02 CS02
1
0
CS01
CS00
– Timer/Counter Interrupt Mask Register
7
6
FOC0A FOC0B
5
4
3
2
1
0
-
-
WGM02
CS02
CS01
CS00
– Timer/Counter Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
0x25
-
-
-
-
-
OCF0B
OCF0A
TOV0
35
1. TCCR0A Register
Bit
0x24
7
6
5
4
COM0A1 COM0A0 COM0B1 COM0B0
3
2
-
-
1
0
WGM01 WGM00
Bit 1-0 : Waveform Generation Mode
• Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source of the maximum (TOP) counter value, and what type of waveform
generation to be used.
Timer/Counter
Mode of Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Mode
WGM02
WGM01
WGM00
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
5
1
0
1
PWM, Phase Correct
OCRA
TOP
BOTTOM
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
Set for Normal Mode (Note we still have to set WGM02 in the TCCR0B Register.)
TCCR0A = (0<<WGM00);
36
2. TCCR0B Register
Bit
7
0x25
6
5
4
3
2
1
0
-
-
WGM02
CS02
CS01
CS00
FOC0A FOC0B
Bit 3 : Waveform Generation Mode
• Use table from previous slide
Timer/Counter
Mode of Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Mode
WGM02
WGM01
WGM00
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
5
1
0
1
PWM, Phase Correct
OCRA
TOP
BOTTOM
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
Setting for Phase Correct PWM
TCCR0B = (0<<WGM02);
37
2. TCCR0B Register (Continued)
Bit
0x25
7
6
FOC0A FOC0B
5
4
3
2
1
0
-
-
WGM02
CS02
CS01
CS00
Bit 2:0 : Clock Select
• These bits select the clock source to be used by the Timer/Counter
CS02
CS01
CS00
Description
0
0
0
No clock source (Timer/Counter stopped)
0
0
1
clkI/O/(No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
Depends on the Frequency needed. We’ll choose no prescaler.
TCCR0B = (0<<WGM02) | (1<<CS00);
38
3. TIMSK0 Register
Bit
7
6
5
4
3
2
1
0
0x25
-
-
-
-
-
OCIE0B
OCIE0A
TOIE0
Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
• When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0
Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register –
TIFR0.
Enabling Timer/Counter Overflow Interrupt
TIMSK0= (1<<TOIE0);
39
4. TIFR0 Register
Bit
7
6
5
4
3
2
1
0
0x25
-
-
-
-
-
OCF0B
OCF0A
TOV0
Bit 0 - TOV0: Timer/Counter0 Overflow Flag
• The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic
one to the flag. When the SREG I-bit, TOIE0, and TOV0 are set, the Timer/Counter0 Overflow
interrupt is executed.
(The setting of this flag is dependent on the WGM02:0 bit settings. Refer to the previous table)
Clear the Timer/Counter Overflow flag (e.g., initiate the overflow counter)
TIFR0 = (1<<TOV0);
40
Internal Interrupt
Timer/Counter0 Overflow
1.
2.
3.
4.
Select avr-libc Reference Manual
Choose Library Reference
Identify Module to include in code
Click on Module
41
Internal Interrupt
(Continued)
5. Find Correct Interrupt
Vector
6. Write Code to be
executed upon the
interrupt
ISR ( ?_vect)
{
//place code to be executed on this interrupt
}
42
PWM Modes
Fast PWM Mode
• High Frequency
• Single Slope
•Counter Counts only
from Bottom to Top
• Suited for power regulation,
rectification, and DAC
application
Phase Correct PWM Mode
• Lower Frequency
• Dual Slope
•Counter Counts up the
down
• Suited for motor control
applications
Top (0xFF)
OCROx Value
Timer/Counter
Register n
(TCNTn)
Bottom (0x00)
OCn
OCn
Period
1
2
3
4
5
6
7
Top (0xFF)
OCROx Value
TCNTn
Bottom (0x00)
OCn
OCn
Period
1
2
3
43
Phase Correct PWM
Timer/Counter 0 (8-bit)
• Set Frequency
– Prescaler
fOCnxPWM 
fclk _ I /O
N  (1  TOP)
N is prescaler divider (1, 8, 64, 256 or 1024)
• Determine Bit Resolution
RPCPWM 
log(TOP  1)
log  2 
• Set Duty Cycle
– Determined by OCR0x
44
ATmega168 Pins
PDIP
PC6
PD0
PD1
PD2
(OC2B) PD3
PD4
VCC
GND
PB6
PB7
(OC0B) PD5
(OC0A) PD6
PD7
PB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5
PC4
PC3
PC2
PC1
PC0
GND
AREF
AVCC
PB5
PB4
PB3 (OC2A)
PB2 (OC1B)
PB1 (OC1A)
45
Key Registers to enable Phase Correct PWM
1.
2.
3.
TCCR0A
–
Timer/Counter0 Control Register A
Bit
7
6
5
4
3
2
1
0
0x24
COM0A1
COM0A0
COM0B1
COM0B0
-
-
WGM01
WGM00
TCCR0B
–
Timer/Counter0 Control Register B
Bit
7
6
5
4
3
2
1
0
0x25
FOC0A
FOC0B
-
-
WGM02
CS02
CS01
CS00
OCR0x
–
Output Compare Register x
An 8-bit Register where x stands for either A or B.
e.g., Timer 0 has Output on PD6 (Pin 12) for OC0A and PD5 (Pin 11) for OC0B
We’ll use A for our example.
46
1. TCCR0A Register
Bit
7
0x24
6
5
4
COM0A1 COM0A0 COM0B1 COM0B0
3
2
-
-
1
0
WGM01 WGM00
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7- 6 : Compare match Output A Mode
• These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A0:1 bits are
set, the 0C0A output overrides the normal port functionality of the I/0 pin it is connected to.
• Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set
to enable the output driver
COM0A1
COM0A0
0
0
Normal port operation, OC0A disconnected.
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
0
Clear OC0A on Compare Match when up-counting. Set
OC0A on Compare Match when down-counting.
1
Set OC0A on Compare Match when up-counting. Clear
OC0A on Compare Match when down-counting.
0
1
1
We’ll set COMOA to 3.
Description
TCCR0A = (3<<COMOA0);
47
1. TCCR0A Register (Continued)
Bit
0x24
7
6
5
4
COM0A1 COM0A0 COM0B1 COM0B0
3
2
-
-
1
0
WGM01 WGM00
Bit 1-0 : Waveform Generation Mode
• Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source of the maximum (TOP) counter value, and what type of waveform
generation to be used.
Timer/Counter
Mode of Operation
TOV Flag
Set on(1)(2)
Mode
WGM02
WGM01
WGM00
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
5
1
0
1
PWM, Phase Correct
OCRA
TOP
BOTTOM
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
Set for Phase Correct PWM
TOP
Update of
OCRx at
(Note we still have to set WGM02 in the TCCR0B Register.)
TCCR0A = (3<<COMOA0) | (1<<WGM00);
48
2. TCCR0B Register
Bit
7
0x25
6
5
4
3
2
1
0
-
-
WGM02
CS02
CS01
CS00
FOC0A FOC0B
Bit 3 : Waveform Generation Mode
• Use table from previous slide
Timer/Counter
Mode of Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Mode
WGM02
WGM01
WGM00
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
5
1
0
1
PWM, Phase Correct
OCRA
TOP
BOTTOM
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
Setting for Phase Correct PWM
TCCR0B = (0<<WGM02);
49
2. TCCR0B Register (Continued)
Bit
0x25
7
6
FOC0A FOC0B
5
4
3
2
1
0
-
-
WGM02
CS02
CS01
CS00
Bit 2:0 : Clock Select
• These bits select the clock source to be used by the Timer/Counter
CS02
CS01
CS00
Description
0
0
0
No clock source (Timer/Counter stopped)
0
0
1
clkI/O/(No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
Depends on the Frequency needed. We’ll choose a prescaler of 8.
TCCR0B = (0<<WGM02) | (2<<CS00);
50
3. OCR0A Register
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
Interrupt, or to generate a waveform output on the OC0A pin.
For PWM, this will be how you set the duty cycle by setting it equal to the duty cycle times
to TOP value. For example, to set this to a 50% duty cycle for our example,
OC0A  0.50*255
 128
Or, we can let the computer do the math!
TCCR0A = (3<<COMOA0) | (1<<WGM00);
TCCR0B = (0<<WGM02) | (2<<CS00);
OC0A = (unsigned int) 0.50 * 255;
51
Arithmetic Operators
52
Data Access and Size Operators
53
Miscellaneous Operators
54
Relational & Logical Operators
55
Bitwise Operators
AND
OR
XOR
0&0=0
0|0=0
0^0=0
0&1=0
0|1=1
0^1=1
1&0=0
1|0=1
1^0=1
1&1=1
1|1=1
1^1=0
56
Steps to Programming
1. Write Program (AVR Studio)
a) Write Code (One module at a time!)
b) Debug in Simulator mode*
c) Create .hex code
2. Transfer code to Chip
a) Connect USB Programmer (AVRISP MKII)
to computer and breadboard
b) Use AVR Studio to download program
3. Place chip in final position and run
*Turn off the compiler's optimization for debugging.
57
AVR Studio 4.13
Select New Project
58
Create a new Project
1.
2.
3.
4.
Select AVR GCC for programming in C
Select Project Name (no spaces)
Set Location to your folder
Click “Next”
59
1. Use “AVR Simulator”
2. Select “ATmega168”
3. Click “Finish”
60
Create the Code
1. Enter Code
2. Select “Build”
3. Choose “Debug”
61
Debug Program
Walk through code,
watch settings for
PORTB, DDRB,
and PINB in lower
right pane.
Note: LED lights
up when PB4 is “off”
62
Setup Breadboard for
Programming ATmega168
Connect USB Programmer to computer and 6-pin header to breadboard
63
Atmel’s AVRISP mkII
USB ISP
LED Color
Description
Red
Idle – No target power
Green
Idle – With target power
Orange
Busy – Programming
Orange blinking
Reversed target cable connection, or
not correct pull-up on the reset line.
Red blinking
Short-circuit on target
Red-Orange
blinking
Upgrade mode
There is also a green LED inside the AVRISP mkII enclosure next to the
USB connector. This LED indicates USB traffic
64
Make Connection to AVRISP mkII
Click “Connect”
65
Make Connection to AVRISP mkII
Select “AVRISP mkII”
and click “Connect…”
66
Verify Parameters (1/3)
1. Correct Device
2. Select ISP Frequency > 5K
(Caution: too high and it won’t transfer)
67
Verify Parameters (2/3)
De-select CKDIV8
(divides clock by 8)
Be sure to select the
Internal clock as selecting
an external may lock-up the
device until you connect
an oscillator.
68
Verify Parameters (3/3)
Set Path to HEX file
69
Download Program
70
Structure of Code
//Definitions
#define THRESHOLD
125
/* Light Threshold */
In this Order!
//Global Variables
int speed
//Functions
void motor (int mtr, int speed)
{
…
}
//Behaviors
void behaviors()
{
…
}
//Main
void main ()
{
…
}
71