Transcript Institute Lecture Series Talk

The Art and Science of VLSI Chip Design:
Bridging the Analog(ue) and Digital Worlds
Dr. Subhajit Sen
DA-IICT, Gandhinagar
The “Digital Divide”
Analog(ue)
or Physical Or
Real World
Digital
Or Computer
Or Virtual
World
Some statements About Analog vs. Digital
• My 3G phone sounds better than your 2G phone
• A “Digital” equipment/instrument is superior to analog
equipment
• A “Digital” camera gives better picture quality than a film
camera
• Analog electronic circuits are more complex: require more
components than digital ones
• Analog equipments consumes more power than “digital”
ones
• Analog electronic circuits are harder to design than digital
ones
• Nobody designs analog circuits/instruments any more
The Analog World
The Analog vs. Digital Signal
• Infinite precision in amplitude and time axes
• Absolute vs. relative “one” and “zero” in a digital signal
• A digital signal is often “coded”
(0 second, 2 Volt)
10111 10110 10101 01101 11…
(1 second, -1 Volt)
Stages of Progression from Analog to
Digital
• Sampling:
– taking instantaneous time snapshots of
changing phenomena
• Quantization
– Rounding off to integer or sub-integer
amplitude intervals
• Coding
– Binary encoding, compression
Information Rate while Sampling
d
v
Rate =
v
d
Minimum Sampling Rate
d’
v
Minimum Sampling Rate =
v
d’
Aliasing in sampled phenomena
Aliasing in continuous-time signal
• Leads to information loss (or rather misinformation)
• Sampled sequence: 0.6, 0.9, 0.9, …
Information rate or “Bandwidth”
• Any phenomenon should be sampled at twice
the bandwidth(or information rate) of the
phenomenon
– Sampling Rate = 2 X Bandwidth
• Any information rate change higher than the
bandwidth leads to “aliasing” and loss of
information
Interpolation
•
•
•
Needed for signal reconstruction
Computation of predicted values
Circuit needed to generate interpolated timeinstants
Quantization
• Inherently lossy
• Needs accurate voltage reference
• Typically combined with binary coding in circuits
1.00 V
0.75
0.5
0.25
0
-1.00
-0.75
-0.5
-0.25 V
Coding
• Binary encoding
• Inherent part of analog-digital converters/codecs
1.00
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1.00
0100
0011
0010
0001
0000
1100
1011
1010
1001
Coding: compression
• More frequently used numbers or number
sequences are encoded with short code words
and vice-versa
• Analogy with text message abbreviations:
– “Wud b late 2nite, b4 12, 2 much wrk, lv”
– “AFAIK he is frm Thiruvananthapuram”
• Information loss
Ideal Sampling
Capacitor
00110 10111 11111 10010
A Sampling Circuit
Clock
Capacitor
Track-and-Hold Circuit
• Can use MOS transistor as switch
Clock
Capacitor
Sample-and-Hold circuit
• Bandwidth reduction necessary to avoid aliasing
• Inaccuracies: gain-error, distortion error,noise
Anti-alias
Filter
T& H
T& H
Capacitor
00110 10111 11111 10010
From Analog signal to Digital Codes
• Anti-alias filtering
• Sample-and-Hold
• Quantization/Coding
clock
ADC
Anti-alias
SampleFilter/Amplifier
And-Hold
Reference voltage
10110 11011 1..
Encoder
Analog Re-construction
• Decoder
• Reconstruction filter
Reference voltage
10110 10111…
Decoder
Digital samples
DAC
Re-construction
Filter
Analog-Digital converter in VLSI chip
VLSI Chip
Analog
or Physical
Or Real
World
Reference
Clock
Reference
Voltage
ADC
Anti-alias
SampleFilter
And-Hold
Encoder
Digital
Or Computer
OrDigital
Virtual World
10110100…
Or Computer
Or Virtual World
DAC
Analog-Digital conversion
“Raw” Analog Signal
Low-pass (anti-alias)
filtering
Sampling and quantization
Coding
00110 10111 11111 10010..
Clock Frequency Accuracy
• Analog information is preserved ONLY if the clock
frequency is accurate
• Time period of an “on-chip” oscillator is governed by
resistor/capacitor component values: R*C or L*C
• Very wide manufacturing variations in frequency if R
and C components are INSIDE the chip: upto 40%
Reference Clock
• Crystal Oscillator: Electronic tuning fork
– Extremely accurate & stable clocks possible: fews
seconds/year
– Eric Vittoz
– The Swiss connection
Crystal Oscillator
Reference Clock sub-division
• Synchronization circuits or phase-locked-loops
• Henri Bellescize
• Arbitrary sub-division of clock is possible
Analog re-construction
• Interpolation involves digital computations
• A PLL (phase-locked-loop) can give sub-divided clock
Accuracy: Reference Voltage Sub-division
• Very accurately matched components possible “on-chip”
• Possible to improve precision using “calibration”
1.00
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1.00
0100
0011
0010
0001
0000
1100
1011
1010
1001
Reference Voltage
• Analog information is preserved ONLY if the
reference voltage is accurate
• Need an accurate “battery” on-chip
• Use physical property of silicon:
– Band-gap of silicon is 1.1 electron Volt at 0 degree Kelvin
– Possible to design “on-chip” circuits to extract this voltage
Conduction Band
Bandgap=1.1 eV
Valence Band
Analog De-mystified
(Complexity)
An analog multiplier
A digital floating-point multiplier
Analog De-mystified
(Complexity)
Analog FM radio
With antenna
“Digital” Radio
Analog De-mystified
(Why Analog chip design is Hard)
• Digital Scaling: supply voltage going down
• Noise is a indispensable part of analog circuits
• Signal to Noise ratio reduces
5V supply
more
headroom
less
1V supply
Old Analog Systems
Modern VLSI Systems
Analog De-mystified
(Why Analog chip design is Hard)
•
•
•
•
Digital Scaling: supply voltage going down
Transistor non-linearity governed by voltage head-room
Lesser the head-room more the distortion
Signal to distortion ratio decreases
5V supply
1V supply
Old Analog Systems
Modern VLSI Systems
Chip Design at DA-IICT
• A sample-and-Hold circuit with a back-end
“sigma-delta” ADC designed and fabricated
• 180nm CMOS
• 2 iterations:
– first version had a bug
– Second has been tested for functionality
• Testing issues
Sample-and-Hold Circuit designed at
DA-IICT (180nm CMOS)
Sample-and-Hold Circuit designed at
DA-IICT (180nm CMOS)
OP-AMP
(A1)
Clock_gen
OP-AMP
(A2)
CLF=2 pF
Cb=5 pF
Cs=10 pF
Sigma-Delta ADC designed at DA-IICT
(180nm CMOS)
Measurement waveforms on Chip
Design at DA-IICT
Conclusion:
Is Digital Really Better Than Analog
• Not always. Any signal transformation to digital
domain always involves information loss due to
aliasing, quantization and coding. If the signal source
characteristics are not well known or power
consumption is an issue use analog signal processing.
• However, once analog signals are converted to
digital domain they can be stored and transmitted
without much degradation i.e. digital circuits are
much more robust against noise and distortion when
stored or transmitted.
Thank You
The Art and Science of VLSI Chip Design:
Bridging the Analog and Digital Worlds
Modern VLSI chip based computers become interesting only when interfaced
with the analog real world of continuous-time signals using analog signal- processing
circuits that convert from continuous-time
signals to coded bits. This talk will explain the methods (algorithms) and circuit techniques
of this conversion based upon the sound principles of information-theoretic principles of
sampling,aliasing, quantization and coding. It will also be explained how a crystal-oscillato
attached to the chip pins and the silicon “band-gap” voltage reference inside the chip play
crucial role in preserving the accuracy of analog information inside a VLSI chip. The talk
also explains the relative merits of analog and digital processing of real world signals.
The talk then attempts to answer the critical question: given the increasing cost and
complexity of chip design how much of digital processing is really necessary in electronic
gadgets and instruments that sense, process, store and transmit real world analog signals
Importance of Sinusoids
• Fourier (spectrum) analysis
• Analog Circuit distortion is detectable
Over-sampling and decimation
• To reduce aliasing we may sample at a rate
higher than twice the signal bandwidth
• Can reduce the sample rate at any later stage
by discarding samples (decimation)
– Need to reduce information rate using an antialias filter
Coding: crytography
“PvUmQ”
“cAokadfofadsfxcliy”
“I won one crore lottery”
Computer
• Key
• Loss of key leads to loss of entire message