Transcript CPU bus - 國立清華大學資訊工程系

Chapter 4
The Embedded Computing
Platform
金仲達教授
清華大學資訊工程學系
(Slides are taken from the textbook slides)
Outline
CPU Bus and DMA
 Memory and I/O Devices
 Component Interfacing
 Designing with Microprocessors
 Development, Debugging, Testing
 Design Example: Alarm Clock

Computing Platform-1
CPU bus
Connects CPU to memory and device
 Bus protocol controls communication between
entities




decides who gets to use bus at any particular time
governs length, style of communication
Four-cycle handshake:


Basis of many bus protocols
2 wires: enq (enquiry) and ack (acknowledgment)
enq
dev1
data
dev2
ack
Computing Platform-2
Four-cycle example
enq
1
3
2
data
4
ack
time
Computing Platform-3
Typical bus signals
Clock
 R/W’: true when bus is reading
 Address: a-bit bundle
 Data: n-bit bundle
 Data ready’

Device 1
Device 2
Clock
R/W’
Address
Data ready’
Data
CPU
Memory
Computing Platform-4
Timing diagrams
one
A
zero
rising
10 ns
falling
stable
B
changing
timing
constraint
C
time
Computing Platform-5
Typical bus timing
Computing Platform-6
Transaction types

Wait state:


Disconnected transfer:



state in a bus transaction to wait for acknowledgment
bus is freed during wait state
request and response are separate
Burst:


multiple transfers
need an extra line called burst’
Computing Platform-7
Computing Platform-8
DMA

Direct Memory Access: a bus operation not
controlled by CPU


Controlled by DMA controller (a bus master)
2 additional wires

Bus request & Bus grant
bus grant
DMAC
Device
bus request
CPU
Memory
Computing Platform-9
DMA Operation

CPU controls DMA operation with 3 registers in
DMAC




Starting address register
Length register
Status register
DMAC operation mode:


Burst mode: CPU stalls until I/O completes
Cycle-stealing mode: DMAC releases bus after each
unit of transfer
Computing Platform-10
System Bus Configuration

The bridge:


A slave on the fast bus
The master of the slow bus
Low-speed
Device
CPU
Memory
High-speed
device
low-speed
bus
Bridge
high-speed
bus
Low-speed
Device
Computing Platform-11
ARM Bus
AMBA
high-performance bus (AHB)
SRAM
ARM
CPU
Bridge
External
DRAM
controller
Low-speed
I/O device
High-speed
I/O
device
Low-speed
I/O device
AMBA
peripherals bus (APB)
System-on-Chip
Computing Platform-12
Outline
CPU Bus and DMA
 Memory and I/O Devices
 Component Interfacing
 Designing with Microprocessors
 Development, Debugging, Testing
 Design Example: Alarm Clock

Computing Platform-13
RAM: Random-Access Memory

SRAM (Static RAM) and DRAM (Dynamic RAM)


DRAM: values must be periodically refreshed;
addressed by row and column addresses
Page mode, synchronous DRAM, video RAM
CE’
R/W’
Adrs
Data
SRAM
CE’
R/W’
RAS’
CAS’
Adrs
Data
DRAM
Clock
CE’
R/W’
RAS’
CAS’
Adrs
Data
SDRAM
Computing Platform-14
Page mode
Computing Platform-15
ROM: Read-Only Memory
Factory-programmed ROM
 Field-programmed ROM (with ROM burners)




Antifuse-programmable ROM (programmed once)
UV-erasble PROM (aka UV-EPROM) (multiple times)
Flash PROM: modern form of EPROM


Old time: need to be removed from the system and
must be erased in entirety
Current time: can be upgraded inside the system and
erased in blocks (aka boot-block flash)
Computing Platform-16
Timers and counters

Very similar:


a timer is incremented by a periodic signal;
a counter is incremented by an asynchronous,
occasional signal.
Rollover causes interrupt
 Watchdog timer:



Periodically reset by system timer
If is not reset, an interrupt to reset the host
interrupt
host CPU
reset
watchdog
timer
Computing Platform-17
A/D and D/A converters

Analog/digital converter (ADC)



Sampling the analog input before converting it to
digital form
Triggered by a control signal
Digital/analog converter (DAC)
R
Vin
bn
encoder
bn-1
bn-2
...
Vout
2R
4R
8R
bn-3
Computing Platform-18
Keyboards
An array of switches
 Switch debouncing:


A switch must be debounced to multiple contacts
caused by eliminate mechanical bouncing
Computing Platform-19
Encoded keyboard

An array of switches is read by an encoder


row address and column output used for encodong
N-key rollover remembers multiple key
depressions.
row
scan
Computing Platform-20
LED

Must use resistor to limit current:

An on LED has only 0.7V voltage drop
digital
logic
current-limiting
resistor
LED
Computing Platform-21
7-segment LCD display

May use parallel or multiplexed input.
Computing Platform-22
Types of high-resolution display
Cathode ray tube (CRT)
 Liquid crystal display (LCD)
 Plasma, etc.

Computing Platform-23
Touchscreen
Includes input and output device.
 Input device is a two-dimensional voltmeter for
position sensing:

ADC
voltage
Computing Platform-24
Outline
CPU Bus and DMA
 Memory and I/O Devices
 Component Interfacing
 Designing with Microprocessors
 Development, Debugging, Testing
 Design Example: Alarm Clock

Computing Platform-25
Example interfacing memory
Computing Platform-26
Example interfacing device
Computing Platform-27
Outline
CPU Bus and DMA
 Memory and I/O Devices
 Component Interfacing
 Designing with Microprocessors
 Development, Debugging, Testing
 Design Example: Alarm Clock

Computing Platform-28
Designing with microprocessors

Architectures and components:


software;
hardware.
Debugging.
 Manufacturing testing.

Computing Platform-29
Hardware platform architecture

There are several components in HW





CPU
bus
memory
I/O devices: networking, sensors, actuators, etc.
How to implement an embedded system using
these components?
Computing Platform-30
Software architecture

Functional description must be broken into
pieces – partitioning





division among people
conceptual organization
performance
testability
maintenance
Software doesn’t run without hardware
 How much hardware you need is determined by
the software requirements



speed
memory
Computing Platform-31
Evaluation boards
Designed by CPU manufacturer or others
 Includes CPU, memory, some I/O devices
 May include prototyping section
 CPU manufacturer often gives out evaluation
board (e.g., EV board)


can be used as starting point for your custom board
design.
Computing Platform-32
Adding logic to a board

Programmable logic devices (PLDs)


Field-programmable gate arrays (FPGAs)


provide low/medium density logic
provide more logic and multi-level logic
Application-specific integrated circuits (ASICs)
are manufactured for a single purpose
Computing Platform-33
The PC as a platform

Advantages:



cheap and easy to get
rich and familiar software environment
Disadvantages:


requires a lot of hardware resources
not well-adapted to real-time
Computing Platform-34
Typical PC hardware platform
CPU
memory
CPU bus
intr
ctrl
DMA
controller
bus
interface
device
high-speed bus
timers
bus
interface
low-speed bus
device
Computing Platform-35
Typical PC busses

ISA (Industry Standard Architecture)


PCI: standard for high-speed interfacing



original IBM PC bus, low-speed by today’s standard
33 or 66 MHz
264 MB/sec or 524 MB/sec
USB (Universal Serial Bus), Firewire, 1394

relatively low-cost serial interface with high speed
Computing Platform-36
Software elements

IBM PC uses BIOS (Basic I/O System) to
implement low-level functions:



boot-up;
minimal device drivers.
BIOS has become a generic term for the lowestlevel system software.
Computing Platform-37
Example: StrongARM SA-1100 (1/2)

StrongARM SA-1100 system includes:


CPU chip (3.686 MHz clock)
system control module (32.768 kHz clock)
Real-time clock
 operating system timer
 general-purpose I/O
 interrupt controller
 power manager controller
 reset controller

Computing Platform-38
Example: StrongARM SA-1100 (2/2)
ARM
CPU
core
3.686 MHz clock
32.768 kHz clock
System
control
module
system bus
Bridge
peripheral bus
Computing Platform-39
Outline
CPU Bus and DMA
 Memory and I/O Devices
 Component Interfacing
 Designing with Microprocessors
 Development, Debugging, Testing
 Design Example: Alarm Clock

Computing Platform-40
Host vs. Target
Host: a PC or workstation for development
 Target: the HW on which the code will run
 Cross-compiler: one that runs on host but
generates code for target

serial
port
Host system
CPU
Target system
Computing Platform-41
Debugging embedded systems

Challenges:




target system may be hard to observe
target may be hard to control
may be hard to generate realistic inputs
setup sequence may be complex
Computing Platform-42
Software debuggers
A monitor program residing on target provides
basic debugger functions
 Debugger should have a minimal footprint in
memory
 User program must be careful not to destroy
debugger program, but , should be able to
recover from some damage caused by user code

Computing Platform-43
Breakpoints
A breakpoint allows the user to stop execution,
examine system state, and change state.
 Replace the breakpointed instruction with a
subroutine call to the monitor program.
 Breakpoint handler actions:




Save registers.
Allow user to examine machine.
Before returning, restore system state.
Safest way to execute the instruction is to replace it
and execute in place.
 Put another breakpoint after the replaced breakpoint to
allow restoring the original breakpoint.

Computing Platform-44
ARM breakpoints
0x400
0x404
0x408
0x40c
MUL r4,r6,r6
ADD r2,r2,r4
ADD r0,r0,#1
B loop
uninstrumented code
0x400
0x404
0x408
0x40c
MUL r4,r6,r6
ADD r2,r2,r4
ADD r0,r0,#1
BL bkpoint
code with breakpoint
Computing Platform-45
In-circuit emulators (a.k.a. ICE)

A microprocessor in-circuit emulator is a speciallyinstrumented microprocessor



Inside ICE, there is a special version of the microprocessor that
allows its internal registers to be read out when stopped
This special CPU provides as much debugging functionality as a
debugger (SW) but does not take out any memory
Disadvantage: one ICE (expensive) is specific to one
particular microprocessor (down to pinout)
Computing Platform-46
Logic analyzers

A logic analyzer is an array of low-grade
oscilloscopes:
Computing Platform-47
Logic analyzer architecture
sample
memory
UUT
system clock
microprocessor
vector
address
controller
clock
gen
state or
timing mode
keypad
display
Computing Platform-48
Code verification

Instruction-level simulator





Cycle-level simulator


a.k.a. CPU simulator
down to the details in the programming model
NOT simulate the actions of bus or I/O devices
ARM and SHARC have such simulator
To simulate HW operation of a computer
Hardware/software co-simulator


Most common type of co-verification
Consists of both HW and SW simulator
Computing Platform-49
How to exercise code
Run on host system.
 Run on target system.
 Run in instruction-level simulator.
 Run on cycle-accurate simulator.
 Run in hardware/software co-simulation
environment.

Computing Platform-50
Manufacturing testing
Goal: ensure that manufacturing produces
defect-free copies of the design.
 Can test by comparing unit being tested to the
expected behavior.



But running tests is expensive.
Maximize confidence while minimizing testing
cost.
Computing Platform-51
Testing concepts

Yield: proportion of manufactured systems that
work.



Proper manufacturing maximizes yield.
Proper testing accurately estimates yield.
Field return: defective unit that leaves the
factory.
Computing Platform-52
Faults
Manufacturing problems can be caused by many
thing.
 Fault model: model that predicts effects of a
particular type of fault.
 Fault coverage: proportion of possible faults
found by a set of test.


Having a fault model allows us to determine fault
coverage.
Computing Platform-53
Software vs. hardware testing

When testing code, we have no fault model.



We verify the implementation, not the manufacturing.
Simple tests (e.g., ECC) work well to verify software
manufacturing.
Hardware requires manufacturing tests in
addition to implementation verification.
Computing Platform-54
Hardware fault models

Stuck-at 0/1 fault model:

output of gate is always 0/1.
0 1
0
Computing Platform-55
Combinational testing
Every gate can be stuck-at-0, stuck-at-1.
 Usually test for single stuck-at-faults.




One fault at a time.
Multiple faults can mask each other.
We can generate a test for a gate by:


controlling the gate’s input;
observing the gate’s output through other gates.
Computing Platform-56
Sequential testing
A state machine is combinational logic +
registers.
 Sequential testing is considerably harder.



A single stuck-at fault affects the machine on every
cycle.
Fault behavior on one cycle can be masked by same
fault on other cycles.
Computing Platform-57
Scan chains

A scannable register operates in two modes:



normal;
scan---forms an element in a shift register.
Using scan chains reduces sequential testing to
combinational testing.


Unloading/unloading scan chain is slow.
May use partial scan.
Computing Platform-58
Test generation
Automatic test pattern generation (ATPG)
programs: produce a set of tests given the logic
structure.
 Some faults may not be testable---redundant.


Timeout on a fault may mean hard-to-test or
untestable.
Computing Platform-59
Boundary scan

Simplifies testing of multiple chips on a board.

Registers on pins can be configured as a scan chain.
Computing Platform-60
Outline
CPU Bus and DMA
 Memory and I/O Devices
 Component Interfacing
 Designing with Microprocessors
 Development, Debugging, Testing
 Design Example: Alarm Clock

Computing Platform-61
Alarm clock interface
Alarm on
Alarm off
buzzer
PM
Alarm
ready
light
set
time
set
alarm
hour minute
button
Computing Platform-62
Operations
Set time: hold set time, depress hour, minute.
 Set alarm time: hold set alarm, depress hour,
minute.
 Turn alarm on/off: depress alarm on/off.

Computing Platform-63
Alarm clock requirements
name
purpose
inputs
outputs
functions
alarm clock
24-hour digital clock with one alarm
set time, set alarm, hour, minute, alarm on/off
four-digit display, PM indicator, alarm ready, buzzer
keep time, set time, set alarm, turn alarm on/off,
activate buzzer by alarm
performance
hours and digits, no seconds; not high precision
manufacturing consumer product
cost
power
AC
physical
fits on stand
size/weight
Computing Platform-64
Alarm clock class diagram
1
Lights*
1
Display
1
1
1
Mechanism
1
1
Buttons*
Speaker*
1
Computing Platform-65
Alarm clock physical classes
Lights*
Buttons*
digit-val()
digit-scan()
alarm-on-light()
PM-light()
set-time(): boolean
set-alarm(): boolean
alarm-on(): boolean
alarm-off(): boolean
minute(): boolean
hour(): boolean
Speaker*
buzz()
Computing Platform-66
Display class
Display
time[4]: integer
alarm-indicator: boolean
PM-indicator: boolean
set-time()
alarm-light-on()
alarm-light-off()
PM-light-on()
PM-light-off()
Computing Platform-67
Mechanism class
Mechanism
Seconds: integer
PM: boolean
tens-hours, ones-hours: boolean
tens-minutes, ones-minutes: boolean
alarm-ready: boolean
alarm-tens-hours, alarm-ones-hours:
boolean
alarm-tens-minutes, alarm-ones-minutes:
boolean
scan-keyboard()
update-time()
Computing Platform-68
Update-time behavior
update seconds
with rollover
Rollover?
display.set-time(current time)
F
Time >= alarm and alarm-on?
T
update hh:mm
with rollover
AM->PM
PM=true
F
T
alarm.buzzer(true)
PM->AM
PM=false
Computing Platform-69
Scan-keyboard behavior
compute button activations
alarm-ready=
true
alarm-ready=
false
alarm.buzzer(false)
Alarm-on
Alarm-off
save button
states
Set-time and
not set-alarm
and hours
Increment time
tens w. rollover
and AM/PM
Increment time
ones w. rollover
and AM/PM
Set-time and
not set-alarm
and minutes
Computing Platform-70
System architecture

Includes:



periodic behavior (clock);
aperiodic behavior (buttons, buzzer activation).
Two major software components:


interrupt-driven routine updates time;
foreground program deals with buttons, commands.
Computing Platform-71
Interrupt-driven routine
Timer probably can’t handle one-minute
interrupt interval.
 Use software variable to convert interrupt
frequency to seconds.

Computing Platform-72
Foreground program

Operates as while loop:
while (TRUE) {
read_buttons(button_values);
process_command(button_values);
check_alarm();
}
Computing Platform-73
Testing

Component testing:



test interrupt code on the platform;
can test foreground program using a mock-up.
System testing:



relatively few components to integrate;
check clock accuracy;
check recognition of buttons, buzzer, etc.
Computing Platform-74