Transcript Open64-Intro

An Introduction to Open64
Compiler
Guang R. Gao (Capsl, Udel)
Xiaomi An (Capsl, Udel)
Curtsey to Fred Chow
Outline
• Background and Motivation
• Part I: An overview of the Open64 compiler
infrastructure and design principles
• Part II: Using Open64 in compiler research
& development
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What is The Original
Open64 (Pro64) ?
• A suite of optimizing compiler tools for
Intel IA-64, x86-64 on Linux systems
• C, C++ and Fortran90/95 compilers
• Conforming to the IA-64, x86-64 Linux
ABI and API standards
• Open to all researchers/developers in
the community
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Historical Perspectives
Stanford RISC
compiler research
Cydrome Cydra5
Compiler
1980-83
MIPS Ucode
Compiler (R2000)
Software
pipelining
1989
Global opt
under -O2
SGI Ragnarok
Floating-pt
Compiler (R8000) performance
1987
1994
MIPS Ucode
Compiler (R4000)
Loop opt
under -O3
1991
Stanford SUIF
Rice IPA
SGI MIPSpro
Compiler (R10000)
1997
Curtsey to Fred Chow
Pro64/Open64
Compiler (Itanium)
2000
Who Might Want to Use
Open64?
• Researchers : test new compiler
analysis and optimization algorithms
• Developers : retarget to another
architecture/system
• Educators : a compiler teaching
platform
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Who Are Using Open64 – from ACM CGO 2008 Open64 Workshop
Attendee List (April 6, 2008, Boston)
12 Companies: Google,
nVidia, IBM, HP, Qualcomm,
AMD, Tilera, PathScale,
SimpLight, Absoft,
Coherenet Logix, STMicro,
9 Education Institutes: USC,
Rice, U. of Delaware, U.
Houston, U. of Illinois,
Tsinghua, Fudan, ENS Lyon,
NRCC,
Abramson
Adhianto
Bagley
Boissinot
Cavazos
Chakrabarti
Chen
Chow
Danalis
Dasgupta
DE
Eachempati
Gan
Gao
Gottlieb
Guillon
Hundt
Jain
Ju
Linthicum
Ma
McIntosh
Murphy
Narayanan
Özender
Ramasamy
Rastello
Ributzka
Ryoo
Schafer
Wang
Ye
Zheng
Zhou
Zhou
Jeremy D
Laksono
Richard
Benoit
John
Gautam
Tong
Fred
Antonios G
Anshuman
Subrato K
Deepak
Ge
Guang
Robert
Christophe
Robert
Suneel
Roy
Charles A.
Yin
Nathaniel
Michael P
Kannan
M. Serhat
Vinodha
Fabrice
Juergen
Shane
Uriel
Xu
Handong
Bixia
Hucheng
Xing
Univ of Southern California
Rice University
AMD
ENS Lyon
University of Delaware
PathScale, LLC.
IBM
PathScale, LLC
University of Delaware
Qualcomm, Inc.
Qualcomm, Inc.
University of Houston
University of Delaware
University of Delaware
Tilera Corporation
STMicroelectronics
Google
Hewlett Packard
AMD
Qualcomm, Inc.
Absoft
Hewlett Packard Company
NVIDIA
Coherent Logix, Inc.
NRCC
Google, Inc.
LIP, ENS Lyon
University of Delaware
University of Illinois
Hewlett-Packard
University of Delaware
University of Delaware
AMD
Tsinghua University
Tsinghua University
Redondo Beach
Houston
Marlborough
Lyon
Newark
Sunnyvale
Yorktown Heights
Fremont
Newark
Austin
San Diego
Houston
Newark
Newark
Westborough
Grenoble
Palo Alto
Los Gatos
Sunnyvale
Austin
Rochester Hills
Lexington
Newark
Milpitas
Istanbul
Mountain View
Lyon
Newark
Urbana
Silver Spring
Newark
Newark
Sunnyvale
Beijing
Beijing
USA
USA
USA
FRANCE
USA
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FRANCE
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TURKEY
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FRANCE
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CHINA
CHINA
Vision and Status of Open64 Today ?
• People should view it as GCC with an alternative
backend with great potential to reclaim the best
compiler in the world
• The technology incorporated all top compiler
optimization research in 90's
• It has regain momentum in the last three years
due to Pathscale and HP's investment in
robustness and performance
• Targeted to x86, Itanium in the public repository,
ARM, MIPS, PowerPC, and several other signal
processing CPU in private branches
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Overview of Open64
Infrastructure
• Logical compilation model and
component flow
• WHIRL Intermediate Representation
• Very High Optimizer
• Inter-Procedural Analysis (IPA)
• Loop Nest Optimizer (LNO) and
Parallelization
• Global optimization (WOPT)
• Code Generation (CG)
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Front end
Very High Optimizer
Interprocedural Analysis and Optimization
Good IR
Loop Nest Optimization and Parallelization
Global (Scalar) Optimization
Middle-End
Backend
Code Generation
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Front Ends
• C front end based on gcc
• C++ front end based on g++
• Fortran90/95 front end from MIPSpro
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Semantic Level of IR
At higher level:
Source program High
•More kinds of constructs
•Shorter code sequence
•More program info present
•Hierarchical constructs
•Cannot perform many optimizations
At lower level:
•Less program info
•Fewer kinds of constructs
Machine
instruction
Low
•Longer code sequence
•Flat constructs
•All optimizations can be performed
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Compilation Flow
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Very High WHIRL Optimizer
Lower to High WHIRL while performing optimizations
First part deals with common language constructs
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Bit-field optimizations
Short-circuit boolean expressions
Switch statement optimization
Simple if-conversion
Assignments of small structs: lower struct copy to
assignments of individual fields
 Convert patterns of code sequences to intrinsics:
• Saturated subtract, abs()
 Other pattern-based optimizations
• max, min
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Roles of IPA
The only optimization component operating at program
scope
• Analysis: collect information from entire program
• Optimization: performs optimizations across procedure
boundaries
• Depends on later phases for full optimization effects
• Supplies cross-file information for later optimization
phases
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IPA Flow
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IPA Main Stage
Analysis
– alias analysis
– array section
– code layout
Optimization
– inlining
– cloning
– dead function and variable
elimination
– constant propagation
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Loop Nest Optimizations
1. Transformations for Data Cache
2. Transformations that help other
optimizations
3. Vectorization and Parallellization
LNO Transformations for Data
Cache
Cache blocking
 Transform loop to work on sub-matrices that fit in
cache
Loop interchange
Array Padding
 Reduce cache conflicts
Prefetches generation
 Hide the long latency of cache miss references
Loop fusion
Loop fission
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LNO Transformations that
Help Other Optimizations
Scalar Expansion / Array Expansion
 Reduce inter-loop dependencies, enable parallelization
Scalar Variable Renaming
 Less constraints for register allocation
Array Scalarization
 Improves register allocation
Hoist Messy Loop Bounds
Outer loop unrolling
Array Substitution (Forward and Backward)
Loop Unswitching
Hoist IF
Inter-iteration CSE
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LNO Parallelization
• SIMD code generation
– Highly dependent on the SIMD instructions in target
• Generate vector intrinsics
– Based on the library functions available
• Automatic parallelization
– Leverage OpenMP support in rest of backend
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Global Optimization Phase
• SSA is unifying technology
• Open-64 extension to SSA technology
– Representing aliases and indirect memory
operations (Chow et al, CC 96)
– Integrated partial redundancy elimination
(Chow et al, PLDI 97; Kennedy et al, CC 98, TOPLAS 99)
– Support for speculative code motion
– Register promotion via load and store
placement (Lo et al, PLDI 98)
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Overview
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Works at function scope
Builds control flow graph
Performs alias analysis
Represents program in SSA form
SSA-based optimization algorithms
Co-operations among multiple phases to achieve final effects
Phase order designed to maximize effectiveness
Separated into Preopt and Mainopt
– Pre-opt serves as pre-optimizing front-ends for LNO and IPA
(in High WHIRL)
• Provide use-def info to LNO and IPA
• Provide alias info to CG
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Optimizations Performed
Pre-optimizer
 Goto conversion
 Loop normalization
 Induction variable
canonicalization
 Dead store elimination
 Copy propagation
 Dead code elimination
 Alias analysis (flow-free
and flow-sensitive)
 Compute def-use chains for
LNO and IPA
 Pass alias info to CG
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Main optimizer
 Partial redundancy elimination
based on SSAPRE framework
o Global common subexpression
o Loop invariant code motion
o Strength reduction
o Linear function test
replacement
 Value-number-based full
redundancy elimination
 Induction variable elimination
 Register promotion
 Bitwise dead store elimination
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Feedback
Used throughout the compiler
• Instrumentation can be added at any stage
• VHO, LNO, WOPT, CG
• Explicit instrumentation data incorporated
where inserted
• Instrumentation data maintained and checked
for consistency through program
transformations.
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WHIRL
WHIRL-to-TOP
CGIR
Extended
basic block
optimization
Control
Flow
optimization
Hyperblock Formation
Critical Path Reduction
Inner Loop Opt
Software Pipelining
IGLS
GRA/LRA
Information from Front end
(alias, structure, etc.)
Smooth Info
flow into Backend
in Pro64
Code Emission
Executable
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Software Pipelining
vs
Normal Scheduling
a SWP-amenable
loop candidate ?
Yes
IGLS
Inner loop processing
software pipelining
GRA/LRA
Failure/not profitable
Success
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No
IGLS
Code Emission
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Code Generation Intermediate
Representation (CGIR)
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•
TOPs (Target Operations) are “quads”
Operands/results are TNs
Basic block nodes in control flow graph
Load/store architecture
Supports predication
Flags on TOPs (copy ops, integer add, load, etc.)
Flags on operands (TNs)
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From WHIRL to CGIR
Cont’d
• Information passed
– alias information
– loop information
– symbol table and maps
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The Target Information Table
(TARG_INFO)
Objective:
• Parameterized description of a target
machine and system architecture
• Separates architecture details from the
compiler’s algorithms
• Minimizes compiler changes when
targeting a new architecture
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WHIRL SSA:
A New Optimization Infrastructure for Open64
Parallel Processing Institute, Fudan University, Shanghai, China
Global Delivery China Center, Hewlett-Packard, Shanghai, China
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Goal
• A better “DU manager”
– Factored UD chain
• Reduced traversing overhead
– Keeping alias information
• Handle both direct and indirect access
• Eliminate ‘incomplete DU/UD chain’
• Easy to use
– STL-style iterator to traverse the DU/UD chain
• A flexible Infrastructure
– Available from H WHIRL to L WHIRL
– Lightweight, demand-driven
– Precise and updatable
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PHI Placement
• For SCF, φ nodes are mapped on the root WN
• For GOTO-LABEL, φ nodes are placed on the LABEL
IF
a3ß φ(a1,a2)
if(p1)
a1 ß
a 2ß
a3ß φ(a1,a2)
if(p1) a1ß
a1ß
while(p1) a2ß φ(a1,a3)
a3ß
a2ß
(a) IF
a2ß φ(a1,a3)
a 3ß
DO_WHILE
a2ß φ(a1,a3)
CMP
I1ß
DO_LOOP
I2ß φ(I1,I3)
I2ß φ(I1,I3)
BODY
while(p1)
p1
(c) DO_WHILE
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a3ß
p1
(b) WHILE_DO
INIT
a 1ß
WHILE_DO
a2ß φ(a1,a3)
a3ß
CMP
STEP I3=op(I2)
I
I1ß
I3ß op(I2)
BODY
(d) DO_LOOP
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Thank you!
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