Low Density Parity Check (LDPC) Code Implementation Matthew Pregara & Zachary Saigh Advisors: Dr. In Soo Ahn & Dr. Yufeng Lu Dept. of Electrical and Computer Eng.

2

Contents

       Background and Motivation Linear Block Coding Example Hard Decision Tanner Graph Decoding Constructing LDPC Codes Soft Decision Decoding Results Conclusion

3

Background

 ARQ: Automatic Repeat Request  Detects errors and requests retransmission  Example: Even or Odd Parity  FEC: Forward Error Correction  Detects AND Corrects Errors  Examples:  Linear Block Coding  Turbo Codes  Convolutional Codes

Why LDPC?

 Low decoding complexity  Higher code rate  Better Error performance  Industry standard for:  802.11n Wi-Fi  Digital Video Broadcasting  WiMAX and 4G 4

5

Performance Comparison

(taken from [1])

6

Project Goals

 Create LDPC code system simulation with MATLAB/Simulink  Implement a scaled down LDPC system on a FPGA using Xilinx System Generator  Complete System performance comparison between MATLAB/Simulink and FPGA implementation

7

Linear Block Coding

 Block Codes are denoted by (n, k).

 k = message bits (message word)  n = message bits + parity bits (coded bits)  # of parity bits: m = n - k  Code Rate R = k/n  Ex: (7,4) code  4 message bits  +3 parity bits  = 7 coded bits  Code rate R = 4/7

8

Hamming Code Example

m Transmitter G (encoder matrix) Channel Receiver u e + r r H’ (decoder matrix) S Error Lookup Table + e u’ Remove Parity bits m’ e = error pattern m = message bit word u = code word r = received code word with error S = syndrome u’ = corrected code word m’ = received message word

9

Constructing Hamming Code

 Factor x n +1  Populate G matrix (k x n) with shifted factor  Take reduced row echelon form to find Systematic G matrix from G matrix  H matrix is obtained by manipulating the systematic G matrix.

10

Encoding Example

 1 0 1 1   1   0   0  0 0 1 0 0 0 0 1 0 0 0 0 1   1 0 1 1 p 1 p 2 1 0 1 1 1 1 1 0 0 1 1 1       p 3  p p 2 p 3 1    m m m 2 1 1   m  m 2 m 3 3   m 4 m 3  m 4  1  1  1  1  0  1  1  0  0  1  1  0   1 0 1 1 1 0 0 

Decoding

 S = rcvd. code word × H T 11  m 1 m 2 m 3 m 4 p 1 p 2 p 3   1   0  1  1     1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1           

S S

2

S

3 1 

S

1

S

2

S

3     m 1  m 1  m 2  m 3 m m 2 3    m 4 m m 3 4    p 1 p p 2 3

12

Correcting Errors

  In this case the 2 nd bit is corrupted Invert the corrupted bit according to the location found by the syndrome table   

1 0

 

1 1 1

S

0 1



0 1



0 1 1



1 0 1 1 1 0 0 0 0 0



0 0

 

13

Tanner Graph and Hard Decision Decoding

(8,4) Example (2458) C 1 (1236) C 2 (3678) C 3 (1457) C 4 V 1 V 2 V 3 V 4 V 5 V 6 V 7 V 8 H  V 1  0   1   0 1 V 2 1 1 0 0 V 3 0 1 1 0 V 4 1 0 0 1 V 5 1 0 0 1 V 6 0 1 1 0 V 7 0 0 1 1 V 8 1 0 1 0      C 1 C 2 C 3 C 4

14 C 1 C 2 C 3 C 4

Hard Decision Decoding

V 5 V 6 V 7 V 8 V 1 V 2 V 3 V 4 0 1 0 1 1 1 0 1

Check Nodes

C 1 C 2 C 3 C 4 Receive Send Receive Send Receive Send Receive Send V 2 → 1 0 → V 2 V 1 → 1 0 → V 1 V 3 → 0 0 → V 3 V 1 → 1 1 → V 1

Activities

V 4 → 1 0 → V 4 V 2 → 1 0 → V 2 V 6 → 1 1 → V 6 V 4 → 1 1 → V 4 V 5 → 0 1 → V 5 V 3 → 0 1 → V 3 V 7 → 0 0 → V 7 V 5 → 0 0 → V 5 V 8 → 1 0 → V 8 V 6 → 1 0 → V 6 V 8 → 1 1 → V 8 V 7 → 0 0 → V 7

15 C 1 C 2 C 3 C 4

Hard Decision Decoding

V 5 V 6 V 7 V 8 V 1 V 2 V 3 V 4 0 1 0 1 1 1 0 1

Check Nodes

C 1 C 2 C 3 C 4 Receive Send Receive Send Receive Send Receive Send

Update

V 2 → 1 0 → V 2 V 1 → 1 0 → V 1 V 3 → 0 0 → V 3 V 1 → 1 1 → V 1

Activities

V 4 → 1 0 → V 4 V 2 → 1 0 → V 2 V 6 → 1 1 → V 6 V 4 → 1 1 → V 4 V 5 → 0 1 → V 5 V 3 → 0 1 → V 3 V 7 → 0 0 → V 7 V 5 → 0 0 → V 5 V 8 → 1 0 → V 8 V 6 → 1 0 → V 6 V 8 → 1 1 → V 8 V 7 → 0 0 → V 7

C 1 C 2 C 3 C 4

Hard Decision Decoding

V 5 V 6 V 7 V 8 V 1 V 2 V 3 V 4 0 1 0 1 1 1 0 1

Check Nodes

C 1 C 2 C 3 C 4 Receive Send Receive Send Receive Send Receive Send V 2 → 1 0 → V 2 V 1 → 1 0 → V 1 V 3 → 0 0 → V 3 V 1 → 1 1 → V 1

Activities Update

V 4 → 1 0 → V 4 V 2 → 1 0 → V 2 V 6 → 1 1 → V 6 V 4 → 1 1 → V 4 V 5 → 0 1 → V 5 V 3 → 0 1 → V 3 V 7 → 0 0 → V 7 V 5 → 0 0 → V 5 V 8 → 1 0 → V 8 V 6 → 1 0 → V 6 V 8 → 1 1 → V 8 V 7 → 0 0 → V 7

C 1 C 2 C 3 C 4

Hard Decision Decoding

V 5 V 6 V 7 V 8 V 1 V 2 V 3 V 4 0 1 0 1 1 1 0 1

Check Nodes

C 1 C 2 C 3 C 4 Receive Send Receive Send Receive Send Receive Send V 2 → 1 0 → V 2 V 1 → 1 0 → V 1 V 3 → 0 0 → V 3 V 1 → 1 1 → V 1

Activities

V 4 → 1 0 → V 4 V 2 → 1 0 → V 2 V 6 → 1 1 → V 6 V 4 → 1 1 → V 4

Update

V 5 → 0 1 → V 5 V 3 → 0 1 → V 3 V 7 → 0 0 → V 7 V 5 → 0 0 → V 5 V 8 → 1 0 → V 8 V 6 → 1 0 → V 6 V 8 → 1 1 → V 8 V 7 → 0 0 → V 7

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Variable Node Decisions

Variable Nodes

V 1 V 2 V 3 V 4 V 5 V 6 V 7 V 8

y i

1 1 0 1 0 1 0 1

Messages from Check Nodes

C 2 → 0 C 1 → 0 C 2 → 1 C 1 → 0 C 1 → 1 C 2 → 0 C 3 → 0 C 1 → 0 C 4 → 1 C 2 → 0 C 3 → 0 C 4 → 1 C 4 → 0 C 3 → 1 C 4 → 0 C 3 → 1

Decision

1 0 0 1 0 1 0 1

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Differences of LDPC Code

 Construct H matrix first  H is sparsely populated with 1s  Fewer edges → less computations  Find the systematic H and G matrices  G will not be sparse

20

Soft Decision Decoding

 Uses Tanner Graph representation with an iterative process  No “hard-clipping” of received code word  2dB performance gain over hard decision [2]

21

High Level LDPC System Block Diagram

Transmitter m Encoder Matrix G u Channel e + r Receiver LDPC Decoder u’ Remove Parity bits m’ e = error pattern m = message bit word u = code word r = received code word with error S = syndrome u’ = corrected code word m’ = received message word

22

Soft Decision Decoder Diagram

-7.11158

-1.5320

-0.3289

5.7602

2.7111

0.4997

-5.1652

1.5357

-5.0942

1.2526

1 6 7 8 4 5 2 3 9 10 23 1 4 5 2 3

-7.11158

1 Re-Calculate Each Edge 24 -1.5320

-0.3289

5.7602

2.7111

0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 4 5 2 3 -1.5320

5 3 4 1 2

-7.11158

1 Re-Calculate Each Edge -1.5320

2

-1.5320

-0.3289

3 5.7602

2.7111

4 5 0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 1 2 3 4 5

-7.11158

1 Re-Calculate Each Edge -1.5320

-0.3289

5.7602

2.7111

0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 4 5 2 3 5 1 2 3 4

-1.5320

Update Algorithm

SUM

-7.11158

1 Re-Calculate Each Edge -1.5320

-0.3289

5.7602

2.7111

0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 4 5 2 3 5 1 2 3 4

-0.3289

Update Algorithm

SUM

-7.11158

1 Re-Calculate Each Edge -1.5320

-0.3289

5.7602

2.7111

0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 4 5 2 3 5 1 2 3 4

5.7602

Update Algorithm

SUM

This Updated Value is Sent back to Variable Node 1

0.2096

-7.11158

1 Re-Calculate Each Edge -1.5320

-0.3289

5.7602

2.7111

0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 4 5 2 3 1 2 3 4 5

-7.11158

1 Re-Calculate Each Edge -1.5320

-1.5320

-0.3289

5.7602

2.7111

4 5 2 3 0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 1 2 3 4 5

-7.11158

1 Re-Calculate Each Edge -1.5320

-0.3289

5.7602

2.7111

0.4997

6 -5.1652

7 1.5357

8 -5.0942

1.2526

9 10 4 5 2 3 -1.5320

1 2 3 4 5

32

Decoding Algorithm

 Phi function:   Difficult to implement on a FPGA Solutions:   Find an approximation Construct lookup table

33

Lookup table Approach

Note: all inputs are >=0

34

Simulation Results

35

Simulink LDPC System

Encoder Comparison 36

38

Encoder with Xilinx blocks

38

Co-Simulation Results

39

Xilinx LDPC Decoder

40 Decoder Control Logic

41 Check Node Implementation

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Conclusion

 MATLAB/Simulink simulation of LDPC system has been completed.

 An efficient approximation of decoding algorithm has been developed for hardware implementation.

 Xilinx System generator design for the decoder has been constructed.

 Comparison and verification has not been completed for those results from MATLAB and Xilinx system generator.

 FPGA implementation and a scaled up system may not be completed.

43

References

[1] Valenti, Matthew. Iterative Solutions Coded Modulation Library Theory of Operation. West Virginia University, 03 Oct. 2005. Web. 23 Oct. 2012. . [2] B. Sklar, Digital Communications, second edition: Fundamentals and Applications, Prentice-Hall, 2000.

[3] Xilinx System Generator Manual, Xilinx Inc. , 2011.

Questions?

44

Appendix

45

46

Matrix Manipulation



47 Reducing Decoding Complexity  Square_add function: y = max_star(L1,L2) - max_star(0, L1+L2);  MAX* function: if (L1==L2) y = L1; return ; end ; y = max(L1,L2) + log(1+exp(-abs(L1-L2))); end ;

48  Reducing Decoding Complexity This: y = max(L1,L2) + log(1+exp(-abs(L1-L2)));  Becomes Approximated MAX* function: x = -abs(L1-L2); if ((x<2) && (x>=-2)) y = max(L1,L2) + 3/8; else y = max(L1,L2); end ;  No costly log function

In Practice 49 Using MATLAB’s Code Profiler… MAX* function takes: 25.85s of simulation Approx. MAX* function takes: 28.02s of equally sized simulation Difference of 2.17s

Simulation Results 50    (10,5) Code 1000 codewords per datapoint, or 10,000 bits

50

Timeline

Feb 11, 2013 MATLAB Implementation Mar 4, 2013 Xilinx System Generator Model Feb 25, 2013 Performance Analysis Apr 2, 2013 FPGA Implementation Mar 29, 2013 Student Expo Abstract Due Apr 15, 2013 - Apr 19, 2013 Student Expo Apr 21, 2013 Design Scaling May 9, 2013 - May 15, 2013 Project Presentations Feb 1, 2013 Jan 28, 2013 Mar 1, 2013 Apr 1, 2013 May 1, 2013 May 15, 2013

52

Division of Labor

   

Zack

Simulink Model Xilinx System generator design of decoder Implementation of VHDL on FPGA Performance analysis of FPGA implementation    

Matt

MATLAB Simulation Error Performance Analysis Xilinx System generator design of encoder Performance analysis of MATLAB/Xilinx implementation